Elyse Rosenbaum, Peter M. Lee, Reza P. K. KO, and C. Hu · Elyse Rosenbaum, Peter M. Lee, Reza Moazzami, P. K. KO and C. Hu ... ust be (7) i com- (8) one of lculate accu- late of

BERT - CIRCUIT OXIDE RELIABILITY

SIMULATOR (CORS)

by

Elyse Rosenbaum, Peter M. Lee, Reza Moazzami, P. K. KO, and C. Hu

Memorandum No. UCB/ERL M90/4

8 January 1990

BERT - CIRCUIT OXIDE RELIABILITY

SIMULATOR (CORS)

by

Elyse Rosenbaum, Peter M. Lee, Reza Moazzami, P. K. KO, and C. Hu

Memorandum No. UCBERL M9014

8 January 1990

ELECTRONICS RESEARCH LABORATORY

College of Engineering University of California, Berkeley

94720

BERT - CIRCUIT OXIDE RELIABILITY SIMULATOR (CC

Elyse Rosenbaum, Peter M . Lee, Reza Moazzami, P . K . KO and C. Hu

Department of Electrical Engineering and Computer Science University of Califomia

Berkeley, CA 94720

Abstract

CORS (Circuit Oxide Reliability Simulator) is a fully integrated part of BERT (I Reliability Tools). CORS projects the probability of oxide breakdown induced circuit i a function of operating time, temperature, power supply voltage and input waveforms can also simulate the effects of bum-in on subsequent yield and lifetime. The user is to provide the simulator with test capacitor breakdown statistics.

This work was funded by SRC, Sandia Laboratories and ISTO/SDIO administered througl ONR under contract NooO19-85-K-0603.

:S)

rkeley

CORS quired

U R as

Table of Contents

I . Introduction .................................................................................................................. II . Circuit Failure Model and Implementation .................................................................

A . Oxide Breakdown Model .................................................................................. B . Temperature Dependence of Oxide Breakdown ................................................ C . Determination of V, (t) ..................................................................................... D . Calculation of & ............................................................................................. E . Calculation of tgD after Bum-In ........................................................................ F . Failure Probability Calculations .........................................................................

111 . Characterizing Defect Density using Program DEFEm ............................................. A . Using DEFECT to Obtain Area Density of Defects .......................................... B . Using DEFECT to Obtain Defect Density per Unit Length ..............................

IV . CORS Command Summary ........................................................................................ A . Ini!oke CORS (.l'TF card) ................................................................................. B . Associate Device Model with Defect Density Datafile (.XEFF card) ................

D . MOSFETs .......................................................................................................... E . The . ALTMODEL card .....................................................................................

G . Project Failures for Large Circuits with Identical Cells (.=I card) .................. H . Simulate Bum-In (.BURNIN card) .................................................................... I . .TR .AN card ........................................................................................................ J . Temperature Setting (.OFTIONS card) ...............................................................

V . Examples ...................................................................................................................... References ......................................................................................................................... Appendix A . CORS Simulations ...................................................................................... Appendix B . Error Messages ............................................................................................ Figures and Examples .......................................................................................................

C . Capacitors ...........................................................................................................

F . Print Failure Probability for each Device (.EACHPROB card) ..........................

...

...

...

... 1..

...

2 3 3 3 4 5 6 6 8 8

10 12 12 13 13 13 14 14 14 15 15 15 16 17 18 19 25

- 2 -

L Introduction

CORS (Circuit Oxide Reliability Simulator) is a fully integrated part of BERT (B Reliability Tools). CORS projects the probability of oxide breakdown induced circuit fi a function of operating time, temperature, power supply voltage and input waveforms. can also simulate the effects of bum-in on subsequent yield and lifetime The user is 1 to provide the simulator with test capacitor breakdown statistics and an input decl describes the circuit using SPICE commands. The input deck will also contains co1 which instruct BERT to execute the CORS module. The input deck may also contain C electron module) and EM (electromigration module) specific commands [1][2]. CORS of a pre- and post-processor for SPICE; Figure 1 shows a block diagram.

Appendix A should be read by the user unfamiliar with the capabilities of COR appendix discusses the capabilities of CORS and provides the user with several exan CORS output. Section 11 discusses the equations implemented in CORS. Section III d the procedure for obtaining test capacitor breakdown data and also details the use of 1 DEFECT which is provided to the user along with BERT. DEFECT formats test c breakdown data for use by CORS. Section IV contains the actual user’s guide for al CORS commands. Finally, Section V contains examples of BERT input decks co CORS commands and the corresponding output listings. The user who needs informi executing BERT, should obtain a copy of [ 13.

lrkeley lure as CORS :quired which lmands rS (hot onsists

i. This ples of scribes mgram pacitor of the

ion on taining

- 3 - I

T has units of KO. Default values of G300, 5 m , 6 and &, are provided or the user may values derived from intrinsic oxide studies of his/her technology (Section IVA).

II. Circuit Failure Model and Implementation

A. Oxide Breakdown Model

(5)

provide

Oxide intrinsic lifetime (tBD) is [3]

(1)

where GX is oxide thickness, V, is oxide voltage, G and z are propomonality co tants. Large area capacitors generally experience "defect-related" breakdown which causes f to have a nondeterministic lifetime. Defect-related breakdown is modeled as [4]

Note that the random variable & has been substituted for & in the above probability that a device undergoes oxide breakdown before a given ~ B D is bility that the oxide contains a specific value of X& This is discussed in

Using a quasi-static approach, we have extended this model for this section.

voltages [5 ] ,

. Inside CORS, V,(t) is derived from SPICE node voltages and the integral evaluated numerically using the Trapezoidal Rule. The integral is not actually large tgD, such as 10 years; instead, it is evaluated for the period, T, of SPICE

~ B D T

then multiplied by a factor of -. This places a constraint on the simulation results; derived assuming repetitive input waveforms.

B. Temperature Dependence of Oxide Breakdown

Time-to-breakdown (tgD) decreases with increasing operating temperature The parameters in (3) are temperature dependent to account for this effect [6]. Specifically, are defined as follows.

-% 1 s ( T ) = ~ ~ ~ e x p - - -- I [ kB [. im]] I

(4)

- 4 -

C. Determination of V,(t)

The voltage drop acmss a capacitor oxide is set equal to

V,(t) = Vdt) - V20) where Vl(t) and V2(t) are the SPICE node voltages for the capacitor electrodes. It is i that both electrodes are made from similar materials (so there is no work function dif and that both electrodes are highly conductive (so there is no voltage drop across a d region). These are reasonable assumptions for VLSI capacitors.

The voltage drop across a MOSFET oxide is not as straightforward to determj voltage drop across the substrate depletion region must be accounted for and work differences must be considered. Furthermore, when current flows along the channel, face potential becomes a function of position and, consequently, so does the oxide field. In the first release of CORS, the position dependence of the oxide field along a N channel is neglected and the oxide voltage is set equal to the maximum of Vgs and Vg, the depletion region voltage drop. Specifically, the oxide voltage along the channel i lated as follows.

N-channel MOSFET

Inversion (Vgs > VJ: Surface potential is near conduction band edge when there is appreciable gate current fore, v o x = I V g s - h n s - 5 - A 2 I

where @ equals the SPICE parameter PHI (surface potential) and em; is the work difference between the gate and substrate,materials.

Accumulation (V, - v b < vfi ): Surface potential is near valence band edge when there is appreciable gate current. The1 vox= I vg-vb-t$m;+$-l E I

2

Depletion: vox = 0.0

P-channel MOSFET

Inversion (V, VJ: E 2 2

v, = I vgs - + 2 + I

Depletion: v, = 0.0

;med :rem) pletion

Le. The lnction he sur- electric ISFET minus calcu-

There-

lnction

:fore,

- 5 -

Examination of these equations will show that the difference between the applied and 1 voltage is zero or Eg, depending on the gate material employed and the operating Additionally, the oxide voltage along the device edges must be calculated for the user 7

vides the simulator with statistics for defect density per unit length along diffusion oxide edges. V, along the field oxide edges is identical to that in the ChanneL The fit source/drain edges is different from that in the channel because these regions have a surface potential from the channel region due to the different carrier concentrations a The voltage at a diffusion, (say, drain) edge is calculated as follows.

N-channel MOSFET

p + po€y gate: Vox = I Vd - Vg + Eg I

P-channel MOSFET

n+ poly gate: Vox = I Vg - vd + Eg I

D. Calculation of Xa

For a given time-to-breakdown (tgD), X, is calculated from (3) using Newton-R method. The X& thus derived is the maximum thickness (least severe defect) predicted to fail by tBD. This calculation is repeated for eight different values of tB1 calculations take up the bulk of the CORS computation time. An alternative algorithl "quick," has been added for the user who wishes to reduce execution time and is v sacrifice some accuracy (about 2% - see section V). The quick algorithm replaces a sion of the form f (Vox(t)) with an expression of the form A*f (V,,J. When 'I(

desired, CORS calculates X,, corresponding the smallest tBD from (3); these are den and t:D. The remaining G s are calculated directly using

: oxide egime. 10 pro- d field I at the fferent types.

hson's lich is These called

r i g to :xpres- ick is ed X&

(6)

- 6 -

E. Calculation of tgD after Burn-In

Circuit lifetime after bum-in may be projected by using CORS in a two-pass moc tion N.H). During the first pass. SPICE provides CORS with the node voltages durh in; during the second pass, SPICE provides CORS with the node voltages under normal ing conditions. If bum-in is performed, the expression for predicted lifetime, (3). I modified to account for oxide wear incurred during the bum-in process [7].

This equation is implemented in CORS using an approximation to save storage space a~ putation time. With the approximation, the equation becomes

where Xbi is the maximum X, screened out by the bum-in trial (calculated during pas! CORS). (8) is solved for X, using Newton-Raphson's method.

The user may choose to invoke a "quick algorithm, rather than using (8), to c &. Accuracy is sacrificed, typically on the order of 50% (see Section V). This loss racy will be acceptable the user who is only interested in an order-of-magnitude esti failure probability. "Quick always ern on the consewative side. If "quick has been i the simulator calculates x b i during the first pass. It also calculates a bi during the pass, which is the X, that would correspond to t& if no bum-in had been performed. proceeds to calculate X, using

F. Failure Probability Calculations

CORS assumes that defects are distributed uniformly and independently across wafers and actual circuits. This allows the use of the Poisson distribution to describe th density (see Section IIl). The probability that a device fails at or before a specifia equal to the probability that the device contains one or more defects of size & or where X, was calculated from (3) for the specified tgD. Using the Poisson distributi probability may be expressed as

-m&d P (failwe) = 1 - e

where D&) is the area density of defects size & or smaller (recall smaller Xd's a severe defects) which has been provided by program DEFECT (Section III).

: (Sec- burn-

>perat- ust be

(7)

i com-

(8)

one of

lculate accu-

late of voked, second corn

(9)

he test defect

maller, a, this

(10) z more

tBD is

t

- 7 -

The probability that a circuit fails at or before time tgD is equal to the pmbabilii least one device in the circuit fails by time tgD. This may be expressed as

P (circuit failure) = 1 - fie-- i l

where n is the number of MOS devices in the circuit, D( X& ) is the defect density fi device and x,& yields tgD for the particular waveform found at device i.

to account for the circuits lost during the bum-in test. The expression for failure pr after bum-in is

When a bum-in hid is simulated in addition to normal operation, (11) must be

n P (circuit failure) = n e - w b i l e

where xii is calculated for device i Mrn (3) with tgD set equal to the bum-in duration, is calculated for device i from (8).

- 8 -

IIL Characterizing Defect Density using Program DEFECT

A. Using DEFECT to Obtain Area Density of Defects

DEFECT takes raw data from a test capacitor breakdown experiment and format use by CORS. There are two commonly used methods for characteking oxide brei statistics, the time-to-breakdown test and the ramp-voltage-breakdown test. DEFEC accept data from either of these experiments. In the absence of experimental data, t may provide DEFECT with parameters for a statistical distribution which is tho1 represent the oxide breakdown statistics.

A time-to-breakdown test is performed by applying a constant voltage to an ensei identical large-area capacitors. The oxide voltage used is larger than the designed pow ply voltage because one wishes to obsexve failures in a short amount of time (see e (2)). The fraction of devices which have failed is recorded as a function of time. FI observed breakdown time, DEFECT derives X a using (2). Next, DEFECT obtains t density, D&,), from (10). An ordered list of XcEl versus D G ) is generated by DEFE is stored in a user-named output file which will be referenced by a .XEFF card in the input deck (Section 1V.B). Following is a description of the format in which t breakdown data should be placed in the DEFECT input file.

Line 1: Oxide Thickness (A)

L i e 2: Area of test structure (an2>

Line 3: Test temperature (CO)

Line 4: 0.0 The value 0.0 notijies DEFECT thut time-to-breakdown data will be provided

Line 5: Voltage difference between VWGd and V,. This value will be subtractedfiom V,w by DEFECT to yield V,. This value may be estimated using the equations in Section II.C.

Line 6: Vapplied (+ volts, the voltage applied to the test capacitor terminals)

Lines 7-: tBD (sec), cumulative percent failed Lines 7- should consist of ordered pairs ranging fromfrom minimum tBD on line 7 to the maximum on the final line of the fire.

A DEFECT input file listing containing time-to-breakdown data may be found in Exa and a DEFECT output file listing is provided in Example 2.

A ramp-voltage-breakdown test is performed by applying a linearly increasing waveform to an ensemble of identical large-area capacitors. A record of breakdown (VBD) versus the fraction of capacitors failed is generated.

; it for kdown rwill ie user ght to

ible of :r sup- pation lr each ie area JT and CORS me-to-

nple 1

voltage voltage

,

- 9 -

which can be derived from (3). DEFECT subsequently derives D(X& using (10). T file format needed for DEFECT to process rampvoltage-bddown data is as follows.


Line 2: Area of test structure (cm2)

Line 3: Test temperature (CO)

Line 4: Ramp rate (V/sec)

Line 5: Voltage difference between V,&d and V,. Vaw is the ramp voltage at a given time. The difference between this value and V, may be inferredfiom the equations in Section II-C. The value listed on line 5 will be subtractedfiom VBD.

Line 6: 0.0 This is a dummy number, not used by DEFECT when VBD is being provided.

Lines 7- VBD (volts), cumulative percent failure Lines 7- should consist of ordered pairs ranging from minimum VBD on line 7 to the largest observed VBD on the final line of thefile.

A DEFECT input file listing containing VBD data may be found in Example 3. The I output file will be similar to that shown in Example 2.

If test capacitor breakdown data is not available, yet a CORS projection of cira biIity is desired, the user may provide DEFECT with a statistical distribution which is to model the time-to-breakdown statistics for the oxide of interest. Specifically, the u describe hisher hypothetical breakdown data with a one or two population lognc Weibull distribution. The parameters for these distributions are placed in a file whicl input to DEFECT to be properly formated for use by CORS. The input file should mated as follows.


Line 2: Area of test svucture (an2)

Line 3: Test temperature (CO) The data on lines I-3 is, of course, hypotheticd

Line4: 0.0

(13)

: input

:FECT

t relia- :Eeved :r may mal or is then

for-

Line 5:

Line 6:

Line 7:

Line 8:

Line 9:

Line 10

Line 1 1:

- 10-

the voltage difference between VWEd (hypothetical) and V,. See format description for time-to-breakdown data (above) for an explanation.

Vappfid (+ volts. the voltage applied to the hypothetical test capacitors)

L o g I l O I m a l -or-

Weibull

Number of populations (1 or 2)

(if Lognormal) t50 median -or-

(if Weibul) alpha location parameter

(if Lognormal) sigma shape parameter -or-

(if Weibull) beta If line 8 reads "2", then the infomation contained on lines 9 and IO pertains to one population qf samples and the following lines must be included to describe the other population.

n n

Fraction of samples following distribution #1 A number between 0 and 1.

Line 12: (if Lognormal) t50 for population #2 -or-

(if Weibull) alpha n n

Line 13: (if Lognormal) sigma for population #2 -or-

(if Weibull) beta n n

*****All parameters have units of seconds.*****

A sample DEFECT input file following the above format is contained in Example 4 alo the generated output file.

B. Using DEFECT to Obtain Defect Density per Unit Length

The user may also wish to pmvide CORS with data about the defect density I length along diffusion and/or field oxide edges. We will describe two possible technic obtaining these defect densities. The first method is to conduct a breakdown test on an ble of test capaciton which have a very large ratio of perimeter to area If one can assu the probability that one of these capacitors encompasses a severe area defect is negligi user may simply substitute the perimeter of the structures (cm) on line 2 of the DEFEC

J with

r unit es for nsem- le that le, the input

- 11 -

file. DEFECT will then output D(X& values which have units of an-'. A second me determining the density of defects along edges is to conduct breakdown tests on two ex of capacitors, each with identical area but diffexent perimeter. The mathematics are as f

Y = 1 - F Y is yield, F is cumulative fraction failed Y, will represent the yield at some tgD (or V B ~ ) for structures with area A and peril while Y2 will represent the yield for structures with area A and perimeter P2 (PI > Pz).

y1= exp [AD* + PI41

1 y2 = exp [AD. + PZD~

The user should enter the value of p1-P~ on line 2 of the DEFECT input file and shorc the values of F' on line 7 and up.

hod for iembles uows.

eter P,

d place

- 12 -

IV. CORS Command Summary

A. Invoke CORS (.'ITF card)

Examples: .m .TTF G=300 TAU=lOp QUICK .TTF 3600 86400 2.59M 5.18M 7.77M 31.54M 63.07M.315G

The .TI'F card must be present for CORS to be invoked by BERT. If it is no input deck, all other CORS commands will be ignored. G and TAU, which character dependent dielectric breakdown for a particular technology, a= obtained by conduc intrinsic oxide breakdown study (instructions are included with Figure 2). EB and I which characterize the temperature acceleration of oxide breakdown, are obtained by c ing a study of the temperature dependence of breakdown (instructions are included witl 3). The inclusion of the QUICK option indicates that user wants the "quick algorit€ (detailed in Sections II.D and II.E) which decreases the CORS run-time with some accuracy. tIfD through t&) are the operating times for which the failure statistics will erated. If the user wishes to specify the values of tBD, he/she must specify a l l eight valu

name

G TAU EB DELTA QUICK -

parameter units

(3300 m/cm 9300 S e C

eV 6 eV

tlf D see tBD sec t;D sec ~ B D SeC G D SeC t$D SeC

t%D SeC

~ B D SeC

default

350

-28 .0167 not quick 1 month 3 months 6 months 1 Y= 2 Years 5 Y- 10 years 20 Years

1.OE-11

in the : time ng an iLTA, lduct- 5gure ! used )SS of : gen-

- 13 -

B. Associate Device Model with Defect Density Datafile (XEFF' card)

General form: .XEFF MNAME FILENAME=areadata cDlFFEDGE=diffdata> cOXEDGE=foxdati

Examples: .XEFF POLYCAF' FXLENWDEFDATA .XEFF NMOS1 FILENAME=MOSDATA DIFFEDGEDRAINDATA OXEDGE=(

MNAhE is the model name listed on a .MODEL (SPICE) or ALTMODEL card for a MOSFET or capacitor. There must be one .XEFF card for each MOSFE name defined in the input deck. Each capacitor which the user wishes included in th down projections will be associated with a model name which must also be f o i d in card. The file named after keyword FILENAME should contain defect density (cm' appropriate for devices described by M N M . The file named after keyword DIl should contain defect density (an-') data for the diffusion (source/drain) edges of a h or for the width-wise edges of a capacitor. The file named after keyword OXEDGI contain defect density (cm-') data for the field oxide edges of a MOSFET or the len edges of a capacitor. All data files should have been fomated by program DEFEm.

C. Capacitors

General form: SPICE 2 or 3:

O C X X X X X X N+ N- VALUE cIC=INCOND> OBDMODEL=MNAME klength

SPICE 3 only: CXXXMCXX N+ N- MNAME klength cW=width> cIC=INCOND> OE3DMODI

Examples: C14 0 1.4P TBDMODEL=CMODEL k l O U W=50U CABC 10 3 CAPMOD Ir lOU W=50U IC=5V TBDMODEkCAPMOD

A capacitor is included in the dielectric breakdown calculations only if the TBD; keyword is included on the card which defines the capacitor. If the first capacitor can illustrated above is used, then an .ALTMODEL card which defines MNAh4E must be in the deck.

D. MOSFETs

If the Level 1, 2 or 3 SPICE MOSFET model is being used, then no changes made to accommodate CORS. If the Level 4 model ( B S I M ) is being used, then an .A DEL card must be created for each model (or "process") name which appears on a h definition card.

>

D A T A

:CORS) ' model ~ break- .- ' ) data

%EDGE OSFET should

*-wise

IODEL format icluded

teed be -TMO- OSFET

- 14 -

E. The .ALTMODEL Card

General form: ALTMODEL MNAME TYPE <parameters>

Examples: .ALTMODEL NMl NMOS V T e . 7 GAMMAz.4 TOX=20N PHI=.6 -1 .ALTMODEL CAP1 C TOX=12.5N

MNAME is a model name which is also found on one or more MOSFET or c; definition cards. TYPE is the type of device, NMOS, PMOS or C (capacitor).

name parameter units default

VTO zero-bias threshold voltage V 1 .o TOX oxide thickness meter 1.Oe-7 GAMMA bulkthresholdparameter V 0.0 PHI surface potential V .6 TPG type of gate material: - 1

+1 opposite of substrate -1 same as substrate 0 Al gate

F. Print Failure Probability for each Device (.EACHPROB card)

General form:

Examples: .EACHPROB cNUItb

.EACHPROB

.EACHPROB 10

The .EACHPROB card, with no arguments following, appends a listing of the probability for each device to the CORS output. These individual failure probabilities culated for an operating time of tiD (default 10 years). If a value of NUM is specific the failure probabilities for just the NUM devices most likely to fail are provided.

G. Project Failures for Large Circuit with Identical Cells (.LSI card)

General form:

Example: .LSI <numb aum2> aum3>

LSI 256K 1M

The .=I card may be used to print out failure probabilities for large circuits wl constructed of cells identical to the circuit described in the input deck. The argumenu three) specify the number of cells in the large circuit@).

?acitor

failure re cal- l, then

&ale (UP to

- 15 -

H. Simulate Bum-In (.BURNIN card)

General form: .BURNIN dIME=bumtime> c'IEh4P=bumtemp>

Example: .BURNIN TIME=14400 -150

The presence of a .BURNIN card indicates that the user wishes to have the el bum-in simulated. The user may not request CAS or EM analysis along with burl other CORS commands are compatible with CAS and EM commands. TIME is the dw tbc bum-in trial, it has units of seconds. TEMP is the temperature (CO) during the trial.

To simulate bum-in, CORS must be run in a two-pass mode. During the first 1 user should adjust the power supply voltage values defined in the input deck to the vali during bum-in. If the user typically performs bum-in using different signal wavefon those during normal operation, the bum-in waveforms should be defined in the input d ing the first pass. During the second pass, the power supply voltage values define input deck should be set to their normal operating values and signal waveforms st those expected under normal conditions. Except for voltage source car&, the in1 should be identical during both simulator passes. Output is only generated after thr pass. Two temporary files are created during thz first pass and not erased until the COI of the second pass; these are named rawtddb and rawburn

L .TRAN Card

General form: .TRAN TSTEP TSTOP aSTART(Z?UIAX>>

Example: .TRAN .lN 50N

The SPICE ."RAN card must be present in any BERT input deck This card SPICE to simulate the timedependent behavior of the circuit described in the input de a SPICE user's guide for more details on the ."RAN card.

J. Temperature Setting (.OPTIONS card)

General form: .OFTIONS OPTl=optval OF'T2=0ptval. . .

Example: .OPTIONS TNOM=55

Simulation of circuit reliability at a given ambient temperatuxe can be specified 1 the SPICE .OFTIONS card as illustrated above. "NOM has units of C".

em of -in. All ition of bum-in

iss, the es used LS from Ck dw- in the

uld be L t deck second ipletion

ls t ruCtS k. see

y using

- 16 -

V. Examples

Example 5 shows a CORS input deck for a simple RC circuit and the subsequent This example illustrates the proper use of the .ALTMODEL card. (The oxide defect distribution used for this simulation is Listed in Example 2.) Example 6 shows a COR deck and subsequent output for a 4-input nand gate. This example illustrates the prope the EACHPROB and .LSI cards. The input deck shown in Example 7 is identical to Example 6 except that the QUICK option is specified on the ."TF wd. Note that thc projections are not very different fiom those in Example 6. Example 8 shows the prop the .BURNIN card. Example 9 is identical to Example 8 except that the QUICK opt requested. The user should compare the output listings in Example 8 and Example 9 t mine if the e m r introduced by using QUICK during a bum-in simulation is accept hisher application

DUtpUt. jensity i input use of that in failure use of In was deter-

ble for

I +

- 17-

References

[l] P.M. Lee et at, "BERT - Circuit Aging Simulator (CAS)," University of C Berkeley, Electronics Research Laboratory Memorandum UCB/ERL M90/2, 1990. B. K. Liew et al., "BERT - Circuit Electromigration Reliability Simulator," Unh California, Berkeley, Electronics Research Laboratory Memorandum UCBERL January 1990.

[3] I. C. Chen et al., IEEE Journal of Solid-State Circuits, Vol. 20, pp. 333, Feb 198 [4] J. Lee et al., IEEE Transactions on Electron Devices, VoL 35, p. 2268, Dec. 198 [5] E. Rosenbaum et aL, IEDM Technical Digest, p. 331, Dee. 1989. [6] R. Moazzami et al., IEEE Transactions on Elecrron Devices, Vol. 36, p. 24(

1989. [7] R. Moazzami et aL, VLTI Symposium Technical Digest. May 1989.

[2]

lifomia, January

mity of M90/3,

2, Nov.

- 18 -

Appendix A. CORS Simulations

This section provides the user with examples of the various kinds of studies wh performed with CORS. All simulations were performed for CMOS circuits operating and 125C. unless otherwise stated.

Figure A.l shows simulated reliability of 10K gate m y after bum-in. (Each ce gate array is identical to the one described by the input deck listed in Example 6.) POI ply voltage during bum-in was 7 volts. These studies are useful for balancing confiicti such as cost, avoidance of hot electron degradation and reduction of field failures due breakdown in choosing the bum-in condition for a product.

CORS has an option for printing out the breakdown probability for individual This is illustrated in Figure A.2.

Figure A.3 shows the effect of operating temperature on the reliability of a SR array. The results shown are for a circuit in which every memory cell is undergoing ous read operations. Previous simulations were perfomed for a SRAM cell in the idle well as one undergoing continuous precharge and read operations. Both cells have near ical failure statistics. The simulator showed that under each of these conditions the Si

transistors in the SRAM cell dominate circuit breakdown. The oxide field across th transistors does not change appreciably during a read operation.

Figure A.4 shows the dramatic effect of oxide quality on the expected circuit lifet 10K gate a m y (the input deck for this simulation was similar to the one listed in Ex% Figure A S shows that the inclusion of edge defects can change the predicted lifetime ing on the relative density and seventy of the edge defects (circuit simulated was the in Figure A.4). If the reader is unfamiliar with the variable Xdf plotted in Figure A.5 can find a discussion of it in Section 11.

h may t 5.5v

in the :r sup- ; goals I oxide

evices.

M cell mtinu- mte as ident-

le two n two

le of a ple 6). epend- m e as he/she

- 19-

Appendix B. Error Messages

Following is a list of the e m r codes generated by CORS. All have an identific form Tnnau. CAS e m r messages can be recognized by the identifier C n n a ~ , EM ex sages by E n n a ~ [1][2]. E m r messages with a 2-digit identifier vnn) are generate pre-processor, those with a 3-digit identifier (Tnnn) come from the post processor. In to the one line error message which is printed out by CORS, the following list suggestions for the user who may be puzled by the occurrence of an error message contains the source code location of each error message. TO1: Cannot open rawtddb file!

Line 52, tddb.c This e m r usually occurs when the user who wishes to do a bum-in simulation ac deletes file rawtddb between the first and second CORS nux.

Line 60, tddb.c User's computer will not allow CORS to open a new file for writing.

Line 72, tddb.c User's computer wil l not allow CORS to open a new file for writing.

Line 169, tddb.c CORS requires that zem or eight time-to-breakdown values be specified on a .'IT

Line 266, tddb.c CORS found a keyword on a .BURNIN card that was neither TIME nor TEMP.

Line 353, tddb.c CORS did not find a .TRAN card in the input deck. This SPICE command specified for CORS or CAS to xun.

Line 395, tddb.c User's file system ran out of memory during execution of pre-processor. The use try to free additional memory space. Simulation of a smaller circuit may be feasi

T08: Not enough arguments on a .XEFF card! Line 418, tddb.c

TO9: Not enough arguments on a .XEFF card! Line 435, tddb.c

T10 .XEFF card formated incorrectly! Line 447, tddb.c CORS did not find keyword FILENAME in its expected position.

Line 456, tddb.c CORS did not find a user pmvided file name after keyword FILENAME.

Line 465, tddb.c CORS did not find a n=w after keyword FILENAME.

TO2: Cannot open rawtddb file!

T03: Cannot open rawinp2 file!

M4: Not enough time-to-breakdown values on .lTF card!

TO5: Bumin card formated incorrectly.

TO6: No .TRAN card. Cannot do tddb analysis!

T07: Insufficient memory space. Reduce the number of MOS models!

T11: .XEFF card formated incomtly!

T12: .XEFF card formated incorrectly!

of the r mes- by the jdition mtains It also

idently

card.

u s be

should a ".

. . .

- 20 -

T13: .XEFF card fomated incofiectly! Line 474, tddb.c CORS did not find a user provided file name after keyword FILENAME.

Line 54 1, tddb.c see M7.

Line 560, tddb.c

Line 6 1 1, tddb.c Some capacitor definition card does not contain the minimum number of pa required by SPICE.

Line 643, tddb.c Keyword TBDMODEL may be spelled incorrectly.

T18: Insufficient memory space. Reduce # of tddb capacitors. Line 657, tddbx see M7.

Line 1104, tddb.c CORS found a model name on a .MODEL card for a MOSFET and did not find i card which contains this same model name. Every MOSFET model name must ai a .XEFF card.

Line 1213, tddb.c CORS can not find a file which was named on .XEFF card. Spelling emrs are mon cause of this problem or the user may have the file stored in a directory from the one CORS is searching.

T21: A tddb data file can not be found! Line 1133, tddb.c see no.

Line 1144, tddb.c see no.

Line 1581, tddb.c see M7.

Line 1588, tddb.c see m7.

Line 43, p0stddb.c User may have deleted file rawtddb between execution of pre- and post-pros maybe never ran the pre-processor.

Line 72, postddb.c User's file system ran out of memory during execution of post-processor. 'I

T14: Insufficient memory space. Reduce the number of transistors.

T15: No model name specified on a MOSFET definition card!

T16: Capacitor card in deck not fomated correctly.

T17: Capacitor card in deck not fomated correctly.

T19: Missing an XEFF statement for some MOS model!

T20: A tddb data file can not be found!

-

T22: A tddb data file can not be found!

T23: Insufficient memory space. Reduce the number of transistors.

"24: Insufficient memory space. Reduce the number of capacitors.

TlO1:Can not open file rawtddb!

T102:Insufficient memory space. Reduce the number of transistors.

meters

.xEFF ear on

L com- fferent

sot or

le user

- 21 -

should try to free additional memory space. Simulation of a smaller Circuit may ble.

Line 79, p0stddb.c See T102.



Line 146, p0stddb.c There are two causes of this emr. The user may have deleted file rawburn betu 1 and 2 of a bum-in simulation. Alternately, CORS may have detected a raw from a previous failed run (this file is automatically deleted after successful nins) now assumes it is doing pass 2 of a burn-in simulation. The solution is to dele raw**** files and retry CORS.

Line 160, p0stddb.c

Line 170, p0stddb.c User’s computer will not allow CORS to open a new file for writing.

T109:Can not open rawoutl file! Line 206, p0stddb.c CORS can not find file rawoutl which should have been created in p0stbert.c (CL

T1lO:Can not create rawout2 file. Line 212, p0stddb.c - See T108.

T1ll:Can not create outtddb file. Line 21 8, p0stddb.c See T108.

Line 284, p0stddb.c Header in SPICE output can not be located. User may be using a version of SPI than those CORS was developed for.

Line 295, p0stddb.c Step size specified on .TRAN card is so mall that a divide-by-zero emr is antic



Line 321, p0stddb.c

T103:Insufficient memory space. Reduce the number of models.

T104:Insufficient memory space. Reduce the number of capacitors.

T1OS:Insufficient memory space. Reduce the number of MOS devices.

T106:Cannot open file rawbum!!!

T107:Rawtddb not fomated correctly!

T108:Cannot open file rawbum for Writing.

T112:Voltage node printout for tddb analysis not found

T113:Division by zero in reading times.

T114:Lnsufficient memory space. Reduce the number of timesteps.

T115:Insufficient memory space. Reduce the number of timesteps.

T116:Xnsufficient memory space. Reduce the number of timesteps.

:n runs db file CORS all the

i).

3 other

md.

- 2 2 -

See T102.





Line 385, p0stddb.c Try a larger step-size on ."RAN card.






Line 499, p0stddb.c See TI 13.


Line 519, p0stddb.c See Tl02.


Line 538. p0stddb.c See T112.


T118:Insufficient memory space. Reduce the number of besteps.

T119:Voltage node printout for tddb analysis not found.


T121:Timesteps too small in reading voltages.

T122:Voltage printout for TDDB analysis not found.








T13O:Insufficient memory space. Reduce the number of timesteps.


- 23 - Tl32:Division by zero in reading times.



Line 1038, p0stddb.c CORS can not find one of the file names originally listed on a .XEFF card with FILENAME.

Line 1078, p0stddb.c CORS can not find one of the filenames originally listed on a .XEFF card with DIFFEDGE.

Line 11 15, p0stddb.c CORS can not find one of the filenames originally listed on a .XEFF card with OXEDGE.




Line 1282, p0stddb.c CORS found a model name on a MOSFET definition card without finding a COI ing .MODEL card to define the model. Or the error may have arisen in CORS' of this information.

Tf41:Could not find model name. Line 1717, pos1ddb.c CORS found a model name on a capacitor definition card without finding a corn MODEL card to define the model. Or the emr may have arisen in CORS's s this information

Line 140, malcs.c CORS solves for Xeff iteratively, Using Newton-Raphson's method. The calcula not converged after 100 iterations.

Line 204, malcs.c CORS solves for Xeff iteratively, using Newton-Raphson's method. The calcula not converged after 100 iterations.

T133:Timesteps too small in reading voltages.

T134:Can not open a defect density data file!






T140:Could not find model name.

T2Ol:N-R method did not converge within .01 percent in tddb calc.

T202S-R method did not converge within .01 percent in tddb calc.

p 0 r d

:yW0rd

:yW0rd

spond- storage

onding rage of

ins had

111s had

- 24 -

T203:N-R method did not converge within .01 percent in tddb calc. Line 241, nrcalcs.~ CORS solves for Xeff iteratively, using Newton-Raphson’s method. The calculab not converged after 100 iterations.

111s had

CORS Flow ,Chart

INPUT POST-

PROCESSOR (DECK &h PRE-

PROCESSOR

I ~ TDDB L

t \ DATA /

.

I . ,. I ’

125 .1 27 0.0 1.2 9 .2,13.3 .4,16.7 .6,20 1.6,23.3 1.8,25 2,26.7 2.4,28.3 3.4,30 4,31.7 4.2,33.3 6,35 6.4,36.7 7.8i38.3 9.4,40 12,41.7 12.2,43.3 13.4,45

14,50 16.6,51.7 17.2,53.3 20.8,55 24.4,56.7 32.4,58.3 36.6,60 39.4,61.7 50,63.3

53.4,66.7 68.2,68.3 68.6,70 84.4,71.7 87,73.3 138,75 230,76.7 275,78.3 650,81.7 673,83.3 1100,85 1165,86.7

1250,90

13. a, 4 6 . 7

51. a, 65

i209~a8.3 I

Example 1

Listing of input file far DEFECT. Contains time-to-breakdown data.

._ a&

52.859482 1.427163 54.404210 1.827216 55.307817 2.231436 57.493666 2.652685 57.756153 2.876821 57.990957 3.106096 58.397273 3.326794 59.173500 3.566749 59.535685 3.812604 59.644417 4.049652 60.439293 4.307829 60.583122 4.572849 61.023990 4.828863 61.439810 5.108256 61.984021 5.395681 62.020858 5.673960 62.229939 5.978370 62.295490 6.292339 62.327557 6.931472 62.707183 7.277386 62.786313 7.614260 63.209838 7.9850'77 63.565586 8.370176 64.197553 8.746691 64.469194 9.162907 64.633478 9.597203 65.164452 10.023934 65.243270 10.498221 65.311064 10.996128 65.856248 11.488535 65.869281 12.039728 66.331208 12.623084

. 66.398824 13.205066 67.426966 13.862944 68.565377 14.567168 68.963604 15.278579 70.880624 16.982691 70.958118 17.897615 72.053060 18.971200 72.181005 20.174062 72.263623 21.455813 72.337946 23.025851

.

Example 2

Listing of DEFECT output file. Input file is displayed in Ex. 1. This oxide has an UMCC defect density for commerical applications!

ibly high

27 -

.. 1 2 5 . 1 27 1 1 . 2 0 7 . 8 , 1 . 8 8 . 4 , 3 . 6 8 . 6 , E . g 8 . 8 , l O . 7 9 , 1 9 . 6 9 . 4 , 2 6 . 8 9 . 6 , 3 7 . 5 9 . 8 , 3 9 . 3 1 0 , 4 1 . 1 1 0 . 2 , 4 6 . 4 1 0 . 4 , 5 0 1 0 . 6 , 5 7 . 1 1 0 . 8 , 6 6 . 1 1 1 , 6 9 . 6 1 1 . 2 , 7 6 .E 1 1 . 4 , 7 8 . 6 1 3 , 8 0 . 4 1 3 . 6 , 8 2 . 1 1 3 . 8 , 8 3 . 9 1 4 , 8 7 . 5 1 5 . 2 , 8 9 . 3 1 5 . 6 , 9 1 . 1

Example 3

Listing of DEFECT input file containing ramp-voltage-breakdown data.

0

- 2 g -

,

***Input file ***

125 .Ol 27 0 0 9 Lognormal 1 20 2

*** Output file ***

Temp- 27 vox- 9.000000 Area= 0.010000 Log normal numpop- 1 t50 - l/sigmal: 20 2

Example 4

Listings of DEFECT input and Output files containing parameters for a lognormal h e - a b m a k distribution. ,wn

- 2 q -

. . . , . , . . . . . . . . , . . * .

Measuring G300 and 2300

.

1 o6

1 o4 Slope = 350 MV/cm

n

Q) cn 0 lo2

m * loo

1 oo2

U

U

.04 -06 .08 01 1 7 /t ox cm/MVl

I

lw

0 1

Take an ensemble of small area capacitors and measure intrinsic time-io-breakdown 8s a function of electric field at mom temperature. Plot log(tBD) vs - 1 shown above. The slope is G300 and the y- intercept is kx

Figure 2

.5

.4

.3

.2

Determination of E, and 6

I I I I I - - - - - rn - - - - * Crook: MOA 2W/

0 Yarnabe: 1 9 a 8 M v Baglee: l o a 7 - E - Model

-1 I I I I I I

-70; I 1 I

Time-to-breakdown, t,, Csecl

d0n(tBd) 1

Activation Energy: = d(T)

The $D in the above equation is measured for some arbitxary breakdown tes (above) for several researchers' data and consistent nsults wen found Solving finds

Figure 3 -

6=.0167eV and E,,=.28eV are obtained from the linear fit shown in the above fi; to be valid for all oxides at temperatures 25-150° C. However, the user may rt provide CORS with different values of 6 and E,,.

.. ,

3 75OC - l0O0C

125OC - 150Oc'

yield. E,,,, was plotted (4) and (5) for &, one

ure. These are believed pat this experiment and

- 3 I -

Inpu Deck

SAMPLE CIRCUIT C 1 2 0 1.4P + TBDMODEL-CMOD L-1OU W-SOU R1 1 2 1K VIN 1 0 PULSE(0 5 5n 5n 5n 10n 30n) .ALTMODEL CMOD C TOX-12.5N .TRAN .5N 60N .XEFF CMOD FILENAMEsdatal25 . TTF .PRINT t r a n v (1) v ( 2 ) . END

CORS Output

TDDB STATISTICS O p e r a t i n g Tempera ture-

number s e c o n d s 2.592e+06 number s e c o n d s 7.776e+06 number s e c o n d s 1.66752e+07 number s e c o n d s 3.1536e+07 number s e c o n d s 6.3072e+07 number s e c o n d s 1.5768e+08 number s e c o n d s 3.1536e+08 number s e c o n d s 6.3072e+08

SAMPLE CIRCUIT

27

f r a c t i o n fa i led 2.131181e-OS f r a c t i o n fa i led 2.779222e-05 f r a c t i o n f a i l e d 3.983974e-05 f r a c t i o n fa i led 4.368089e-05 f r a c t i o n f a i l ed 5.299287e-05 f r a c t i o n f a i l ed 6.692421e-05 f r a c t i o n fa i led 7.033430e-05 f r a c t i o n fa i led 7.523625e-05

Example 5

0

37-

FUUK LNYUT CMUS N A N D GATE MPA 2 3 1 1 MODP W-20U L-1U MPB 2 4 1 1 MODP W-2OU L-1U MPC 2 5 1 1 MODP W-2OU L - 1 U MPD 2 6 1 1 MODP W-2OU L-1U MNA 9 3 0 0 MODN W=32U L-1U MNB 8 4 9 0 MODN W-32U L-1U MNC 7 5 8 0 MODN W=32U L-1U MND 2 6 7 0 MODN W-32U L-1U CLOAD 2 0 30F .MODEL MODP PMOS VT0--.7 TOX-12.5N Kp-8U GAMMAs.4 TPGa-1 .MODEL MODN NMOS VTOs.7 TOX-12.5N KP-20U GAMMA=.4 VDD 1 0 5.5 VA 3 0 PWL(0 5.5 79N 5.5 80N 0 85N 0 87N 5.5 117N 5.5 119N 0 160N 1 VB 4 0 5.5 VD 6 0 5.5 VC 5 0 PWL(0 0 5N 0 7N 5.5 37N 5.5 39N 0 80N 0 81N 5.5 160N 5.5) .TRAN 1N 160N . TTF .XEFF MODP FILENAME-datal25 .XEFF MODN FILENAME=datal25 .LSI 16K 64K . EACHPROB .options reltol-.01 abstol-le-9 vntol-.0001 itll-2000 it12-500 . END

Example 6

. . _ . .

FOUR INPUT CMOS NAND GATE

TDDB STATISTICS O p e r a t i n g Tempera ture- 27

number s e c o n d s 2.592e+06 number s e c o n d s 7.776e+06 number seconds 1.66752e+07 number s e c o n d s 3.1536e+07 number s e c o n d s 6.3072e+07 number s e c o n d s 1.5768e+08 number s e c o n d s 3.1536e+08 number s e c o n d s 6.3072e+08

f r a c t i o n fa i led 7.841907e-06 f r a c t i o n fa i led 1.080054e-05 f r a c t i o n fa i led 1.297638e-05 f r a c t i o n fa i led 1.547089e-05 f r a c t i o n fa i led 1.743291e-05 f r a c t i o n f a i l ed 1.953538e-05 f r a c t i o n fa i led 2.104177e-05 f r a c t i o n fa i led 2.297238e-05

TDDB STATISTICS FOR 16000 IDENTICAL CELLS

number number number number number number number number

s e c o n d s 2.592e+06 s e c o n d s 7.776e+06 s e c o n d s 1.66752e+07 s e c o n d s 3.1536e+07 s e c o n d s 6.3072e+07 s e c o n d s 1.5768e+08 s e c o n d s 3.1536e+08 s e c o n d s 6.3072e+08

f r a c t i o n f a i l ed 0.117919 f r a c t i o n f a i l ed 0.158702 f r a c t i o n fa i led 0.187487 f r a c t i o n fa i led 0.219278 f r a c t i o n fa i led 0.243406 f r a c t i o n fa i led 0.268435 f r a c t i o n f a i l ed 0.285857 f r a c t i o n fa i led 0.30758




f r a c t i o n fa i led 0 .394611 f r a c t i o n f a i l ed 0.499045 f r a c t i o n fa i led 0.564166 f r a c t i o n f a i l ed 0.628477 f r a c t i o n fa i led 0.672319 f r a c t i o n fa i led 0.713574 f r a c t i o n fa i led 0.7399 f r a c t i o n fa i led 0.770132

' P r o b a b i l i t y of F a i l u r e a t 3.1536e+08 s e c o n d s

MNB 5.244740e-06 MNA 5.174992e-06 MND 4.932426e-06 MNC 4.912059e-06 MPA 3.906532e-07 MPC 3.870731e-07 MPB 0.000000e+00 MPD 0.000000e+00

Example 6

- 3 v -

FOUR INPUT CMOS NAND GATE MPA 2 3 1 1 MODP W-2OU L-1U MPB 2 4 1 1 MODP W-2OU L-1U MPC 2 5 1 1 MODP W-20U L-1U MPD 2 6 1 1 MODP W=20U L-1U MNA 9 3 0 0 MODN W-32U L-1U MNB 8 4 9 0 MODN W-32U L-1U MNC 7 5 8 0 MODN W=32U L=lU MND 2 6 7 0 MODN W=32U L=lU CLOAD 2 0 30F .MODEL MODP PMOS VT0--.7 TOX=12.5N KPx8U GAMMAz.4 TPG=-1 .MODEL MODN NMOS V'i0=.7 TOX-12.5N KP-20U GAMMA=.4 VDD 1 0 5.5 VA 3 0 PWL(0 5.5 79N 5.5 80N 0 85N 0 87N 5.5 117N 5.5 119N 0 160N VB 4 0 5.5 VD 6 0 5.5 VC 5 0 PWL(0 0 5N 0 7N 5.5 37N 5.5 39N 0 80N 0 81N 5.5 160N 5.5) . T W 1N 160N .TTF QUICK .XEFF MODP FILENAME-datal25 .XEFF MODN FILENAME-datal25 .LSI 16K 64K . EACHPROB .options reltol=.01 abstol-le-9 vntol-.0001 itll-2000 it12-500 . END

Example 7

1

- 3s-

FOUR INPUT CMOS NAND GATE

TDDB STATISTICS O p e r a t i n g Tempera ture=


s e c o n d s 2.592e+06 s e c o n d s 7.776e+06 s e c o n d s 1.66752e+07 s e c o n d s 3.1536e+07 s e c o n d s 6.3072e+07 s e c o n d s 1.5768e+08 s e c o n d s 3.1536e+08. s e c o n d s 6.3072e+08

27

f r a c t i o n fa i led 7.841907e-06 f r a c t i o n fa i led 1.091490e-05 f r a c t i o n fa i led 1.314527e-05 f r a c t i o n fa i led 1.571562e-05 f r a c t i o n f a i l ed 1.757264e-05 f r a c t i o n f a i l ed 1.979985e-05 f r a c t i o n fa i led 2.145751e-05 f r a c t i o n fa i led 2.350215e-05



s e c o n d s s e c o n d s s e c o n d s s e c o n d s s e c o n d s s e c o n d s s e c o n d s s e c o n d s

f r a c t i o n fa i led 0.117919 f r a c t i o n fa i led 0.16024 f r a c t i o n fa i led 0.18968 f r a c t i o n fa i led 0.222329 f r a c t i o n fa i led 0.245096 f r a c t i o n fa i led 0.271524 f r a c t i o n fa i led 0.290592 f r a c t i o n fa i led 0.313424

TDDB S T A T I S T I C S FOR 64000 IDENTICAL CELLS


s e c o n d s s e c o n d s s e c o n d s s e c o n d s s e c o n d s s e c o n d s s e c o n d s s e c o n d s

f r a c t i o n fa i led 0 .394611 f r a c t i o n fa i led 0.502698 f r a c t i o n f a i l ed 0.568852 f r a c t i o n fa i led 0 .634251 f r a c t i o n fa i led 0.675237 f r a c t i o n fa i led 0.718382 f r a c t i o n f a i l ed 0.746729 f r a c t i o n fa i led 0.777795

P r o b a b i l i t y of F a i l u r e a t 3.1536e+08 s e c o n d s

MNB 5.549167e-06 MNA 5.200911e-06 MND 4.994622e-06 MNC 4.923741e-06 MPA 4.019757e-07 MPC 3.872671e-07 MPB 0.000000e+00 MPD 0.000000e+00

1

Example 7

I- 3b-

**** Input deck used during pass 91. **** FOUR INPUT CMOS NAND GATE MPA 2 3 1 1 MODP W-20U L=lU MPB 2 4 1 1 MODP W-2OU L-1U MPC 2 5 1 1 MODP W-20U L-1U MPD 2 6 1 1 MODP W-20U L-lU MNA 9 3 0 0 MODN W-32U L-1U MNB 8 4 9 0 MODN W-32U L=lU MNC 7 5 8 0 MODN W=32U L-1U MND 2 6 7 0 MODN W-32U L-1U CLOAD 2 0 30F .MODEL MODP PMOS VT0=-.7 TOX-12.5N KP=8U GAMMA=.4 TPG=-1 .MODEL MODN NMOS VT0=.7 TOX-12.5N KP-20U GAMMA=.4 V D D 1 0 7 VA 3 0 PWL(0 7 79N 7 80N 0 85N 0 87N 7 117N 7 119N 0 160N 0) v B 4 0 7 V D 6 0 7 VC 5 0 PWL(0 0 5N 0 7N 7 37N 7 39N 0 80N.O 81N 7 160N 7) .TRAN 1N 160N . TTF .XEFF MODP FILENAME-datal25 .XEFF MODN FILENAME-datal25 .LSI 64K .BURNIN TIME-28800 TEMP==125 .options reltol-.Ol abstol-le-9 vntol=.0001 itll-2000 it12-500 . END

**** Input deck used during pass t2. **** FOUR INPUT CMOS NAND GATE MPA 2 3 1 1 MODP W-20U L-1U MPB 2 4 1 1 MODP W-20U L-1U MPC 2 5 1 1 MODP W-20U L=lU. MPD 2 6 1 1 MODP W-2OU L-lU MNA 9 3 0 0 MODN W-32U L-1U MNB 8 4 9 0 MODN W=32U L-1U MNC 7 5 8 0 MODN W-32U L-1U MND 2 6 7 0 MODN W-32U L-1U CLOAD 2 0 30F .MODEL MODP PMOS VTO=-.7 TOX-12.5N KPu8U GAMMA=.4 TPG=-l .MODEL MODN NMOS VTOs.7 TOX-12.5N Kp-20U GAMMAs.4 VDD 1 0 5.5 VA 3 0 PWL(0 5.5 79N 5.5 80N 0 85N 0 87N 5.5 117N 5.5 119N 0 160N 0 VB 4 0 5.5 VD 6 0 5.5 VC 5 0 PWL(0 0 5N 0 7N 5.5 37N 5.5 39N 0 80N 0 81N 5.5 160N 5.5) .TRAN 1N 160N . TTF .XEFF MODP FILENAME-datal25 .XEFF MODN FILENAMEsdatal25 .LSI 64K .BURNIN TIME-28800 TEMP-125 .options reltol-.Ol abstol-le-9 vnto1-.0001 itll-2000 it12-500 .END 1

Example 8

- '37-

. , . . . _ . . _ _ . .. .


P r i o r t o O p e r a t i o n , Burn I n w a s Conducted f o r seconds- 28800.000000 t e m p e r a t u r e = 1 2 5 *** The Yield af ter Burn-In w a s 0.999847 *** number number number number number number number number


f r a c t i o n fa i led 5.719652e-09 f r a c t i o n fa i led 1.713684e-08 f r a c t i o n fa i led 3.674918e-08 f r a c t i o n fa i led 6.950972e-08 f r a c t i o n fa i led 1.388086e-07 f r a c t i o n fa i led 3.460567e-07 f r a c t i o n fa i led 6.883102e-07 f r a c t i o n fa i led 1.361870e-06




f r a c t i o n f a i l ed 0.000365991 f r a c t i o n f a i l ed 0.00109616 f r a c t i o n fa i led 0.00234918 f r a c t i o n fa i led 0.00443874 f r a c t i o n fa i led 0.00884441 f r a c t i o n f a i l ed 0.0219042 f r a c t i o n f a i l ed 0.0430957 f r a c t i o n f a i l ed 0.0834693

Example 8

c

**** Input deck used during pass #l. **** FOUR INPUT CMOS NAND GATE MPA 2 3 1 1 MODP W-20U L-1U MPB 2 4 1 1 MODP W-20U L-1U MPC 2 5 1 1 MODP W-2OU L-1U MPD 2 6 1 1 MODP W-20U L=lU MNA 9 3 0 0 MODN W-32U L-1U MNB 8 4 9 0 MODN W=32U L-1U MNC 7 5 8 0 MODN W-32U L-1U MND 2 6 7 0 MODN W-32U L-lU CLOAD 2 0 30F .MODEL MODP PMOS VT0--.7 TOX-12.5N KP=8U GAMMA=.4 TPGS-1 .MODEL MODN NMOS VT0=.7 TOX-12.5N Kp-20U GAMMA=.4 V D D 1 0 7 VA 3 0 PWL(0 7 79N 7 80N 0 85N 0 87N 7 117N 7 119N 0 160N 0) V B 4 0 7 V D 6 0 7 VC 5 0 PWL(0 0 5N 0 7N 7 37N 7 39N 0 80N 0 81N 7 160N 7) .TRAN 1N 160N .TTF QUICK .XEFF MODP FILENAME-datal25 .XEFF MODN FILENAME-datal25 .LSI 64K .BURNIN TIME=28800 TEMP-125 .options reltol==.Ol abstol-le-9 vntol=.0001 itll-2000 it12-500 . END **** Input deck used during pass X2. **** FOUR INPUT CMOS NAND GATE MPA 2 3.1 1 MODP W-2OU L-IU MPB 2 4 1 1 MODP W-20U L-lU MPC 2 5 1 1 MODP W-20U L-1U MPD 2 6 1 1 MODP W=20U L-1U MNA 9 3 0 0 MODN W=32U L-1U MNB 8 4 9 0 MODN W-32U L-1U MNC 7 5 8 0 MODN W-32U L=lU MND 2 6 7 0 MODN W-32U L-1U CLOAD 2 0 30F .MODEL MODP PMOS VTO--.7 TOX-12.5N KP-8U GAMMA=.4 TPGS-1 .MODEL MODN NMOS VTOz.7 TOX-12.5N KP-20U GAMT!4A=.4 VDD 1 0 5.5 VA 3 0 PWL(0 5.5 79N 5.5 80N 0 85N 0 87N 5.5 117N 5.5 119N 0 160N ( VB 4 0 5.5 VD 6 0 5.5 VC 5 0 PWL(0 0 5N 0 7N 5.5 37N 5.5 39N 0 80N 0 81N 5.5 160N 5.5) . T W 1N 160N .TTF QUICK .XEFF MODP FILENAME-datal25 .XEFF MODN FILENAME-datal25 .LSI 64K .BURNIN TIME-28800 TEMPz125 .options reltol-.01 abstol-le-9 vntol=.0001 itll-2000 it12-500 . END

Example 9


P r i o r t o Operation, Burn I n w a s Conducted f o r seconds- 28800.000000 temperature= 1 2 5 *** The Yield a f t e r Burn-In w a s 0.999847 *** number number number number number number number number

s e c o n d s 2.592e+06 s e c o n d s 7.776e+06 s e c o n d s 1.66752e+07 s e c o n d s 3.1536e+07 seconds 6.3072e+07 s e c o n d s 1.5768e+08 s e c o n d s 3.1536e+08 s e c o n d s 6.3072e+08

f r a c t i o n fa i led 8.079108e-09 f r a c t i o n fa i led 2.427901e-08 f r a c t i o n f a i l ed 5.197523e-08 f r a c t i o n fa i led 9.837406e-08 f r a c t i o n fa i led 1.963456e-07 f r a c t i o n fa i led 4.887101e-07 f r a c t i o n fa i led 9.697074e-07 f r a c t i o n fa i led 1.909520e-06


number s e c o n d s 2.592e+06 f r a c t i o n fa i led 0.000516929 number s e c o n d s 7.776e+06 f r a c t i o n fa i led 0.00155265 number s e c o n d s 1.66752e+07 f r a c t i o n fa i led 0.00332089 number s e c o n d s 3.1536e+07 f r a c t i o n fa i led 0.00627616 . number s e c o n d s 6.3072e+07 f r a c t i o n fa i led 0.0124875 number s e c o n d s 1.5768e+08 f r a c t i o n fa i led 0.0307934 number s e c o n d s 3.1536e+08 f r a c t i o n f a i l ed 0.0601747 number s e c o n d s 6.3072e+08 f r a c t i o n fa i led 0.115037

Example 9

Lifetime after Bum-In

7 - 1UK gate array

1 1 , , I , 1 , 8 I , , I , , , , * ,

.01 m l 1 Time (years)

Figure A.1

10

93.2%

1.4%

F

100

-41-

.I->., I... I . . I . . .

I M9

Device Failure Probabilities

2.80~10-~

Vi" b-

VDD

M 9 1 I-

I I

cumulative 96 circuits failec /

I I CF%at I

I I M 2 I 1.11xlo-8 I

1.43 x 1 OD9 M4 5.10~10

I UfJ I

Schmitt Trigger

Figure A.2

Temperature Effects

256K SRAM

.

.01 *l 1 10 TIME (years)

Figure A.3

w 100

- 4 3 -

95 90 -i

Effect of Oxide Quality on Lifetime

test capacitor breakdown data (hypothetical)

A

CORS simulation

s Process B

1OK gate array

a * . I . 01 1 1 1- 1 1

4 $ i

TIME (seconds)

Figure A.4

Q $ H f

8

H

C C r

C c

w

-45 -

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