Embedded Leadless Chip Carrier

L. A. Lim / Ramkumar. MASM Technology Singapore Pte. Ltd.

2, Yishun Avenue 7, Singapore 768924.

Abstract Efforts were put in to have a dual row package with aRecently there have been several developments in the challenging leadframe etch process, but the gain was not

areas of small form factor and high-density lead frame based comparable to PBGA level I/O counts. There were severalIC packages. These packages have the benefits of occupying attempts recently to reach this level of I/O counts withsmaller PC board area, lower assembly material consumption multiple row QFN using partial etch techniques, but most ofdue to their smaller volume package construction, and good these methods called for wet end processes, like a chemicalthermal dissipation properties. Details of benefits of the etch line at the assembly house, in order to separate the leads.relevant assembly processes would be covered including Wet end processes are additional investments and manyactual comparison. companies are not willing to go in that direction. Embedded

Another area of recent development in packaging Leadless Chip Carrier (ELCC) addresses this situation; byintegration is system in package SIP. A SIP package can giving Multi-row leads feasibility with no wet end processintegrate various ICs in a package. For example; CPU, logic, requirement at the assembly house.analog, digital, discrete and passive components can be Embedded Leadless Chip Carrier Designintegrated in a single package. SIP provides a high level of The typical QFN leadframe, as we all know, is an etchedintegration capability of several functional chips. It provides leadframe with adjacent leads connected typically by a halfgood miniaturization capability for hand held portable etched connecting bar. The die attach pad is also connected toelectronic communication devices. High-density capability the structure by QFP type tie bars at the corners. The resultingand flexibility in design using a substrate like chip carrier will leadframe design, typically, is a matrix array with all leads andbe covered. units connected.

However there are several challenges faced by the end userin assembly of these packages. This paper will cover thebenefits of a newly developed leadless chip carrier and thechallenges faced and addressed in the assembly downstreamprocesses.Introduction

Years ago when the IC industry was shifting to substrate-based packages; FBGA, CSP etc, one of the major packagecost factors was the cost of substrates. Packaging engineerschose to fall back on leadframe again by innovating the QFN,which has small form factor but low I/O count. For manyyears, QFN has been a major industry driver due to the smallersize, lower cost, and ease of high volume manufacturing usinghigher unit density matrix array designed, etched lead frames. Fig.2 Embedded Leadframe Chip CarrierHowever since QFN is also a peripheral leaded package and ThELCdsgaloasmtierwsflasanadesmall in size, the I/O feasibility was limited to a little over atchpdarngdimtixrayfm.Hwv,telas

* ~~~~~~~~~~~~~~anddie attach pads are already disconnected and embedded in__ ~~~~~~~~~~~~aninsulative epoxy matrix and held together with the outer

~~~~~~~~~~~~supportive copper frame. Since the leads and pads are just| ~~~~~embedded in an epoxy matrix, the design layout of leads and

*1|1B ~~~~pads, or the number of I/O are fully flexible and only limited- ~~~~tothe PCB routing design rules. Thus ELCC is able to meet

design feasibility and at the sa:me time no special wet* n~~~~rocesses when compared1 to some similar techniqules.

Packages and Form FactorUtilizing its embedding concept, ELCC has the freedom of

|----|E||| - 0|0 ~~~~~aflexible footprint layout. Thus it can serve from very low

with its small form factor, with a typical 0.5 mm lead pitch forFig. 1 QFN Leadframe with die a 12x12 mm package with 4 rows of leads can yield over

300L. Also this 12x12 mm package will occupy only 900O of

978-1-4244-21 18-3/08/$25.00 ©)2008 IEEE 2008 1 0th Electronics Packaging Technology Conference

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area, in comparison to QFP (40x40 mm) of similar I/O. When As it is illustrated in Fig.5, the ELCC-based process usescompared to a 27x27 mm PBGA, this will yield 80% board the mainstream processes only and does not require anyspace reduction. Due to its flexibility in the layout design, etching/plating stage thus cutting investment cost.ELCC can help include power rings / ground rings, as we seein substrate based packages.

LOeadfame Leadfiame Leeadframe Leadrame LeatarnmeDie Afttch Die Attac Die Attach Detah Die AttAch

Wir Bodi WiedBWi Wire Bon WreBd WreBodd

:~~~~~~~~~~~~~~~~~~~~~~~~~rcs flow'*

Lwrassemb

Fig.5 Process flow comparisonProcess Advantages

There can be many process advantages realized whenusing the ELCC. Wire bond process can achieve good stitchpull strength of typically 7.5 gms on 25 micron gold wire withsimple process setup. Wire bond process may not requirespecial thermo compression bonding/scrub motions as used in

Fig.3 Multilayer high pin count wire bonding. QFN wire bond process, resulting in UPH gain. Since thewire bond process is only thermo-sonic and leads been alreadyAnother recent development in assembly technology is the isltdloefrcisnvvdadhgerpwranb

SIP (System in Package). ELCC is a very promising option to applied withouneking olem as see pical QFadopt for this multi-chip application. At times, if the "no die rocess)attach pad" is intended, the epoxy matrix can serve to support process).the die with normal die attach process.

equival/OePBGAnt_a5 | Fig.6 Neck stress in QFN wire bonding

| ~~~~~~equivalent S

| ~~~power rings Layout M _UI ~~~~~~~~flexibility IF

Fig.4 Packages ftom ELCC

Assembly Process Flow Comparison Fig.7 ELCC Stitchpulltestdata.The process flow of ELCC-based assembly is very simple

and uses existing machines of a typical assembly house. Asindicated in the Fig.5, ELCC can be used as we handle the F EM volum clead frames. Starting from die attach, the strips can move to isse.I oprsnt BG -30) neuvlnwir bon foloe by typca QF modn process An ELCC-based package will use considerably lower EMCrequirements for plasma cleaning are also possible as per the (aot90 oe)a iet oprsn lo yialuser needs. After the PMC process, the strips can be sent toelectrical testing in "strip form", since the leads are alreadyelectrically isolated. Later, the unit singulation can beperformed by a standard dicing singulation process.

2008 10th Electronics Packaging Technology Conference

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I~~~~~~~ir-l 1 _;,a e

ElLCC ddoe5ot ug QFN tdoe ih ftdimbly_Fig.8 No Tape Residue with ELCC Process iQFNmoldnissisotft

QFN molding processes require tape below the leadframe for_flash free molding. However for ELCC molding will not be Fig.10O Pre-isolated leads aid Strip testingaffected by any tape residue, as no tape will be involvedduring assembly process.

As the leads are just embedded in an epoxy matrix, the saw QFN - Package Dual Pass sawing neededsingulation process is not cutting metal connecting bars. Thus Ifor Strip Test/Singulation

resulting in increased UPH as well as longer blade life.|

. . .. _.~~~~~Sain ELCC Package No sawing needed for Strip Test

_Fig.l 5SinglePassSawingforSStrip Testl

~~~ ~ ~ ~ ~ ~ ~ ~~~55S55 SW1B. 55 55..0 X,,SSSSSSS 55 a ,555*5...gRe S.Kr,,6E'-ET -......................Thermal PerformancThermal resistance simulation results (against air velocity)

_ 1 1 _ - * ~~~~~~~~showthat ELCC-based packages follow the thermal_111 .. . - - | ~~~~~~performance similar to QFN packages. The comparison was

done with respect to other packages data.

Fig.9 Singulation speed advantage 61

ELCC formats are pre-plated leadframe with the proven I

also Pb-free. ThusELCC offers acomplete Pb-free solution. |4155Pre-plating rernoves the solder plating requirernent of leads |

One of the major processes after package assembly is the5*55453

asem lCChouesnhv ookedQFntoateipAssimbilte of doin * SS55

QFNctrmoldtsingisafecthed bytsi tape rstidupic mostotef.ThesiQFnmoldinps"Srocessesig"reqirce taeadbelo tELC eadrae foredFi.2Tm raueisibtounrarflwfslash ,ipoiestifreedmlin.Hoee fofsriELCCmoling. wl o eFg 0Peioae ed i ti etn

during~~~ ~ ~ ~ ~ ~ ~ ~ ~~ ~20assmbl process.acain ecnloyCofrecAs heledsarjstemededin n poy atix te awQF - acag DalPas awngnede

E250 500 1

Airflow11 _(11_p_m)LFig. 13 Thermal Resistance Simulation

Lead IntegrityThe concern of leads coming off the package due to less Fig.16 T-SCAN after MSL1 Precon

locking was tested based on the lead integrity test guidelinesfrom MIL STD 883 for leadless packages. The method Assembly Challengesinvolves soldering a joint to the lead, allowing it to cool and ELCC offers a few challenges particularly when dealingsubsequently pulling vertically upwards to test the strength of with high I/O and thin packages. Typically high I/O packagesthe solder bond with the lead. The criteria will be, the joint are involved with many rows of leads and require multi-tiershould withstand at least 227 gm-f in tensile pull. ELCC- wire bonding. When package thickness is small, the loopbased packages are found to withstand an average goo gf of height to wire length ratio will also be very small betweenload without leads being pulled out. Fig. 1O illustrates this. wire layers. Proper selection and optimization of low loop

profile might help to resolve the issue.As the epoxy matrix is very thin and fragile, handlingF d>-klPltt - | a =

related epoxy matrix cracks is another challenge that can beencountered. These are typically caused by improper handlingof the ELCC strip. Thus a careful handling will help to reducethe instances.

Wire sweep is another issue with multi-row high I/Opackages, and ELCC is no exception. However, current EMCare able of meeting the requirements. Further adjustment can

Fig. 14 Lead integrity (solder pull test) also help to keep the wire sweep under control.Conclusions

Package Reliability Embedded Leadless Chip Carrier addresses all theElevated features greatly enhance the package integrity by requirements of the Packaging Engineering. It offers low toacting as locks. The unique locking mechanism designed in high I/O with small form factor. The design flexible package /ELCC not only provides good reliability but also good lead leads layout empowers the designer with more freedom tointegrity. Tests show that the package is able to withstand design the package. ELCC is environmentally friendly andMSL precon level 1. Further to the preconditioning, other offers a complete Pb-free packaging.reliability tests are on being conducted and the results areawaited. ELCC

FIatue6s Pkg QFP QFN PBGA

HighFi.1 iE ir ifSmall form'fator / i

Flexiblie ln package design layout V v

EnvironmrEental friendly (Pb free)o C nf eCo5patible to Mainstream assembly

process / V V

Support ini-strip testing v

H4igMHreliabiltyv

Since the leads are already isolated, ELCC supports strip Acknowledgmentstesting and improves productivity. Singulation is easier and The authors would like to thank the team members offaster since no metal smear is encountered due to metal-free Packaging Technology, Leadframe Development,cut line at the saw operation. Encapsulation Development and the management of ASM for

Finally, the package reliability and lead integrity are the contributions and various supports to the ELCC program.outstanding; thanks to the special etch profile lock mechanism Last but not least the authors would like to thank the variousdesign. Thus, despite some typical challenges with any high material suppliers, customers and research institutes for theirI/O packages, ELCC is truly offering the best options to contributions to the program.packaging engineers to reach optimal solutions for complex Referencespackaging challenges. 1. JEDEC Package Outline Specifications MO-220, MO-247

2. JEDEC JESD22-A104C3 IPC-2226,22214. IPC-2226,2221

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