Embedded Systems Design at Mentor

Platform Express Drag and Drop Design in Minutes

IP Described In XML Databoo

ks

Simple System Diagrams

represent complex designs.

Consistent HW and SW

Programmers View

Advanced IP Configuration Options Statically Configured IP

— Configuration options are generated automatically.

Dynamically Configured IP

— Generated as part of the design creation/context process.

Platform Transforms— Auto-customization of IP for

specific design contexts.

Creating The Design HDL Choice of Verilog and

VHDL.

Targeted for Modelsim and other simulators.

Auto-Generation of HDL bus infrastructure.

— Platform Express is bus agnostic.

— Proprietary and custom bus formats are easily supported.

Creating A Complete Verification SoC Environment

Seamless HW/SW Co-verification

Modelsim HDL Simulation

XRAY Embedded Debugger

Seamless Co-Verification Enables software & hardware

development in parallel Removes software from the

critical path Reduces the risk of hardware

iterations Provides accurate analysis of

system performance Increases overall product quality Increases visibility into your

hardware

SEAMLESSCo-Verification

Performance

ProfileDatabase

System Profiler

Balancing Performance & Detailwith Seamless

Coherent Memory Server

SW ExecutionCode Debug

HW SimulationDesign Verification

VHDL/Verilog/SystemC Pin Wrapper

BUS Interface Model (BIM)

– Peripherals– Bus Cycle Timing– Controllers (DMA, MMU, Cache …)– Memory/BUS tracing/profiling

Instruction Set Simulator (ISS)

– Complete Instruction Set– Registers– Interrupt– Reset– Instruction Timing– Code Profiling

Coherent Memory ServerMemory Profiling

Seamless Processor Support Packages

High-performance ISS models core functionality

Integrated high-level debugger, e.g. XRAY, RealView and Multi

Interface to ModelSim and all popular Verilog and VHDL simulators

Comprehensive CPU Support

PowerPC 4xxPowerPC 603, 74x, 75x, 8xxxPowerQUICC I, II, III

Oak, Teak, TeakLite, Palm

4K, 4KE, 5K, 20K, 24K

SC1200, SC1400 Xtensa

ARM7, ARM9 ARM10, ARM11, Cortex

C6416, C64+, C55

RM70xx, RM79xx

Models also available for Analog Devices, ARC, ETRI, Faraday, Fujitsu, Infineon, Intel, Lucent, Matsushita, NEC, Philips, Renesas, Samsung, ST, Toshiba, Xilinx

ZSP400, ZSP500

Integrating the Software Domain with Assertion-based Verification

Seamless

ISS

ISS

Profiler Views

Software Profile

Bus Load

Software Gantt

Bus Delay

PowerMemoryHeat Map

Profiler: Views aligned to show cause & effect

An Evolution of the “Traditional” Flow

Paper SpecificationPaper SpecificationPaper SpecificationPaper SpecificationHigh Level Models

Co-Verification HDL - RTLHDL - RTL• DesignDesign• DebugDebug• VerificationVerification

HDL - RTLHDL - RTL• DesignDesign• DebugDebug• VerificationVerification

ApplicationApplication

BSP (drivers)BSP (drivers)

ApplicationApplication

BSP (drivers)BSP (drivers)

RTOSRTOS

SoftwareSoftware Hardware HardwareSoftwareSoftware Hardware Hardware

SoftwareSoftwareSoftwareSoftware HardwareHardwareHigh Level ModelHigh Level Model

HardwareHardwareHigh Level ModelHigh Level Model

System High Level ModelSystem High Level ModelExecutable SpecificationExecutable SpecificationSystem High Level ModelSystem High Level ModelExecutable SpecificationExecutable Specification

Consistent Verification

Requirements follow-up

Virtual Prototype

Transaction Level Modeling

This is a methodology, also known as TLM, that defines new abstraction levels above the register.

It is itself made of several stages, which gradually abstract from hardware implementation constraints but still with a structured view of the design.

Its goal is to reduce the number of events and the amount of data that has to be treated during simulation.

This modeling method is built as a set of interfaces that define how models communicates.

AA

MemMem

Generic CPUGeneric CPU(B, C and ctrl)(B, C and ctrl)

DD

TLM Channel

AA

MemMem

Specific CPU - ISSSpecific CPU - ISS(B, C and ctrl)(B, C and ctrl)

DD

Bus

Transactions

TLM API

TLM APITLM API

TLM API

AA CC DD

BB

TLMTLM RTLRTLAlgorithmicAlgorithmic

The Performance of the Models

Algorithmic Level (ALAL)

Function CallsFunctional description

≈ 10 MHz

UML, Matlab, C/C++

Programmer View (PVPV)

Generic BusArchitecturalMemory Map

≈ 1 MHz SystemC

Programmer View + Timing (PVTPVT)

Bus specificTiming approximation

≈ 500 kHz

SystemC

Cycle Callable (CCCC)

Word transferCycle accurateClock Edges

≈ 10 kHz

SystemC

Register Transfer Level (RTLRTL)

Signal and bitsCycle accurate

≈ 1 kHzVHDL, Verilog

AA CC DD

BB

AA

MemMem

Generic CPUGeneric CPU(B, C and ctrl)(B, C and ctrl)

DD

TLM Channel

AA

MemMem

Specific CPU - ISSSpecific CPU - ISS(B, C and ctrl)(B, C and ctrl)

DD

Bus

FunctionCall

Transaction

Clock

Register Transfer LevelRegister Transfer Level

Hardware Transaction LevelHardware virtual prototyping, high level verification environment,

architecture refinement, performance verification

Hardware Transaction LevelHardware virtual prototyping, high level verification environment,

architecture refinement, performance verification

System Exploration LevelSystem executable specification, architecture exploration,

HW/SW partitioning, mapping of functional list on HW/SW resources

System Exploration LevelSystem executable specification, architecture exploration,

HW/SW partitioning, mapping of functional list on HW/SW resources

Algorithmic LevelFunctional design and verification,

exploration of the functional requirement list

Algorithmic LevelFunctional design and verification,

exploration of the functional requirement listExplore the feasibility of requirementsExplore the feasibility of requirements

Partition HW and SW - Define the architectureFinalize the specification

Partition HW and SW - Define the architectureFinalize the specification

Create a first prototype of the HWCreate a verification infrastructureCreate a first prototype of the HWCreate a verification infrastructure

Implement the hardware at register levelImplement the hardware at register level

In Summary

“ESL Space”

Uncommitted Systems

HardwareCommitted

Functional RequirementsFunctional Requirements

GatesGates

Catapult C Synthesis – Algorithm to RTL

Develop Algorithms using ANSI C++

No proprietary extensionFocus on the functional intent

Develop Algorithms using ANSI C++

No proprietary extensionFocus on the functional intent

Synthesize with Catapult CExplore the design space

Find the optimal architecture

Synthesize with Catapult CExplore the design space

Find the optimal architectureTechnology

Files

TechnologyFiles

ArchitecturalConstraints

ArchitecturalConstraints

Generate High Speed ModelsVerilog, VHDL, SystemC

Accelerate system level verification

Generate High Speed ModelsVerilog, VHDL, SystemC

Accelerate system level verification

Untimed TLMUntimed TLM

Timed TLMTimed TLM

Cycle TLMCycle TLM

Generate Target Optimized RTL Faster and better than hand-coded

For ASIC, FPGA or FPGA prototyping of ASICs

Generate Target Optimized RTL Faster and better than hand-coded

For ASIC, FPGA or FPGA prototyping of ASICs

Automatically Verify the RTLGeneration of testbench infrastructure

Seamlessly reuse original C++ test vectors

Automatically Verify the RTLGeneration of testbench infrastructure

Seamlessly reuse original C++ test vectors

PerspectaPerspectaPerspectaPerspecta

Perspecta

Modeling ‘components’— Library builder and

distributor System Architecture

— Assemble and modify design

Performance analysis— Throughput, bandwidth

Design validation— Functional and

performance goals HW/SW co-design

— Full system integration Verification

— Hardware & software functional test

PX for System LevelPX for System Level

MEMCPU

Co-Proc

MEM Bridge

Peri 1 Peri 2

ComponentLibrary

Model ExpressModel Express

my Algorithmswitch( m_state ) { case RES_WAIT :

if( rsp_fifo._get( rsp ) ) { send_resp( rsp ); } break;

Software Debugging

Environment

System Analysis