Enhanced Current Gain in SiC Power BJTs using a novel Surface Accumulation Layer Transistor (SALTran) Concept

8/14/2019 Enhanced Current Gain in SiC Power BJTs using a novel Surface Accumulation Layer Transistor (SALTran) Concept

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Enhanced Current Gain in SiC Power BJTs using a novel

Surface Accumulation Layer Transistor (SALTran) Concept

M. Jagadesh Kumar and Vinod PariharDepartment of Electrical Engineering, Indian Institute of Technology,

Hauz Khas, New Delhi 110016, India

Email: [email protected]: 091-11-25681264

Abstract: In this paper, we demonstrate that the current gain of SiC power bipolar transistors

can be improved by as large as 100 % by using a novel Surface Accumulation Layer Transistor

(SALTran) concept in which a reflecting boundary in the emitter reduces the base current. The

reasons for the improved current gain are explained based on simulation results.

Key words: Semiconductor Devices, Current gain, Bipolar Transistors, Silicon Carbide.

M. Jagadesh Kumar and Vinod Parihar, "Enhanced Current Gain in SiC Power BJTs usinga novel Surface Accumulation Layer Transistor (SALTran) Concept," MicroelectronicEngineering, Vol.81, pp.90-95, July 2005


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1. Introduction

Silicon Carbide (SiC) has been recognized as the choice for high voltage, high temperature,

high power applications because of its large bandgap and high critical electric field [1-3]. SiC

bipolar junction transistors [4] have been demonstrated with high blocking voltage and high on

currents taking the full advantage of the material properties of SiC. Current gain is a key

parameter for the power BJTs as it decides the driving loss of the transistor. But the power SiC

BJTs reported in literature exhibit a low current gain usually in the range of 10-15. This is

mainly because of the poor carrier lifetimes in SiC material. Both heterojunction bipolar

transistors(HBTs) and polysilicon emitter transistors have been used for realizing high current

gains in silicon BJTs.. Another method used to improve the current gain of silicon bipolar

transistors is the application of high-low emitter junction in which a lightly doped n-region is

introduced between the n+-region and the p-base region [5]. However, the above methods are

not technologically well suited for increasing the current gain in SiC BJTs. Recently, it has

been shown that by using the Surface Accumulation Layer Transistor(or SALTran) concept in

which a reflecting boundary for the minority carriers is created in the emitter region, the base

current of a silicon BJT can be significantly reduced resulting in a large current gain

enhancement[6]. It would be very beneficial if the current gain of a SiC BJT can be enhanced

using such a simple emitter contact concept.

Since the properties of SiC are different from that of silicon, we do not yet know how the

SALTran concept works for the SiC bipolar transistors. The main objective of this work is,

therefore, to implement the SALTran concept on power SiC BJT using a two dimensional

device simulator ATLAS [7] and examine if the current gain of the SiC BJT can be improved.

Based on our simulation results we demonstrate that for identical minority carrier lifetime, the


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performance of the power SiC SALTran is better than the conventional power SiC BJT in terms

of high current gain mainly because of the improved emitter injection efficiency due to the

reflecting boundary at the emitter contact. Also we observe that due to the low emitter doping

required in the case of the SALTran, the complexity involved in high doping epitaxial growth

can be avoided for the SiC BJT.

2 Device structure and parameters

In order to validate our simulation results we have first implemented the power SiC BJT

already reported in literature [8] in ATLAS with the following parameters. The collector drift-

region thickness is 20 m with a uniform doping of 2.5x1015

/cm3

and the n+

collector doping is

1x1019/cm3, the p-base thickness is taken as 1 m with a uniform doping of 2.5x1017/cm3

while the emitter doping is 1x1019/cm

3with thickness 0.75 m. The JTE doping is taken as

2.5x1017/cm3. The cell pitch for the structure is taken to be 14 m. For the above dimensions,

we have adjusted the recombination parameters in our simulation so that our simulated peak

current gain matches with the reported experimental current gain of the published structure[8].

3 Design methodology

Fig. 1 shows the cross-sectional view of the optimized power SiC BJT and power SiC

SALTran. To apply the SALTran concept to the power SiC BJT reported in [8], we have

optimized the thickness of the emitter and base thickness to be 0.3 m and 0.4 m respectively.

It may be noted that the base thickness is reduced compared to the original structure in [8] to

make sure that the base region recombination does not overshadow the gain enhancement

provided by the SALTran concept. All the device parameters of the conventional SiC power

BJT and the power SALTran are kept the same except that in the case of the power SALTran,

we have changed the emitter doping to 1x1014/cm3 and chosen an emitter metal with very low


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workfunction (3.35eV) e.g magnesium, to obtain surface accumulation near the emitter contact.

In the following sections we show the comparison of the power SiC SALTran with the power

SiC BJT which differ only in their emitter doping and emitter contact properties.

4 Simulation results

We have taken the value of electron affinity and band gap for the 4H-SiC to be 3.9 eV and 3.2

eV respectively. We have used the two-dimensional simulator ATLAS to understand the DC

characteristics of the proposed structure. Drift-diffusion calculations are carried out using

appropriate physical models given in ATLAS for 4H SiC. The field dependent mobility [9] and

the Arora mobility [10] models are used and the bandgap narrowing effect is taken into

account. For recombination we have incorporated SRH and Auger recombination mechanism.

SRH minority carrier lifetime coefficient for electrons and holes are tuned to be 30 nS and 6 nS

respectively, while the SRH equilibrium concentration is 5x1016

cm-3

for both electrons and

holes. The incomplete ionization is also taken into account.

We have first simulated the band diagrams of both the structures to examine if surface

accumulation takes place. Fig. 2 shows the band diagram in the emitter-base region for both the

SiC SALTran and the SiC BJT structures. Fig. 2(a) is for zero emitter-base bias and Fig. 2(b)

is under normal biasing conditions corresponding to the peak current gain. We observe that at

the metal-semiconductor interface, with or without the bias, there is a bending in the

conduction band indicating that accumulation of electrons does take place. The accumulated

electron profile near the emitter contact is shown in Fig. 3 and also the minority carrier profile

is shown in Fig. 4. The presence of accumulated electrons results in a high electric field near

the emitter contact as shown in Fig. 5 which causes the reflection of holes coming from the

base. Because of the presence of this reflecting boundary in the emitter to the holes coming


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from the base, the hole gradient in the emitter decreases reducing the base current. This is a

clear indication that the SALTran effect works not only for lateral high speed bipolar

transistors[6] but is also effective for vertical power bipolar transistors. However, when

applying the SALTran concept to the power transistors, care should be taken to see that the

base width is of some reasonable value so that the base recombination does not overshadow the

potential benefits of the reflecting boundary in the emitter.

Fig. 6 shows the output characteristics of power SiC SALTran and power SiC BJT. The

comparison shows that the current driving capability of power SiC SALTran is higher as

compared to the power SiC BJT. Our simulations indicate the power SiC SALTran device

shows a high BVceo of around 1700 V. The current gain comparison in Fig. 4.4 shows that

the power SiC SALTran exhibits almost double the current gain of the power SiC BJT. The

Gummel plot in Fig. 7 clearly shows that the high current gain of the power SALTran is due to

the reduced base current. The reduced base current in the case of the power SiC SALTran can

be attributed to the reduction in number of holes reaching the emitter because of the SALTran

effect.

Fig.9 shows the current gain for different temperatures for the power SiC SALTran and

the power SiC BJT. We observe that in both the cases the current gain decreases with

increasing temperature. Further the effect of temperature on the normalized current gain i.e

()/300 is plotted in Fig. 10, where () is the peak current gain at a particular temperature

and 300is the peak current gain at room temperature. Power SiC SALTran shows a higher

negative temperature coefficient for the current gain due to the low emitter doping. The

negative temperature coefficient for the current gain is due to the deep level acceptors in the

base region [11]. At elevated temperatures, the minority carrier lifetime increases, resulting in


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a significant increase in the current gain of the conventional silicon bipolar devices. However,

in SiC npn BJTs, due to deep level of acceptors, holes that were frozen out at room temperature

ionize at elevated temperatures, resulting in higher hole concentrations in the base at high

temperatures. This effect reduces the emitter injection efficiency of the device at elevated

temperatures, which cancels out the increasing minority carrier lifetime in the base region and

keeps the current gain of the SiC npn BJTs almost stable. This negative temperature coefficient

makes this device attractive for paralleling and for preventing thermal runaways [12]. In Fig. 11

we have plotted peak current gain for different temperatures against 1/KBT of the power

SALTran and the power SiC structure. The slope of the natural logarithm of peak current gain

curve for different temperatures gives the activation energy which is nothing but the difference

of the effective bandgap narrowing of the emitter and the base[13]. We see that the activation

energy comes out to be -44.5 meV and -37.5 meV for power SiC SALTran and power SiC BJT

respectively. This shows that in the case power SiC SALTran, the current gain decreases at a

higher rate than the power SiC BJT making the SALTran structure more suitable for high

temperature applications.

5 Conclusions

In this paper, for the first time, we have successfully implemented the SALTran

concept to the power SiC BJT. The high current gain obtained for the proposed structure results

in low driving losses making this device more useful for high voltage applications. Further the

high current gain can be traded off by increasing the base doping to obtain better output

characteristics in terms of increased early voltage. The power SiC SALTran is also more

suitable in situations where thermal runaway due to an increase in temperature is a problem.


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References

1. J. B. Casady and R. W. Johnson, Status of silicon carbide (SiC) as a wide bandgap

semiconductor for high temperature application: A review, Solid-state Electron., vol.

39, no. 10, pp. 1409-1422, 1996

2. P. G. Neudeck, Progress in silicon carbide semiconductor electronics technology,J.

Electron. Mater., vol. 24, pp. 283-288, 1995.

3. Y. Singh and M. J. Kumar, "A New 4H-SiC Lateral Merged Double Schottky

(LMDS) Rectifier with Excellent Forward and Reverse Characteristics," IEEE Trans.

on Electron Devices, Vol.48, pp.2695-2700, December2001.

4. J. W. Palmour, R. Singh, L. A. Lipkin, and D.G. Waltz, 4H-SiC high temperature

power devices, in Trans. 3rd

Int. Conf. High-Temperature Electron. (HiTEC), vol. 2,

Albuquerque, NM, June 1996, pp. XVI-9-14.

5. S. S. Ang, A high-low emitter bipolar power transistor,Microelectronics Journal,

vol.26, pp.1-7, 1995.

6. M. J. Kumar and V. Parihar, "Surface Accumulation Layer Transistor (SALTran): A

New Bipolar Transistor for Enhanced Current Gain and Reduced Hot-carrier

Degradation," To appear in IEEE Trans. on Device and Materials Reliability, Vol.4,

June 2004.A PDF file of this paper can be found in Accepted for future publication

at (http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?puNumber=7298 )

7. ATLAS Users Manual, Silvaco Int., 2000.

8. D. M. Caughey and R. E. Thomas, Carrier Mobilities in Silicon Empirically Related

to Doping and Field, Proc. IEEE, Vol.55, pp. 2192-2193. 1967.

9. N. D. Arora, J. R. Hauser, and D. J. Roulston, Electron and Hole Mobilities in Silicon

as a function of concentration and temperature,IEEE Trans. on Electron Devices,

vol.29, pp.292-295, 1982.


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Figure Captions

Fig. 1 Schematic cross section of the Power SiC SALTran and Power SiC BJT

Fig. 2 Band diagram of emitter-base region (a) without bias and (b) with bias

Fig. 3 Electron concentration in the emitter region of power SiC SALTran and power SiC BJT

Fig. 4 Minority carrier profile in the emitter-base region (a) without bias (b) with bias

Fig. 5 Electric field in the emitter region in power SiC SALTran and power SiC BJT

Fig. 6 Output characteristics of the power SiC SALTran and power SiC BJT

Fig. 7 Current gain of power SiC SALTran and power SiC BJT

Fig. 8 Gummel plots of power SiC SALTran and power SiC BJT

Fig. 9 Current gain versus collector current for different temperature for (a) power SiC

SALTran and (b) power SiC BJT

Fig. 10 Normalized peak current gain of power SiC SALTran and power SiC BJT

Fig. 11 Peak current gain versus 1/KBT for power SiC SALTran and and power SiC BJT.


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N+ 4H-SiC Substrate

P, JTE P, JTE

P, 2.5x1017 cm-3, 0.4 mP+

P

+

N, 0.3 m

Emitter

Base

Collector

N-, 2.5 x 1015 cm-3, 20 m

N+ 4H-SiC Substrate

P, JTE P, JTE

P, 2.5x1017 cm-3, 0.4 mP+

P

+

N, 0.3 m

Emitter

Base

Collector

N-, 2.5 x 1015 cm-3, 20 m

Fig.1


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0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

-4

-3

-2

-1

01

2

3

BaseEmitter

Metal

Fermi level

Conduction band

Valence band

Power SiC SALTran

Power SiC BJT

Energy(eV)

Distance from emitter contact (m)

(a)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

-5

-4

-3

-2

-1

0

1

2

3

4

5

BaseEmitter

Metal

VBE

=2.96 VHole quassi fermi level

Valence band

Conduction band

Electron quassi fermi level

Power SALTran

Power SiC BJT

Energy(eV)


(b)

Fig. 2


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0.0 0.1 0.2 0.31010

1014

1018

1022

Power SiC SALTran

Power SiC BJT

E

lectronconcentratio

n(cm-3)


0.0 0.1 0.2 0.31010

1014

1018

1022

Power SiC SALTran

Power SiC BJT

E

lectronconcentratio

n(cm-3)


Fig. 3


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0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.71010

1012

1014

1016

1018VBE=2.96 V Emitter base junction

Power SALTran

Power SiC BJTCarrierconcentratio

n(/cm

3)


0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.71010

1012

1014

1016

1018VBE=2.96 V Emitter base junction

Power SALTran

Power SiC BJTCarrierconcentratio

n(/cm

3)


Fig. 4


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0.0 0.1 0.2 0.3

0

100

200

300

400

500

Power SiC SALTran

Power SiC BJT

Electricfield(kV/cm)


Fig. 5


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0 20 40 60 80 1000.0

0.1

0.2

0.3

0.4

0.5

IB=0.5 A to 2 A

Step 0.5 A

Power SiC SALTran

Power SiC BJT

Collectorcurrent(mA)

Collector emitter voltage (V)

Fig. 6


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10-9 10-8 10-7 10-6 10-5 10-4 10-30

20

40

60

80

100

120

140 VCE

= 10 V

Power SiC SALTran

Power SiC BJT

Currentgain

Collector current (A)

Fig. 7


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1.5 2.0 2.5 3.0 3.5

10-15

10-13

10-11

10-9

10-7

10-5

10-3

IB

IC

VCE

=10 V

Power SiC SALTran

Power SiC BJT

Collectorandbasecur

rents(A)

Base emitter voltage (V)

Fig. 8


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10-8 10-7 10-6 10-5 10-4 10-30

20

40

60

80

100

120

140300 K

450 K

T= 300 K to 450 K

Step 50 K

Currentgain

Collector current A (a)

10-8

10-7

10-6

10-5

10-4

10-30

10

20

30

40

50

60

70

80T=300 K to 450 K

Step 50 K

450 K

300 K

Currentgain

Collector current (A)

(b)

Fig. 9


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250 300 350 400 450 500

0.6

0.7

0.8

0.9

1.0

Power SiC SALTran

(300

=140)

Power SiC BJT

(300=70)

(T)/300

Temperature (K)

Fig. 10


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24 28 32 36 4010

100E

g

=-37.5 meV

Eg=-44.5 meV

Power SiC SALTran

Power SiC BJTPeakcurrentgain

1/KBT(eV-1)

24 28 32 36 4010

100E

g

=-37.5 meV

Eg=-44.5 meV

Power SiC SALTran

Power SiC BJTPeakcurrentgain

1/KBT(eV-1)

Fig. 11

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Enhanced Current Gain in SiC Power BJTs using a novel Surface Accumulation Layer Transistor (SALTran) Concept