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Industry Architecture and Entrepreneurial Opportunities:

The case of the U.S. semiconductor industry

Abstract

This is the first paper to empirically analyze the relationship between the emergence of

vertical disintegration and of entrepreneurial opportunities, where this paper uses the concept

of industry architecture to analyze vertical disintegration. One form of vertical disintegration

emerged between design and manufacturing within the semiconductor industry and a second

form emerged between the semiconductor and electronic systems industries. A critical aspect

of the second form of vertical disintegration has been the increasing sales of so-called

standard modules that reduce the transaction costs of having different firms design

electronic systems and design semiconductors and that also reduce the importance of having

capabilities in both electronic systems and semiconductors. The impact of vertical

disintegration on entrepreneurial opportunities is analyzed by showing how de novo

entrepreneurial startups were more likely to be suppliers of these standard modules than non-

standard semiconductors and to be design houses or foundries than to be integrated (both

design and manufacturing) suppliers of semiconductors, as the vertical disintegration and thus

the new form of industry architecture emerged.

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1. Introduction

Research on vertical disintegration has steadily increased over the last 15 years as its

increasing occurrence and importance have become widely recognized. The visible hand

(Chandler, 1977) has been partially replaced by the virtual hand (Langlois, 2003, 2007;

Chesbrough, 2003) where these visible and virtual hands guide the emergence of vertical

disintegration in either a top-down or bottom-up (Jacobides, 2005; Jacobides and Winter,

2005) process. These and related research have concluded that the emergence of vertical

disintegration has challenged incumbents and thus this research implies that vertical

disintegration has led to opportunities for new entrants in a variety of industries (Langlois,

1992; 2003, 2007; Baldwin and Clark, 2000; Arora et al, 2001; Chesbrough, 2003).

Furthermore, the increasing extent to which vertical disintegration is emerging in many

industries has led to an increasing interest in so-called industry architectures and a

recognition of the limitations in the product life cycle model (Jacobides, Knudsen and Augier,

2006).

Industry architectures are an abstract description of the economic agents within an

economic system and they represent the degree of vertical (dis)integration in the industry

(Jacobides, Knudsen and Augier, 2006). Changes in industry architecture can come from

technological, institutional, or social changes that impact on the way in which economic

agents divide up work. In particular, reductions in transaction cost can reduce both the costs

of having work done by multiple agents and the importance of integrative capabilities and

thus facilitate the emergence of vertical disintegration (Brusoni and Prencipe, 2001;

Jacobides, 2005; Jacobides and Winter, 2005). These reductions in transaction costs can come

from the emergence of standards, modular designs (Langlois, 2003, 2007), and other events

such as governments (or legal systems) requiring the un-bundling of products, restricting a

firms ownership/market share in a market, or approving standards (Arora et al, 2001; Caves,

2002; Kenney, 2003; Steinmueller, 2003) where these events can emerge in either a bottom-

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up or top-down process (Jacobides, 2005; Jacobides and Winter, 2005).

In spite of this wide agreement that vertical disintegration is occurring and is somehow

related to entrepreneurial opportunities, however, the specific connection between the

emergence of vertical disintegration and entrepreneurial opportunities has not been

empirically examined and recognized partly because the literature cited in the previous

paragraph primarily emphasizes the impact of vertical disintegration on incumbents. More

specifically: 1) how might vertical disintegration emerge and create opportunities; 2) are new

entrants able to exploit these opportunities better than are incumbents; 3) among new entrants,

are ones that are founded to enter the industry (de novo) able to exploit these opportunities

better than ones that enter from another industry (de alio); 4) among firms that are founded to

enter the industry, are more recently founded ones able to exploit these opportunities better

than less recently founded ones; and 5) if so, why?

This paper partially addresses these questions through an analysis of the U.S.

semiconductor industry. The semiconductor industry was chosen as an object of analysis

because the number of firms that have entered this industry just in the U.S. is in the thousands

(Braun and MacDonald; 1982; Borrus, 1987; Saxenian, 1994; Angel, 1994) and the fact that

semiconductors represented the fourth largest recipient of U.S. venture capital funding (Dow

Jones, 2006) in 2004 suggests that large numbers of firms (Clark, 2006) are still being

founded to enter the industry. It focuses on the U.S. because the number of entrepreneurial

startups and the extent of vertical disintegration are much larger in the U.S. than in other

semiconductor producing nations. In focusing on the U.S., this paper also challenges the

conventional wisdom that early entrants failed solely because they did not develop the

appropriate capabilities (Tilton, 1971; Wilson, Ashton, and Egan, 1980; Braun and

MacDonald, 1982; Malerba, 1985; Utterback, 1994) or so-called core competencies (Langlois

and Steinmueller, 1999).

This paper directly analyzes changes in the architecture of the semiconductor industry and

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indirectly analyzes changes in the architecture of the electronic systems industries. In the

former, the emergence of vertical disintegration between design and manufacturing represents

changes in the architecture for the semiconductor industry. In the latter, the emergence of so-

called standard semiconductor modules (e.g., memory and microprocessors) and open

interface standards for them changed the physical architectures of electronic systems, led to

vertical disintegration between electronic systems and semiconductors, and thus changed the

architecture of electronic systems industries. Both changes in industry architecture emerged

through an interaction between transaction costs and capabilities, challenged incumbents, and

provided opportunities for new entrants including so-called de novo entrepreneurial startups.

2. Theoretical discussion

Understanding where entrepreneurs should look for opportunities remains an important

issue for practitioners and academics. The popular press focuses on final products such as

MP3 players (e.g., i-pod), mobile phones (e., i-phone, Google phone), Internet search (e.g.,

Google), tablet computers (e.g., i-pad) and personal digital assistants. The literature on

entrepreneurship has found that entrepreneurs do better in software than hardware (Audretsch,

1991) or in industries with rapid growth, low capital intensity, small scale, and low

concentration (Bygrave and Zacharakis, 2003; Shane, 2004; Baron and Shane 2005). The

literature on technological management and innovation has found that technological

discontinuities, particularly those that destroy competencies, provide opportunities for new

entrants (Tushman and Anderson, 1986; Anderson and Tushman, 1990; Henderson and Clark,

1990; Christensen, 1997) particularly when firms enter before a dominant design has

emerged (Utterback, 1994; Suarez and Utterback, 1995).

The existing management and economic literature on early competition in the

semiconductor industry largely focuses on the competence-destroying nature of transistors

and integrated circuits (ICs). Suppliers of vacuum tubes were not able to succeed in

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semiconductors because transistors and ICs required a different set of capabilities than did

vacuum tubes where the new capabilities were defined by the planar process (Tilton, 1971;

Braun and MacDonald, 1982; Malerba, 1985; Utterback, 1994), which is often defined as the

dominant design in the industry (Utterback, 1994). Similarly, most vertically integrated

suppliers of electronic systems failed in semiconductors because they did not devote

sufficient attention to semiconductors (Wilson, Ashton, and Egan, 1980) and to the

development of the right capabilities, or so-called core competencies in them (Langlois and

Steinmueller, 1999).

This paper focuses on vertical disintegration and industry architecture, which have not

been linked to entrepreneurial opportunities by the entrepreneurship or technology

management literatures. Although there are many terms that can be used in place of

industry architecture, this paper uses the term industry architecture because it has been

successfully used to describe the evolution of many industries, including mortgage banking

(Jacobides, 2005; Jacobides and Winter, 2005), construction, (Cacciatori and Jacobides,

2005), apparel (Jacobides and Billinger, 2006), and mobile Internet (Tee and Gawer, 2009),

and because it incorporates many of these other terms. For example, the evolution of

industry architecture primarily involves an interaction between transaction costs and

capabilities (Jacobides, 2005; Jacobides and Winter, 2005), which are separately emphasized

by many other scholars (Kogut and Zander, 1992; Leonard-Barton, 1992; Teece, Pisano, and

Shuen, 2003; Baldwin, 2007; Wolter and Veloso, 2008).

Reductions in transaction costs can come from a variety of sources where modular

designs are one example that is emphasized by a number of other scholars. Modular designs

are those in which the interfaces that determine how the functional components or modules

in a product or process design will interact are specified to enable the substitution of

component variations within the design (Ulrich, 1995; Sanchez and Mahoney, 1996; Brusoni

and Prencipe, 2001, 2006). The term standard or interface standard (Farrell and Saloner,

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1985; Shapiro and Varian, 1999) is often used to define the way in which these different

modules interact, particularly when products from different firms are compatible with the

same interfaces. The greater the extent to which these modular designs or standard interfaces

are open, the greater the chances that vertical disintegration will emerge and challenge

incumbents. For example, although the specific connection has not been empirically

examined and recognized, the emergence of relatively open modular designs or open standard

interfaces have challenged incumbents in the mainframe (Baldwin and Clark, 2000), personal

(Langlois, 1992), and other computer (Christensen et al, 2002), mortgage banking (Jacobides,

2005), biotechnology (Chesbrough, 2003), audio equipment (Langlois and Robertson, 1992)

and telecommunication (Steinmueller, 2003) industries and thus their emergence has probably

enabled the entry of some new firms.

In the U.S. semiconductor industry two changes in industry architecture have been

gradually occurring since the 1970s. First, the gradual emergence of so-called standard

semiconductor modules such as memory and microprocessors has caused system suppliers to

design their electronic systems around these standard modules. These standard modules

include open interface standards that reduce the transaction costs associated with different

firms designing semiconductors and electronic systems and that reduce the importance of

capabilities in electronic system design for semiconductor suppliers, and thus enable vertical

disintegration to emerge between electronic systems and semiconductors. Second, the

separation between design and manufacturing represents changes in the architecture of the

semiconductor industry. This separation depended on reductions in the transaction costs

associated with different firms doing design and manufacturing, which also reduced the

importance of capabilities for integrating design and manufacturing, and thus enabled vertical

disintegration to emerge between so-called design houses and foundries.

The degree to which these changes in industry architecture provided entrepreneurial

opportunities for new entrants can be measured by looking at the relative success of

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incumbents versus new entrants in these standard modules and as design houses or foundries.

Since any firm can be defined as a new entrant to a new industry like the semiconductor

industry, this paper distinguishes between firms that were founded to enter the semiconductor

industry, i.e., de novo entrepreneurial startups, and firms that entered from another industry,

i.e., de alio firms. All of the de alio firms in the semiconductor industry entered from one or

more electronic system industries such as military, computer, telecommunication, or

broadcasting (and some were also producers of vacuum tubes or other electronic components).

Since many of them produced semiconductors for their electronic systems business or at least

used their systems business to determine which semiconductors to introduce (Braun and

MacDonald, 1982; Tilton, 1971; UN, 1986; Steinmueller, 1987), they were more likely to

supply non-standard semiconductors both to themselves and to other firms than standard

semiconductor modules. On the other hand, de novo firms were probably focused on a

broader set of potential customers than were the de alio firms and thus were more likely to

supply standard semiconductor modules than non-standard semiconductors. This leads to two

hypotheses:

Hypothesis 1: as the sales of standard modules increased, de novo entrepreneurial startups

were more likely to be suppliers of standard modules than non-standard semiconductors

Hypothesis 2: even as the sales of standard modules increased, de alio firms were still more

likely to be suppliers of non-standard semiconductors than standard modules

Similarly, just as de alio firms are more likely to continue producing non-standard

semiconductors even as the sales of standard modules increase, de alio firms are more likely

to continue being integrated producers even as a separation between design and

manufacturing becomes possible. On the other hand, de novo entrepreneurial startups are

expected to more easily adapt to new industry architectures and be design houses or foundries

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than be integrated producers of semiconductors. This leads to two additional hypotheses:

Hypothesis 3: as it becomes possible for different firms to do design and manufacturing, de

novo entrepreneurial startups are more likely to be design houses or foundries than to be

integrated producers of semiconductors

Hypothesis 4: even as it becomes possible for different firms to do design and manufacturing,

de alio firms are still more likely to be integrated producers of semiconductors than to be

design houses or foundries.

Also because of difficulties of adaptation, more recently founded de novo entrepreneurial

startups are expected to more easily adapt to new industry architectures and thus be suppliers

of standard modules and be design houses or foundries than will less recently founded de

novo entrepreneurial startups. This leads to two more hypotheses:

Hypothesis 5: a larger percentage of recently founded de novo entrepreneurial startups will

be suppliers of standard modules than will less recently founded de novo entrepreneurial

startups.

Hypothesis 6: a larger percentage of recently founded de novo entrepreneurial startups will

be design houses or foundries than will less recently founded de novo entrepreneurial

startups.

3. Methodology

Changes in industry architecture including the emergence of standard semiconductor

modules were identified using the primary and secondary literature on the semiconductor

industry including academic papers and books from the management, economic, and

historical fields, practitioner-oriented accounts, technical accounts, and encyclopedic histories.

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Standard semiconductor modules are defined as standard semiconductor products that include

standard interfaces and that are widely used in many electronic systems (have sales that

exceed 5% of total semiconductor sales). Almost all accounts of the semiconductor industry

emphasize the emergence of design houses, foundries, and standard modules such as logic,

memory, microprocessors, and ASICs (Braun and MacDonald, 1982; Malerba, 1985; Borrus,

1987; Steinmueller, 1987; Gruber, 1994; Flamm, 1996); more recent accounts emphasize

ASSPs (ICE, 1996; Turley, 2003). These sources were supplemented with other widely

referenced histories of the semiconductor industry, including academic papers (Macher et al,

2002; Linden and Somaya, 2003; Dibiaggio, 2007) and insider accounts (Walker, 1992), with

searches on the Internet and by perusing almost every issue of Electronics and Electronic

Business between 1960 and 2005.

An analysis of firms would ideally focus on sales or even profitability data for their

semiconductor businesses. However, sales and certainly profitability data are difficult to

obtain for individual businesses within a single firm and many of the leading U.S.

semiconductor suppliers have operated in multiple businesses for many years including ones

associated with various electronic systems (i.e., de alio systems suppliers). Therefore, this

paper does two different types of analyses. First, it contrasts the composition of firms in

Chapter 4 of Tiltons 1971 seminal book with those in ICEs (1996) database for 1995. Tilton

lists (in his Table 4-1) 47 firms that offered semiconductor transistors for at least three years

between 1951 and 1968 and mentions in the text an additional firm that only offered ICs for

more than three years thus providing a total of 48 firms. Integrated Circuit Engineering

analyzes 130 U.S. semiconductor suppliers for a single point in time, 1995, with almost 400

pages of data (ICE, 1996). Three firms were eliminated from this database because they

provided a service not relevant to the study (providing discontinued products) and two firms

were eliminated because there was insufficient information for them, leaving a total of 125

firms.

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The second type of analysis focuses on the largest U.S. suppliers of semiconductors in the

global market and on the changes in the composition of these suppliers over the life of the

semiconductor industry. Although focusing on the most successful firms prevents one from

concluding whether one de novo entrepreneurial strategy is better than another strategy, it

enables one to compare the extent to which successful de alio and de novo firms adapted to

the changes in industry architecture. Lists of the top U.S. semiconductor suppliers in terms of

sales were gathered from many sources including Tilton (1971), Braun and MacDonald

(1982), the United Nations (UN, 1986), Dataquest (Yoffie, 1993), ICE (1996), Electronic

Business (Edwards, 2006) and Compustat. All of these sources included both de novo and de

alio firms in the rankings and the more recent sources (UN, 1986; ICE, 1996; Edwards, 2006)

included captive sales for the de alio firms1. From these sources, lists of the top suppliers

were assembled for 1955 (12 firms), 1965 (14 firms), 1983/4 (35 firms), 1995 (35 firms), and

2005 (35 firms).

In some cases multiple sources were used in order to create a longer list of firms for a

single year than any single source contained. For example, the top 25 U.S. firms in 2005 were

identified from the top 25 ones that were in the top 50 global semiconductor firms in 2005

(Edwards, 2006) and the 26th to 35th U.S. firms were identified using Compustats listing of

firms in the semiconductor industry. Firms in Compustats list that only do assembly or test

were excluded. Because Compustat only classifies firms as semiconductor ones if they are

primarily suppliers of semiconductors, I also checked the 2005 semiconductor sales of firms

that were in the 1995 database (ICE, 1996) in order to ensure that all de alio firms were

included in the top 35 firms in 2005.

1 A lack of data on captive sales during the early years of the industry causes the analysis to underestimate

the importance of de alio firms; solving this problem would provide further support for the papers

hypotheses.

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Largely using the sources mentioned above2 each firm was classified in terms of three

variables: 1) as either de alio or de novo; 2) as either integrated producer, design house or

foundry; and 3) as either a supplier of standard modules or non-standard semiconductors.

Firms that designed or produced anything else before they released semiconductors are

defined as de alio firms and thus this paper uses a more restrictive definition of de novo firms

than has been used in other analyses of the semiconductor industry (Langlois and

Steinmueller, 1999)3. Spinoffs, of which there were only a few, are only considered de novo

firms if: 1) they are spun off from a de novo firm; or 2) they are spun off from a de alio firm

that did not integrate a de novo acquisition with the rest of the de alio firms semiconductor

business. The founding years for the de novo firms were also gathered. In the first case the

year of the parents establishment is used as the founding year and in the second case the year

of the original de novo firms establishment is used as the founding year.

Forty four unique de novo and 27 unique de alio firms were identified in the top ranked

U.S. semiconductor suppliers in 1955, 1965, 1983/4, 1995, and 2005 thus providing 131 data

points for these firms along with 48 unique firms for the early years of the industry (1951-

1968) and 125 unique firms for 1995. They are classified as a supplier of standard modules

only if more than 50% of their sales are from a specific standard module such as logic,

memory, microprocessors, ASICs, and ASSPs. In the case of ASSPs, the analysis of firm

descriptions looked for references to the terms ASSP, standard module, or standard product.

Because standards and standard modules have emerged more for digital than for analog ICs

2 The exception was for the firms in the 2005 ranking; these classifications relied on annual reports that

were largely found on the Internet.

3 For example, Langlois and Steinmuellers (1999) analysis defines or implies that Motorola, TI, General

Electric, General Instruments and Rockwell are vertically disintegrated firms in spite of the fact that they

all produced electronic systems before they produced semiconductors and were founded before the

semiconductor industry was formed in the early 1950s. Although defining them as de novo firms would

increase the statistical support for this papers hypotheses, this paper defines them as de alio firms.

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and systems (Malerba; 1985; Kressel and Lento, 2007), most of the non-standard

semiconductors involved analog or so-called mixed-signal ICs; the latter ICs combine both

digital and analog circuitry on a single IC. The integration of analog and digital circuitry (as

Moores Law has allowed it) on a single IC has slowed the emergence of standard modules in

these mixed-signal ICs and in combination with their larger features sizes (and thus lower

factory capital costs) have slowed the vertical disintegration between design houses and

foundries for analog circuits (Turley, 2003).

4. Results

Table 1 shows the percentage of U.S. semiconductor suppliers that are classified as de

novo firms. The percentage grew from 31% in the early days of the industry (Tiltons list of

participants from 1951 to 1968) to about 82% by 1995 (ICEs database in 1995). As for the

top ranked firms, the percentage grew from 8.3% in 1955 to 47% in 1983/4 and had reached

60% by 1995.

Table 2 lists the standard semiconductor modules and shows how the percentage of

semiconductor sales that are represented by them has grown steadily between 1965 and 1986.

Other sources that are discussed in the subsequent sub-sections state that this percentage has

continued to grow since 1986 particularly for ASICs and ASSPs. Figure 1 summarizes the

industry architecture for the electronic system and semiconductor industries that has been

brought about by emergence of these standard modules and other events.

Table 3 shows the ratio of de novo to the total number of firms for standard modules vs.

non-standard semiconductors and for design houses and foundries vs. integrated producers

for the top ranked suppliers in the relevant years. The corresponding proportions of de alio to

the total number of firms can be easily calculated from the numbers in this table. Table 4

focuses on the 125 firms in ICEs 1996 report for 1995 and it lists the number of de novo and

de alio firms for standard modules vs. non-standard semiconductors and for design houses

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and foundries vs. integrated producers. Table 5 focuses on the de novo firms in ICEs (1996)

database and it distinguishes between those that were founded between 1955 and 1980 and

those that were founded between 1981 and 1994.

The data in Tables 3 through 5, hypothesis testing for the difference between two

binomial proportions (Mitra, 1993, p. 119), and the changes in industry architecture, which

are described in subsequent sub-sections, were used to test hypotheses 1 through 6 in each

relevant year. Subsequent sub-sections describe how standard modules began emerging in the

1970s and thus these changes began to have an impact on the top-ranked firms in the 1983-4,

1995, and 2005 rankings and on the composition of all firms in the 1995 (ICE, 1996)

database. These sub-sections also describe how it became easier to separate design from

manufacturing beginning in the early 1980s and thus these changes began to have an impact

on the top-ranked firms in the 1995 and 2005 rankings and on the composition of all firms in

the 1995 (ICE, 1996) database. Therefore, hypotheses 1 and 3 are addressed in the 1983-4,

1995 and 2005 rankings. Hypotheses 2 and 4 are addressed in the 1995 and 2005 rankings.

The larger proportions of de novo, and the smaller proportions of de alio, to the total

number of firms supplying standard modules than supplying non-standard semiconductors are

significant at the 0.001 level for 1983/4, 1995 and 2005 in Table 3 and overall for Table 4

(ICEs database of 125 firms in 1995). The larger proportions of de novo, and the smaller

proportions of de alio, to the total number of firms in design houses than in integrated

producers are significant at the 0.001 level for 1995 and the 0.03 level for 2005 in Table 3

and at the 0.001 level overall for Table 4 (1995 ranking). Focusing just on de novo firms in

the 1995 database (Table 5), the larger percentages of recently (after 1980) than less recently

founded (before 1981) de novo entrepreneurial startups as suppliers of standard modules and

as design houses are significant at the 0.001 level. Excluding foundries, this confirms

Hypotheses 1 through 6. Since the largest independent and dependent foundries in the world

are Taiwanese, Singaporean, and Japanese (Edwards, 2006) and there are only four foundries

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in the 1995 data base, the hypotheses concerning foundries could not be tested. The

subsequent sub-sections describe the emergence of standard modules, design houses, and

foundries and thus the evolution in the industry architecture for the semiconductor industry

along with more details about the success of de novo entrepreneurial startups.

4.1 Early years of the semiconductor industry

The semiconductor industry was formed in the early 1950s and it was initially dominated

by de alio systems firms that produced both semiconductors and various electronic systems,

such as ones for the military, broadcasting, and telecommunication industries. One of the

largest reasons why de alio suppliers dominated the early years of the semiconductor industry

was because there was a need for capabilities in both semiconductor and electronic system

design and in both product and process design for semiconductors. Capabilities were needed

in system design in order to define the types of transistor designs and the combination of

them that were needed for various applications, partly since many of these discrete transistors

were customized for each application (Tilton, 1971; Braun and MacDonald, 1982;

Steinmueller, 1987). Capabilities were needed in manufacturing in order to properly design

transistors. In fact, virtually every account of the early years of the semiconductor industry

emphasizes a close relationship between product and process design and the key role that

system suppliers such as Western Electric/AT&T, RCA, General Electric, Westinghouse, and

Philco played in these early developments (Tilton, 1971; Braun and MacDonald, 1982;

Malerba, 1985; Steinmueller, 1987). Improved diffusion, etching, masking, and oxidation

processes enabled new forms of transistors to be made where the sum total of these

improvements are often called the planar process (Tilton, 1971; Braun and MacDonald, 1982;

Malerba, 1985), which some management scholars consider a dominant design for transistors

(Utterback, 1994). This process defined the basic steps for producing semiconductors where

the top 18 firms in terms of patent recipients for semiconductor processes between 1952 and

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1968 were de alio system firms (Tilton, 1971, Table 4-2).

4.2 ICs and logic chips

The first ICs were introduced in the early 1960s and they can be divided into analog and

digital ones (Malerba, 1985). Early applications for analog ICs included ones in military,

broadcasting (both radio and television), and telecommunication systems where the ICs

processed audio or video signals. Because of the continued difficulties associated with

defining standard ICs for analog applications, the design of analog ICs still required (and to

some extent still requires) close cooperation between system and IC design in order to define

the types of ICs designs and the combination of them that were needed for various

applications and thus de alio suppliers continued to dominate these markets (Steinmueller,

1987). For example, the top 15 U.S. semiconductor suppliers in 1965 (Braun and MacDonald,

1982) included manufacturers of broadcasting systems and receivers (e.g., Motorola, RCA,

GE, Sylvania, Philco-Ford, Westinghouse, and Delco Radio), of telecommunication systems

(Western Electric), and of defense systems (TRW and Raytheon), all of which produced large

numbers of analog ICs for internal use (Steinmueller, 1987). To some extent these same de

alio firms continue to dominate the markets for analog circuits.

Digital ICs were first used for logic functions in computers and defense products and now

are used in every type of electronic product. So-called logic gates perform simple logic

functions where the mathematics of Boolean Logic is used to combine these simple logic

gates into more complex electronic circuits such as those that add and multiply (Malerba,

1985; Borrus, 1987; Kressel and Lento, 2007). Standard inputs and outputs for these logic

gates (Murphy et al, 2000) emerged through competition between different IC logic families

and these standard inputs and outputs reduced the transaction costs associated with having

different firms design logic chips and design electronic systems. Furthermore, these

reductions in transaction costs also reduced the number of capabilities that semiconductor

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suppliers needed in electronic system design and thus provided opportunities for new entrants

to the semiconductor industry such as de novo entrepreneurial startups. These startups

increased their share of the semiconductor market as the percentage of semiconductor sales

that are represented by digital logic ICs increased in the 1970s (See Table 2). Along with TI, a

de alio firm, three de novo startups, Signetics, Fairchild, and National Semiconductor, were

the leading suppliers of logic chips in the 1970s (Borrus, 1987; Malerba, 1985) and were in

the top ten producers of semiconductors in 1975 (Braun and MacDonald, 1982). Most logic

chips were gradually replaced by ASICs and ASSPs in the 1980s

4.3 Processors and memory

The increasing number of transistors on a chip (i.e., Moores Law) gradually enabled

semiconductor suppliers to introduce a variety of processors and memory chips during the

1970s where these processors and memory chips enabled new forms of physical and industry

architectures to emerge in various electronic systems (Borrus, 1987; Steinmueller, 1987;

Jackson, 1998; Turley, 2003). Simple forms of microprocessors, called micro-controllers, had

evolved from the first microprocessors and were used for many years in a large variety of

non-computer applications. Digital signal processors emerged for applications that required

the processing of audio and video digital signals. They became widely used in CD players,

mobile phones, and video graphic chips (Turley, 2003) and are now generally classified as

ASSPs (see below) because they are designed for specific electronic systems.

The wide use of microprocessors also caused new forms of memory to emerge. While the

early programs for microprocessors were stored in so-called Read-Only Memory (ROM), the

ability to modify programs in so-called Programmable ROMs (PROMs), and to change the

programs with in Erasable or Electrically Erasable PROMs (EEPROMs) reduced the

transaction costs associated with different firms designing (supplying) and programming

(using) the microprocessors. Other forms of memory such as DRAMs (Dynamic Random

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Access Memory), SRAMs (Static Random Access Memory), and flash memory also emerged

and further reduced these transaction costs (Borrus, 1987; Jackson, 1998; Gruber, 1994;

Turley, 2003). As shown in Table 2, the sales of microprocessors, memories, and logic chips

represented 12%, 36%, and 25% respectively of total IC sales or 56% of total semiconductor

sales in 1984.

In combination, these new forms of standard semiconductor modules increased the

number of opportunities for de novo firms because they reduced the transaction costs

associated with different firms designing the standard semiconductor modules and the

electronic systems and reduced the importance of capabilities in system design for

semiconductor suppliers. As shown in Table 1, the percentage of firms that are de novo ones

among the top 12 ranked firms rose from 16.6% in 1965 to 50% in 1983/4. Fairchild

remained in the top 12 as a leader in multiple standard modules (bipolar memories, logic

chips, and microprocessors) and thus is classified as a supplier of non-standard

semiconductors in 1983/4. Of the five new members of the top 12 in 1983/4 that were de

novo firms, three of them are classified as suppliers of standard modules; Intel and AMD

focused on microprocessors and Signetics focused on logic chips. Of the de novo firms

among the top 35 ranked firms (percentages shown in Table 1), five of them are classified as

suppliers of logic, memory or microprocessors in 1983/4, 1995 and in 2005. Of the 59 de

novo suppliers of standard modules in the 1995 database (ICE, 1996) (See Table 3), 21 are

classified as suppliers of memory or processor ICs.

4.4 ASICs

ASICs (Application Specific ICs) are semi-custom ICs that are designed for specific

applications. Table 6 (Thomke, 2003) contrasts three types of ASICs with each other and with

full-custom ICs. In general, full-custom chips have the highest performance and lowest unit

manufacturing costs, but the highest development costs and longest development times of the

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approaches summarized in Table 6. As one moves to the right in Table 6, standard cell

designs, gate arrays (Posa, 1980; Fields, 1982; Bogle, 1984; Bourbon, 1984), and

programmable logic devices have progressively lower performance and higher unit

manufacturing costs, but much lower development costs and times. Thus, system designers

move to the right in their choices of ASICs in Table 6 as the volumes of their systems decline

(Thomke, 2003; Rowen, 2004).

Although some suppliers of electronic systems had been designing ASICs for their low-

volume systems (e.g., military systems) since the 1960s (Walker, 1992), rapid growth did not

start until the early 1980s (See Table 2) when the increasing number of transistors on a chip

(i.e., Moores Law) led to an increasing emphasis on reducing the development costs of ICs

and as reductions in transaction costs enabled a new form of industry architecture to emerge

for both ASICs (See Figure 2) and for electronic systems (See Figure 1). These gradual

reductions in transaction costs are being driven by five different trends.

First, high-level symbolic design methods from Carver Mead and Lynn Conway

substantially reduced the cost of designing complex ICs including ASICs (Beresford, 1983;

Bourbon, 1984; Baldwin and Clark, 2000). Second, as opposed to designing the complete

ASIC, new entrants began providing libraries of pre-designed circuitry (i.e., standard cells),

transistor arrays, and the design tools necessary for suppliers of electronic systems to

customize these arrays and libraries of cells for their applications. This caused these standard

cells, transistor arrays, and design tools to emerge as standard modules for ASICs, where

different interface standards emerged for the three types of ASICs shown in Figure 2 and

Table 64. Furthermore, like the discussion of logic chips, microprocessors and memory ICs

4 Suppliers of standard cell designs provide libraries of pre-designed circuit blocks that are selected by

system engineers and that have increased in complexity as the number of transistors on a chip (i.e.,

Moores Law) has increased (Fields, 1982). The term SoC is now used when these pre-designed blocks

include microprocessors and large blocks of memory (Linden and Somaya, 2003; Thomke, 2003; Rowen,

2004). Suppliers of gate arrays provide standard arrays of transistors that are customized by system

19

above, these standards emerged through competition between different suppliers of ASICs

and these standards reduced both the transaction costs associated with designing electronic

systems from externally available cells, arrays, and design tools and the importance of

capabilities in electronic system design for ASIC suppliers.

Third, the emergence of so-called dimensionless and scalable design rules reduced the

transaction costs associated with different firms doing the design and manufacture of ASICs

and other ICs. These rules define geometrical relationships between line widths, material

thicknesses, power consumption, and speed and their emergence reduced the need for

communication between design and manufacturing even as designs had to be updated for

smaller feature sizes (Baldwin and Clark, 2000; Murphy et al, 2000; Critchlow, 1999; Macher

et al, 2002). Fourth, the separation between design and manufacturing is also being driven by

the rising cost of new manufacturing facilities that are a barrier to entry for manufacturers

and thus for integrated producers of ICs (ICE, 1997; Macher et al, 2002). Fifth, the

emergence of standard CAD tools and the Internet further reduced the transaction costs

associated with different firms doing the design and manufacture of ICs (Walker, 1992;

Macher et al, 2005).

In summary, the last three trends have facilitated the emergence of vertical disintegration

between design and manufacturing and the first two trends have facilitated the emergence of

certain portions of ASICs (mentioned above and shown in Figure 2) as standard modules and

thus the increasing vertical disintegration between semiconductors and electronic systems.

The impact of vertical disintegration between design and manufacturing on the success of de

novo firms can be seen in the large percentage of de novo firms in Tables 3 and 4 that are

engineers who design the so-called metal mask and thus choose the connections between transistors

(Posa, 1980; Bogle, 1984; Bourbon, 1984). The level of standardization is taken one step further with so-

called programmable logic devices (PLDs) that can be customized in a matter of minutes by connecting

specific fuses (Cole, 1988; Ristelhueber, 1996; Thomke, 2003).

20

design houses and that were statistically tested at the beginning of the results section. Fifteen

of 18 (83%) of the design house data points in Table 3 and 92% (58 of 61) of the design

houses in 1995 (See Table 4) were de novo firms, and 88% (51 of 58) of the design houses in

1995 (See Table 5) were both de novo firms and were founded after 1981. On the

manufacturing side, as of late 2007 there were more than 150 foundries in the world where

many of them specialize in different types of materials, processes, transistor designs, and

logic families5.

The impact of the emergence of standard modules on the vertical disintegration between

design and manufacturing on the success of de novo firms can be seen in the large percentage

of de novo firms in Tables 3 and 4 that are suppliers of standard modules (and that were

statistically tested at the beginning of the results section). Four (VLSI Technologies, LSI

Logic, Altera, and Xilinx) of the five unique firms that are classified as ASIC suppliers in the

top ranked firms in 1983/4, 1995, and 2005 and 10 of the 11 data points for these years are de

novo firms. Eleven of the 59 de novo suppliers of standard modules (See Table 3) in the 1995

database (ICE, 1996) are classified as suppliers of ASICs of which 9 of them were design

houses and all 9 of them were founded after 1981.

Furthermore, there is an interaction between the two types of vertical disintegration and

the emergence of opportunities for de novo firms. As shown in Table 5, 45 (3+42) of the de

novo firms in the 1995 database (ICE, 1996) were both design houses and providers of

standard modules and 27 (13+14) de novo firms that were both integrated producers and

providers of non-standard semiconductors versus 27 ones (4+10+7+4) that were one or the

other. Using hypothesis testing for the difference between two binomial proportions (Mitra,

1993, p. 119), the interaction between the two types of opportunities (standard modules and

5For example see:

http://electronic-contract-manufacturing.globalspec.com/LearnMore/Electrical_

Electronic_Contract_Manufacturing/Semiconductor_Foundry_Services

21

design houses) are significant at the 0.001 level.

4.5 ASSPs

The term ASSP refers to standard IC chips that are designed for a specific system/product

and often a specific module in that system/product. Since they are often designed using

ASIC-design techniques, one key difference with ASICs is that they are sold as standard as

opposed to custom products in the market (Walker, 1992). The emergence of high-volume

digital electronic products in the 1980s and 1990s is one reason why the market for such

ASSPs has grown and is still growing. Factors that drove reductions in the transaction costs

for different firms designing the ASSPs and the electronic systems include the vertical

disintegration between the design and manufacture of semiconductors that was discussed

above, the move from analog to digital design of electronic systems, and the emergence of

open standards in computers, telecommunication systems, and consumer electronic products.

One of the first large markets for ASSPs was in personal computers (PCs) as standards

emerged and as Intel and other de novo firms began to customize processors and other ICs for

the PC in response to the growing market for them in the 1980s. For example, Chips and

Technologies successfully reversed engineered IBMs so-called BIOS chips in the early

1980s (Cole, 1987) and other de novo startups such as Cirrus Logic later offered similar ICs.

Other firms offered video processors (Takahashi, 1999 and controllers for modems (Lineback,

1987), Ethernet local area networks (Hindin, 1982) and hard disks (McLeod, 1987). Similar

things have occurred in telecommunication systems where firms such as Broadcom provides

ASSPs for Ethernet LANs, cable modems, ADSL trans-receivers, and digital set top boxes in

cable systems and Marvel Technology provides them for LANs.

In summary, similar to the other standard modules, the emergence of ASSPs as a standard

module changed the physical architecture of many electronic systems, reduced the transaction

costs associated with different firms doing the design of semiconductors and electronic

22

systems, further reduced the importance of capabilities in system design for semiconductor

suppliers, and thus changed the industry architecture for semiconductors and electronic

systems (See Figure 1) and facilitated the entry of de novo startups in the semiconductor

industry. As shown in Table 3, 14 of the 18 ASSP suppliers in the top ranked firms for 1983/4,

1995, and 2005 were de novo startups. Furthermore, like ASICs, the emergence of vertical

disintegration between design and manufacturing also facilitated the success of de novo

entrepreneurial startups. For the 1995 database (ICE, 1996), 28 of the 59 de novo suppliers of

standard modules (See Table 3) are classified as suppliers of ASSPs of which 21 of the 28

firms were also design houses.

5. Discussion

This is the first paper to empirically analyze the relationship between the emergence of

vertical disintegration and entrepreneurial opportunities. Although other studies of vertical

disintegration imply that vertical disintegration has led to the emergence of entrepreneurial

opportunities, the specific connection has not been empirically examined and recognized

partly because this literature primarily emphasizes the impact of vertical disintegration on

incumbents. Furthermore, the entrepreneurial literature ignores the relationship between the

emergence of vertical disintegration and entrepreneurial opportunities and the technology

management literatures analysis of the semiconductor industry focuses solely on capabilities

(Malerba, 1985; Wilson, Ashton, and Egan, 1980; Utterback, 1994; Langlois and Steinmueller,

1999).

This paper analyzed the emergence of two forms of vertical disintegration and how

reductions in the transaction associated with different firms doing different activities reduced

the importance of integrative capabilities and gradually led to changes in industry architecture

First, the emergence of so-called standard semiconductor modules such as logic chips,

microprocessors, memory, ASICs, and ASSPs, which included open interface standards,

23

gradually changed the physical architecture of electronic systems and the industry

architecture of these electronic system industries. In particular, they reduced the transaction

costs associated with different firms designing semiconductors and electronic systems, and

reduced the importance of capabilities in system design for semiconductor suppliers. Second,

the separation between design and manufacturing represents changes in the architecture for

the semiconductor industry. It involved reductions in both the transaction costs associated

with different firms doing the design and manufacture of semiconductors and the importance

of capabilities for integrating design and manufacturing.

These changes in industry architecture occurred over a long period of time and in multiple

bottom-up processes in which few participants may have been looking at the entire

architecture for the electronic systems and semiconductor industries as these changes were

occurring. With respect to standard modules, rather than a top-down process in which system

firms defined the modules and then semiconductor firms developed them, it was a bottom-up

process in which system firms only adopted these standard semiconductor modules after the

modules had emerged and as further improvements were made to them. This competition

involved not just improving the performance of the standard modules but also reducing the

transaction costs associated with integrating them into a system design. Semiconductor firms

promoted standard interfaces, some of which were open and others proprietary, through

software and other design, which reduced the transaction costs associated with integrating

standard modules into a system design and thus the transaction costs associated with different

firms designing the semiconductors and the electronic systems. In turn this reduced the

importance of electronic system design capabilities for the suppliers of semiconductor

suppliers and thus enabled de novo entrepreneurial startups to become suppliers of these

standard semiconductor modules.

Focusing on the second set of changes in industry architecture, which concerns the

vertical disintegration between design and manufacturing, a similar argument can be made for

24

these changes. The gradual emergence of so-called dimensionless and scalable design rules

reduced the transaction costs associated with different firms doing the design and

manufacturing of ASICs, ASSPs, and other ICs. These rules emerged in a bottom-up process

in which engineers were solving micro-level problems associated with updating designs for

smaller feature sizes (Baldwin and Clark, 2000; Murphy et al, 2000; Critchlow, 1999; Macher

et al, 2002). As these problems were solved other engineers developed standard CAD tools

and a variety of Internet-based tools that further reduced the transaction costs associated with

different firms doing the design and manufacturing of ICs (Walker, 1992; Macher et al, 2005).

Reductions in the transaction costs associated with different firms doing the design and

manufacture of semiconductors also reduced the importance of manufacturing capabilities for

semiconductor suppliers and thus the large entry barriers that had previously existed for new

entrants. The high cost of semiconductor manufacturing facilities had been a high entry

barrier for prospective suppliers for many years where this entry barrier has continually

grown as the number of transistors on a chip and thus the cost of these manufacturing

facilities has increased. Reductions in the transactions costs associated with different firms

doing design and manufacturing have enabled firms to enter as design houses that do not

have any manufacturing facilities.

The impact of these falling transaction costs (and the resulting vertical disintegration) on

entrepreneurial opportunities was analyzed by showing how de novo entrepreneurial startups

were more likely to be design houses or foundries than to be integrated (both design and

manufacturing) suppliers of semiconductors and to be suppliers of standard modules than

non-standard semiconductors, after the vertical disintegration and thus the new form of

industry architecture became possible. Similarly, de alio firms were more likely to be

integrated suppliers than design house or foundries and to be suppliers of non-standard than

standard modules, even after the vertical disintegration and thus the new form of industry

architecture emerged. Support was found for six hypotheses concerning the greater

25

representation of de novo firms among suppliers of standard modules and among design

houses and foundries and of de alio firms among suppliers of non-standard semiconductors

and among integrated producers.

Generally speaking, as the sales of these standard modules grew (See Table 2) and as the

separation between design and manufacturing became possible, the number of de novo firms

in the top ranked suppliers and in larger databases of firms dramatically increased. The

number of de novo firms among the top 12 suppliers grew from 1 in 1995 to 2 in 1965, 7 in

1983/4 and 9 in 1995 and 2005, among the top 35 suppliers it grew from 18 in 1983/4 to 24

in 1995 and 2005, and among a larger database of firms grew from 31% during the early

years of the industry to 82% in 1995. Without the increase in sales of standard modules such

as logic chips, memory, and microprocessors in the 1970s and 1990s, it is unlikely that the

number of de novo firms in the top 15 U.S. suppliers would have reached 7 by 1983/4.

Without increases in the sales of these and other standard modules such as ASSPs and the

emergence of design houses as a viable option, it is unlikely that the number of de novo firms

in the top 35 U.S. suppliers would have reached 24 by 1995 and the percentage of them in the

1995 database of firms would have reached 82%.

The fact that recently founded de novo firms (after 1980) were more represented in the

1995 database than less recently established ones (before 1981) is consistent with the notion

that the industry architecture continues to evolve. The emergence of new forms of standard

modules such as ASSPs is one example of this evolution while changes in specific electronic

systems industries provide other examples of this continued evolution. Examples from the

PC industry were briefly summarized in the sub-section on ASSPS and other electronic

systems industries have probably undergone similarly large changes in industry architecture.

This is a good area for future research on capabilities, transaction costs, and industry

architecture.

This papers results have important implications for entrepreneurs. While the literature

26

on entrepreneurship focuses on software (Audretsch, 1991) and industries with rapid growth,

low capital intensity, small scale, and low concentration (Bygrave and Zacharakis, 2003;

Shane, 2004; Baron and Shane 2005) and the literature on technological management and

innovation focuses on capabilities and dominant designs (Utterback, 1994; Suarez and

Utterback, 1995), this papers results suggests that entrepreneurs should focus on industry

architecture and in particular on how vertical disintegration may emerge in an architecture.

This requires entrepreneurs to consider how transaction costs are falling or will fall and the

impact these falling transaction costs will have on firm entry and on the importance of

integrative capabilities.

Future research should attempt to understand how de novo entrepreneurial startups have

adapted to these changes better than have de alio firms. In the semiconductor industry, many

de alio systems firms probably found it hard to abandon manufacturing and to focus just on

design and in particular the design of standard semiconductor modules. One reason they may

have found it difficult to focus just on standard semiconductor modules is that many

semiconductor subsidiaries of system firms (which are de alio firms) were probably

encouraged to focus on the needs of their internal customers (i.e., the systems business) and

this may have made it difficult for them to identify and develop standard modules that would

appeal to a broad number of external customers. De novo firms were not constrained by

internal customers because they were probably selling to a broad range of customers.

On the other hand, the greater representation of recently formed than less recently formed

de novo firms in the 1995 database of U.S. semiconductor suppliers suggests that even de

novo firms have trouble adapting to changes in industry architecture. Was this because the

firms did not notice the changes in industry architecture or because they noticed them but

were unable to adapt to them? If it is the latter, why was it difficult to adapt? What is known

is that these changes emerged slowly in the form of both standard modules and a separation

between design and manufacturing and thus there was ample time to notice and adapt to the

27

changes. For standard modules, they started in niches and diffused slowly and many de novo

firms were established long after the standard modules first appeared. For example, more

than two-thirds of the suppliers of processors and memories in the 1995 database (ICE, 1996)

were established after 1980 in spite of the fact that processors and memories first appeared in

the early 1970s. More research is needed on this issue and why some de novo firms were

more successful than others.

6. Conclusions

This is the first paper to empirically analyze the relationship between the emergence of

vertical disintegration and entrepreneurial opportunities, where this paper uses the concept of

industry architecture to analyze the emergence of vertical disintegration. Changes in two

forms of industry architecture emerged through bottom-up processes that involved

interactions between reductions in transaction costs and changes in capabilities. De novo

entrepreneurial startups adapted to these changes in industry architecture better than did the

incumbents. This enabled the number of entrepreneurial startups among U.S. semiconductor

suppliers to dramatically increase over the life of the industry and these changes are still

occurring and providing new opportunities for startups.

28

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Table 1. Percentage of Firms that are De Novo Ones for Various Databases/Lists Databases/Lists 1955 1965 1983/84 1995 2005 Tiltons (1955) and ICEs (1995) list of firms

31.3% 82%

Top 12 8.3% 16.6% 50% 58% 58% Top 35 51% 69% 69%

Table 2. Growing Percentage of Global Semiconductor Sales that are Represented by Standard Modules

Standard Modules Year Logic Memory Processors ASICs ASSPs

Other Semiconductors

1966 100% 1971 29% 5% 66% 1980 20% 29% 10%

35

Table 3. Ratio of De Novo to the Total Number of Firms* in the Top Ranked U.S. Semiconductor Suppliers

Standard Modules vs. Non-Standard Semiconductors

Design Houses, Foundries, and Integrated Producers

Year

Standard Modules

Non-Standard Semi-conductors

Total Number of Firms

Design Houses

Foundries Integrated Producers

Total Number of Firms

1955 1/12 1/12 1/12 1/12 1965 2/14 2/14 2/14 2/14 1983/4 9/11 9/24 18/35 18/24 18/35 1995 15/18 9/17 24/35 5/5 19/30 24/35 2005 16/19 8/16 24/35 10/12 14/23 24/35 For all years

40/48 29/83 69/131 15/18 0/0 54/114 69/131

*Includes both de novo and de alio firms

Table 4. Number of De Novo and De Alio Firms for 125 Firms in 1995 (ICE, 1996) Standard Modules vs. Non-Standard Semiconductors

Design Houses, Foundries, and Integrated Producers

Year

Standard Modules

Non- Standard Semi-conductors

Total Number of Firms

Design Houses

Foundries Integrated Producers

Total Number of Firms

De Novo

59 40 99 58 3 41 102

De Alio 5 17 22 3 1 19 23 Total 64 57 121 61 4 60 125 Note: Foundries were not classified by modules and thus the total number of firms is different for columns 4 and 8.

36

Table 5. Number of De Novo Firms in 1995 Database (ICE, 1996) for Different Classifications and Founding Dates

Design Houses vs. Integrated Producers* Founding Dates

Standard Modules vs. Non-Standard Semiconductors

Design Houses Integrated Producers

Total

Standard Modules 3 10 13 Non-Standard Semiconductors

4 13 17 1955 - 1980

Total 7 23 30 Standard Modules 42 4 46 Non-Standard Semiconductors

9 14 23 1981 - 1995

Total 51 18 69 Grand Total (all years) 58 41 99 * Foundries are excluded from the analysis due to the small number of them

Table 6. Comparison of Custom and Semi-Custom Design Methods

Full Custom Standard Cell Gate Array PLD Prototype Cost Highest

(>$50,000) High Medium Lowest

($1000) Prototype Time

Highest (>8 weeks)

High Medium Lowest (minutes)

Variable Cost Lowest Lower Medium Highest Complexity, Performance

Highest Higher Medium Lowest

Market (2000) >$10 Billion $9.5 Billion $2.7 Billion $5.4 Billion

Source: Thomke, 2003; Abbreviations: PLD (Programmable Logic Devices)

37

Electronic

System and

Semi-

conductor

Design

and

Production

Figure 1. General Evolution of Industry Architecture for Electronic Systems and Semiconductor Industries

System design(and production)

using standardsemiconductormodules and other components

1950s, 1960s From 1970s From 1980s From 1990s

Design and fabricationof standardsemiconductormodules(logic, memory,processors)

Equipmentdesign andproduction

System designusing standardsemiconductormodules and other components

Contract

Manufacturing

Design of standardsemiconductormodules (logic,memory, micro-processors, ASIC)

Foundry

Equipment design and production

System designusing standardsemiconductormodules, IP,and othercomponents

Contract

Manufacturing

Design of standardsemiconductormodules (logic,memory,microprocessors,

ASIC, ASSPs)

IP designs

Foundry

Equipment design and production

38

1. Definition of standard cells

2. Design tools

1. Design of transistor array2. Design tools

1. Design of transistor array

2. Designtools

Connecttransistors on

IC chips

Design metal mask that connects transistors

Choice of cells and thusmasks for most

layers

Foundry/Fabrication

StandardCells

GateArrays

Program-mableLogic Devices

Type of Standard Module Customization of StandardASIC offered by ASIC Supplier Modules by System Firms

Figure 2. New Industry Architecture for ASICs

System Firms