EXPERIMENT 13: DIGITAL LOGIC CIRCUITS · PDF fileEXPERIMENT 13: DIGITAL LOGIC CIRCUITS ... All of the integrated circuits ... Grey connectors indicate inputs. 74LS TTL inputs have

EXPERIMENT 13: DIGITAL LOGIC CIRCUITS

The purpose of this experiment is to gain some experience in the use of digital logic circuits.These circuits are used extensively in computers and all types of electronic instrumentation,including physics experiments.

All of the integrated circuits (ICs) we will use are members of the Transistor-TransistorLogic (TTL) family and its improved variants. The circuits are a mixture of chips from the74LS00 series (“Low-power Schottky,” introduced 1976) and 74HCT00 series (“High-speedCMOS, TTL compatible,” introduced 1982), and are in the form of 14-pin dual-inlineepoxy packages (DIPs).

Background on 7400-Series Digital Logic

1. 7400-series TTL chips operate from a single DC power supply of VCC = +5 volts±5%(+5 V ± 10% for 74HCT). They can be destroyed if the supply voltage is raisedabove above +7.0 V or made negative even briefly (below −0.5 V for 74HCT). TTLlogic levels for 7400 series ICs. Here are logic output and input levels:

+4.75 V: Supply voltage VCC ; also max. allowed input voltage.

+2.40 V: VOH , min. output voltage for logical one @ 0.4 mA.

+2.00 V: VIH , min. input voltage for logical one @ 0.04 mA max. IIN .

+1.30 V: VS, threshold voltage (typical value – varies).

+0.80 V: VIL, max. input voltage for logical zero @ -1.6 mA max. ISINK .

+0.40 V: VOL, max. output voltage for logical zero @ -16 mA.

0.00 V: Ground; also min. allowed input voltage.

2. The delay in passing a signal through one NAND gate, called the propagation delay,is typically about 10 ns for 74LS and 74HCT TTL logic.

3. Unless you are not using an entire gate or section of a TTL logic chip, all of itsunused inputs must be connected to low or high.∗ (Compare with a CMOS logicchip, which must have all its inputs connected to something, or the chip mightdestroy itself!)

4. 7400 series inputs source a maximum of 1.6 mA if held low or sink a maximum 0f40 µA if held high; the outputs can sink 16 mA while maintaining their guaranteedlow output voltage, and supply 0.4 mA at their guaranteed high output voltage.This allows up to ten inputs to be connected to one output, for a “fanout” of ten.

∗This is not strictly true; unconnected TTL inputs will float to logical high, and a circuit designedwith floating inputs might appear to work, but such designs will not operate reliably. For more on why,see Section 9.06 of Horowitz and Hill, The Art of Electronics second edition, where they describe leavingdigital inputs unconnected as “foolish and dangerous.”

logic circuits 3 December 2010

5. The 7400 (“commercial”) series of TTL ICs have an operating case temperature rangeof 0C to +70C; 54xx devices are “military grade”, with an operating temperaturerange of −55C to +125C. Many commercial CMOS logic series have a largertemperature range than the normal “commercial” rating, but you need to checkthe individual manufacturer’s data sheet. Some devices are rated for an “industrial”temperature range of −40C to +85C. (Note that even this may be inadequate forsome “under-the-hood” automotive applications.)

Apparatus

All of the digital circuits needed for the next two laboratories have been incorporated intoprewired “logic boards.” The integrated circuits are mounted in DIP sockets inside thechassis of the logic board, with the inputs and outputs wired to external connectors. The+4.75 volt power supply is also located inside the chassis. The ground and DC power leadsare permanently wired to the DIP sockets. The ground wire is large (22 gauge) to reduceits inductance and noise. The DC power line is bypassed to ground at several points bylow-inductance disc ceramic capacitors. This reduces the spikes in the supply voltagecaused by the rapid switching of currents in the ICs.

Each logic board contains the following circuits:

16 2-input NAND gates

3 3-input NAND gates

10 indicator LEDs

4 push-button switches

8 JK flip-flops

1 4-bit adder

1 UART

4 toggle switches

(note: NOR gates with 2-8 inputs are readily available. You get NAND gates only as anexercise in DeMorgan’s theorem.)

Please note the following information about our logic boards:

1. Grey connectors indicate inputs. 74LS TTL inputs have a very non-linear impedance(2 kΩ near 0 V and 20 kΩ near +4 V) and may be connected to any voltage between0 and +4.75 V. 74HCT inputs are CMOS, and draw extremely small currents; theymay be connected to voltages up to 1.5 V above VCC or below ground withouttrouble.

2. Green connectors indicate outputs. To prevent damage by accidental shorting, a47 Ω resistor has been placed in series with each output. Each output can driveseveral inputs to logical one or zero; the number of inputs you can connect oneoutput to is called the fanout of a logic circuit. Typical fanouts for modern TTLICs are around 10; the use of protection resistors on our board limits its fanout to 4.

2


3. Light emitting diodes (LEDs) driven by internal buffer circuits can be used to indicatethe digital voltage level at various points in the circuit: LED on indicates logicalone, while LED off indicates logical zero.

4. Push-button and toggle switches can be used to provide logical one or logical zeroinputs for other circuits on the board.

5. Pull-up resistors inside the board connect any floating (otherwise unconnected)inputs to high (logical one). (This means you don’t have to worry about connectingfloating inputs.)

Laboratory Exercises

Perform the exercises outlined below. As you go through the individual operations, itshould become apparent how simple digital circuits can be combined to perform morecomplex operations.

Do not introduce any external voltages into the logic board.

1. Experimentally verify the truth table for a 3-input NAND gate.

2. Use 2-input NAND gates to construct circuits that perform the following logicalfunctions. In each case, draw the circuit diagram and experimentally verify the truthtable.

(a) 2-input AND gate: A AND B = A ·B.

(b) 2-input OR gate: A OR B = A + B.

(c) 2-input NOR gate: A NOR B = A + B.

(d) 2-input XOR gate: A XOR B = A⊕B.

3. Use NAND gates to construct circuits that perform the following functions. In eachcase, try to minimize the total number of gates, using 3-input NANDs whereverpossible. Draw your circuits and write out at least a portion of the truth table (atleast 8 states for each circuit; you can also use “Don’t Care” states to simplify thetable).

(a) (A ·B) + C

(b) ((A ·B) + C) ·D

(c) (A ·B) + (C ·D)

(d) (A ·B · C) + D + E.

4. A comparator is a circuit that compares the values of two numbers A and B andoutputs a one if A = B or a zero if A 6= B. Consider a 2-bit comparator; such acircuit must have 4 inputs, one for each bit of each number. Let A1 and A0 be themost and least significant bit of A, respectively, and similarly for B1 and B0.

(a) Write down a logical expression for C in terms of A0, A1, B0, and B1. (If youget stuck, it might help to write out a truth table.)

3


Inputs OutputsA0 B0 C0 S0

0 0 0 00 1 0 11 0 0 11 1 1 0

Table 1: Truth table for a half adder.

HAA0

B0

C0

S0

Figure 1: A block schematic symbol for ahalf adder.

(b) Design a circuit that uses only 2- and 3-input NAND gates to perform a 2-bitcomparison. Draw its schematic in your lab notebook.

(c) Build the circuit you designed, and verify that it does what you designed it to do.

(Hint: The XOR circuit from part 2d is pretty close to a 1-bit comparator – comparethe truth tables! You will need two such circuits, one for the first bit and anotherfor the second bit.)

5. A basic circuit for adding two bits, called a half adder, has the truth table shown in Ta-ble 1. A half adder will add bits A0 and B0 to produce their sum S0 and a carry bit C0.

(a) Write down logical expressions for S0 and C0 in terms of A0 and B0.

(b) Design a half adder circuit using only 2- and 3-input NAND gates.

(c) Build your half adder design, and verify that it produces the truth table shownin Table 1.

6. The circuit shown in Figure 2 is referred to as a full adder. A chain of N full adderscan add two N -bit numbers A and B one bit at a time, starting from the leastsignificant digit, giving their N -bit sum.

In each full addition step it combines three inputs,

• An, the nth bit from A

• Bn, the nth bit from B

• Cn−1, the carry bit from the previous step

and generates two outputs,

• Sn, the nth bit of the sum of A and B

• Cn, a carry bit for the next step.

The full adder is an extremely important and useful circuit found in every digitalcalculator and computer.

(a) What should you do with the carry input to the LSB of an N-bit adder?

4


An

An

An

Bn

Bn

Bn

Cn−1

Cn−1

Cn−1

Cn

Sn“all three”

“at least two”

“at least one”“just one”

Figure 2: A full adder built with NAND gates. Labels describe the functions of blocks.

FA FA FA FA

A0B0A1B1A2B2A3B3

S0S1S2S3

Cin

Cout

C0C1C2C3

Figure 3: A block diagram of a 4-bit adder built from full adders.

(b) For the last addition in an N -bit sum, the final carry bit CN−1 is also calledthe overflow bit. Why?

(c) Write down the truth table for a full adder. You may reference Figure 2, oryou can start from the functional definition of a full adder.

7. The 4-bit adder on the logic board is a single chip (a 74LS283 IC) that performsthe function of four full-adder circuits like the one in Figure 2. A schematic diagramof four full adders connected to form a single 4-bit adder with carry is shown inFigure 3. Notice that the carry input and the carry output allow you to connect Nof these chips together to obtain a 4N -bit adder.

5


Use the 4-bit adder to add the following pairs of decimal numbers:

(a) 6 + 7.

(b) 13 + 5.

(c) 11 + 14.

Next, try using the adder to add signed numbers. Use two’s complement form fornegative numbers [(−3) = 11012], which will restrict our signed adder to the range−8 to +7 (we are using 4-bit words, so we can only represent 16 distinct numbers).

Add the following pairs of decimal numbers:

(d) (−3) + 5.

(e) 3 + (−5).

(f) (−2) + (−3).

Observe what happens if you try to use just the most significant bit to indicatethe sign [(−3) = 10112], called sign-and-magnitude representation. Why is two’scomplement the preferred representation for negative numbers?

8. (Optional.) Design a circuit which returns the two’s complement negation of itsinput, a 4-bit number. You may use all of the circuits available on the logic board.If you feel like it, build and test this circuit.

9. (Optional.) A multiplexer is a very useful circuit which has two sets of inputs: addresslines A and data lines D, along with a single output Q. The address lines choosewhich data line is copied to the output. The number d of data lines is at most 2a.

(a) Write down the truth table for a 2-input multiplexer with address line A anddata lines D0 and D1: Q = D1 if A is high or Q = D0 if A is low.

(b) Design, build, and test a 2-input multiplexer circuit.

(c) Design, build, and test a 4-input multiplexer circuit.

10. (Optional.) Using the oscilloscope’s single-shot trigger mode, measure the propa-gation delay of a NAND gate.

11. (Optional.) Make a ring oscillator with 7 NAND gates connected in series as inverters.Measure the frequency with your oscilloscope and calculate the propagation delayper gate from this.

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SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

schematic

’00

GND

Y

130 Ω

VCC

4 kΩ

A

1.6 kΩ

1 kΩ

B

VCC

Resistor values shown are nominal.

Y

GND

3 kΩ

4 kΩ

120 Ω8 kΩ20 kΩ

1.5 kΩ

12 kΩ

A

B

2.8 kΩ 900 Ω

B

A

500 Ω 250 Ω

3.5 kΩ

’LS00 ’S00

VCC

Y

GND

50 Ω


4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted) †

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage: ’00, ’S00 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

’LS00 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS package 95°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.2. The package termal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN5400 SN7400UNIT

MIN NOM MAX MIN NOM MAXUNIT

VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 V

IOH High-level output current −0.4 −0.4 mA

IOL Low-level output current 16 16 mA

TA Operating free-air temperature −55 125 0 70 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)

PARAMETER TEST CONDITIONS‡SN5400 SN7400

UNITPARAMETER TEST CONDITIONS‡MIN TYP§ MAX MIN TYP§ MAX

UNIT

VIK VCC = MIN, II = −12 mA −1.5 −1.5 V

VOH VCC = MIN, VIL = 0.8 V, IOH = −0.4 mA 2.4 3.4 2.4 3.4 V

VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V

II VCC = MAX, VI = 5.5 V 1 1 mA

IIH VCC = MAX, VI = 2.4 V 40 40 µA

IIL VCC = MAX, VI = 0.4 V −1.6 −1.6 mA

IOS¶ VCC = MAX −20 −55 −18 −55 mA

ICCH VCC = MAX, VI = 0 V 4 8 4 8 mA

ICCL VCC = MAX, VI = 4.5 V 12 22 12 22 mA

‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.§ All typical values are at VCC = 5 V, TA = 25°C.¶ Not more than one output should be shorted at a time.



switching characteristics, V CC = 5 V, TA = 25°C (see Figure 1)

PARAMETERFROM

(INPUT)TO

(OUTPUT)TEST CONDITIONS

SN5400 SN7400 UNITPARAMETER

(INPUT) (OUTPUT)TEST CONDITIONS

MIN TYP MAX

UNIT(INPUT) (OUTPUT)

MIN TYP MAX

tPLHA or B Y RL = 400 Ω, CL = 15 pF

11 22ns

tPHLA or B Y RL = 400 Ω, CL = 15 pF

7 15ns


SN54LS00 SN74LS00UNIT





IOH High-level output current −0.4 −0.4 mA





PARAMETER TEST CONDITIONS†SN54LS00 SN74LS00

UNITPARAMETER TEST CONDITIONS†MIN TYP‡ MAX MIN TYP‡ MAX

UNIT

VIK VCC = MIN, II = −18 mA −1.5 −1.5 V

VOH VCC = MIN, VIL = MAX, IOH = −0.4 mA 2.5 3.4 2.7 3.4 V

VOL VCC = MIN, VIH = 2 VIOL = 4 mA 0.25 0.4 0.25 0.4

VVOL VCC = MIN, VIH = 2 VIOL = 8mA 0.35 0.5

V

II VCC = MAX, VI = 7 V 0.1 0.1 mA

IIH VCC = MAX, VI = 2.7V 20 20 µA

IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA

IOS§ VCC = MAX −20 −100 −20 −100 mA

ICCH VCC = MAX, VI = 0 V 0.8 1.6 0.8 1.6 mA

ICCL VCC = MAX, VI = 4.5 V 2.4 4.4 2.4 4.4 mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time.


PARAMETERFROM

(INPUT)TO


SN54LS00 SN74LS00 UNITPARAMETER


MIN TYP MAX


MIN TYP MAX

tPLHA or B Y RL = 2 kΩ, CL = 15 pF

9 15ns

tPHLA or B Y RL = 2 kΩ, CL = 15 pF

10 15ns


6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265


SN54S00 SN74S00UNIT





IOH High-level output current −1 −1 mA





PARAMETER TEST CONDITIONS†SN54S00 SN74S00

UNITPARAMETER TEST CONDITIONS†MIN TYP‡ MAX MIN TYP‡ MAX

UNIT

VIK VCC = MIN, II = −18 mA −1.2 −1.2 V

VOH VCC = MIN, VIL = 0.8 V, IOH = −1 mA 2.5 3.4 2.7 3.4 V

VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V

II VCC = MAX, VI = 5.5 V 1 1 mA

IIH VCC = MAX, VI = 2.7 V 50 50 µA

IIL VCC = MAX, VI = 0.5V −2 −2 mA

IOS§ VCC = MAX −40 −100 −40 −100 mA

ICCH VCC = MAX, VI = 0 V 10 16 10 16 mA

ICCL VCC = MAX, VI = 4.5 V 20 36 20 36 mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time.


PARAMETERFROM

(INPUT)TO


SN54S00SN74S00 UNITPARAMETER


MIN TYP MAX


MIN TYP MAX


3 4.5ns


3 5ns


4.5ns


5ns



PARAMETER MEASUREMENT INFORMATIONSERIES 54/74 DEVICES

tPHL tPLH

tPLH tPHL

LOAD CIRCUITFOR 3-STATE OUTPUTS

High-LevelPulse

Low-LevelPulse

VOLTAGE WAVEFORMSPULSE DURATIONS

Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

VCC

RL

Test Point

From OutputUnder Test

CL(see Note A)

LOAD CIRCUITFOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUITFOR 2-STATE TOTEM-POLE OUTPUTS

(see Note B)

VCC

RLFrom Output

Under Test

CL(see Note A)

TestPoint

(see Note B )

VCCRL

From OutputUnder Test

CL(see Note A)

TestPoint

1 kΩ

NOTES: A. CL includes probe and jig capacitance.B. All diodes are 1N3064 or equivalent.C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series

54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.F. The outputs are measured one at a time with one input transition per measurement.

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)

Waveform 1(see Notes C

and D)

Waveform 2(see Notes C

and D)≈1.5 V

VOH − 0.5 V

VOL + 0.5 V

≈1.5 V

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

tw

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

VOH

VOL

Figure 1. Load Circuits and Voltage Waveforms

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EXPERIMENT 13: DIGITAL LOGIC CIRCUITS · PDF fileEXPERIMENT 13: DIGITAL LOGIC CIRCUITS ... All of the integrated circuits ... Grey connectors indicate inputs. 74LS TTL inputs have