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EXPLAINING PRINCIPLES REGISTER
APPLYING BASICS DIGITAL ENGINEERINGBy Sri Wahyuni
Teknologi dan Rekayasa
DIRECTION
Participant be able to:
1. Explain the functions of the register2. Explain the functions of clock 3. Explain the functions of Flip-flop 4. Explain the functions and Counter register
CLOCK
Teknologi dan Rekayasa
RA
+VCC
C
U7
555
1
2
3
4
5
6
7
8
GND
TRIG
O
R
CTL
TH
DVCC
Gambar 1
Vout0.01uF
RB
Including the series of clock with Astabil Multivibrator IC 555
HOW IT WORKS SERIES CLOCK 1. C at the time charged exceeds the rising threshold
voltage + (2 / 3) Vcc. 2. Capacitor C cleared through Rb therefore blanking time
convention can be determined with the formula T = Rb x C.
3. Voltage when C is a bit of down + (Vcc / 3) then the output becomes high.
4. Cycle work formulated: W = 0,693 (Rb + RA). C T = 0693. Rb. C T = W + t F = 1 / T
Where: W = width of balance; T = time period T = seconds; F = Hert
Teknologi dan Rekayasa
Teknologi dan Rekayasa
Operating system on the balance going digital clock will transition from 0 to 1 or from 1 to 0.
Transition 0-to-1: the rise (rising edge); Transition 1-to-0: the falling (falling edge)
FLIP-FLOP
A series of logic with the output of the two opposite each other.
Teknologi dan Rekayasa
FF two working conditions: (1) Q = 0, Q’=1 : (2) Q = 1, Q’ = 0 .
FLIP-FLOP TYPES:
1. RS FLIP-FLOP
Teknologi dan Rekayasa
S
R
Q
Q
RS-FF arranger by NAND gate
S B Q Q Description0 0 1 1 Restricted0 1 1 0 Set1 1 1 0 Stabil I1 0 0 1 Reset1 1 0 1 Stabil II0 0 1 1 Restricted
1 1Qn
Qn
Memory condition
Truth Table:
2. CRS FLIP-FLOP
Teknologi dan Rekayasa
S
R
Ck
Q
Q
S
R
RS FF
S R Qn +1
0 0 Qn
0 1 0
1 0 1
1 1 Restricted
Truth Table:
3. D FLIP-FLOP
Teknologi dan Rekayasa
D
Ck
Q
Q
S
R
RS FF
D Qn+101
01
Truth Table:
4. T FLIP-FLOP
Teknologi dan Rekayasa
Ck
Q
Q
S
R
RS FF
T Q0 01 00 11 10 01 00 11 1
Tabel Kebenaran:
Truth Table:
5. J-K FLIP-FLOP
Teknologi dan Rekayasa
Q
Q
JK FF
Clear
J
Ck
K
J K Qn+1 Description
0 0 QnMemory
0 1 0 Reset
1 0 1 Set
1 1Qn
(strep)Togle
Truth Table:
REGISTER
Order to register the memory with 4-bit DFF:
Teknologi dan Rekayasa
4-bit memory register which consists of 4 pieces D FF. Input data is inserted in parallel to the terminals A, B, C,
and D.
In the input data will be transfer to balance the output of each clock is also in parallel.
Teknologi dan Rekayasa
REGISTER TYPES:
1. REGISTER SISO (Serial Input Serial Output)
Teknologi dan Rekayasa
Q3
FF3
1
2
3
4
5
J
CLK
K
Q
Q
Q4
FF4
1
2
3
4
5
J
CLK
K
Q
Q
Q1
FF1
1
2
3
4
5
J
CLK
K
Q
Q
Q2
FF2
1
2
3
4
5
J
CLK
K
Q
Q
Word in (SI)
Clock
Clock ke
Word in Q1 Q2 Q3 Q4
0 0 0 0 0 01 1 1 0 0 02 0 0 1 0 03 1 1 0 1 04 1 1 1 0 1
Truth Table: (Ex entrance 1101)
2. REGISTER SIPO (Serial Input Paralel Output)
Teknologi dan Rekayasa
C
Clock
A D
DFF4
2
1 3
CLK
D Q
DFF2
2
1 3
CLK
D Q
Data load
B
DFF1
2
1 3
CLK
D Q
DFF3
2
1 3
CLK
D Q
Read Out
Read Out Clock Input Q1 Q2 Q3 Q4 A B C D
0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 0 0 0 0
0 2 1 1 1 0 0 0 0 0 0
0 3 0 0 1 1 0 0 0 0 0
0 4 1 1 0 1 1 0 0 0 0
1 1 0 1 1 1 0 1 1
Truth Table:
3. REGISTER PIPO (Paralel Input dan Paralel Output)
Teknologi dan Rekayasa
Clock
RReset
QD
DFF2
2
1 3
CLK
D Q
DFF2
2
1 3
CLK
D Q
R
D2 D0D1
R
QC QB
D3
QA
R
DFF2
2
1 3
CLK
D Q
DFF2
2
1 3
CLK
D Q
ClockD1 D2 D3 D4
QD QC QB QA
01 1 0 1
0 0 0 0
11 1 0 1
1 1 0 1
21 0 0 1
1 0 0 1
30 0 0 1
0 0 0 1
Truth Table:
TABEL KEBENARAN:
4. REGISTER PISO (Paralel Input Serial Output)
Teknologi dan Rekayasa
SerialOut
B
DFF2
2
1 3
CLK
D Q
DFF2
2
1 3
CLK
D Q
Clock
C
DFF2
2
1 3
CLK
D Q
RR
A D
R
DFF2
2
1 3
CLK
D Q
Dataload
R
Data IC Preset Reset0 1 1 01 1 0 10 0 1 11 0 1 1
Truth Table:
COUNTER
There are 2 kinds of counter, namely:
1. Counter sync (syncronuous counters) or counter row.
2. Counter is not synchronized (asyncronuous counters), which is sometimes also called counter array (series counters) or counter ruga (rippIe counters).
Teknologi dan Rekayasa
COUNTER TYPES
1. Syncronuos Counter :
Counter forward sync that runs continuously (Free Running).
Counter synchronized forward that can stop yourself (Self Stopping).
Counter reverse sync.
Counter forward and reverse sync (Up-down Counter)
Teknologi dan Rekayasa
2. Asyncronuos Counter :
Asyncronuos forward counter continuously (Free Running)
Asyncronuos forward counter stopself (Self Stopping).
Asyncronuos back counter
Asyncronuos back and forward counter (Up-down
Counter).
Teknologi dan Rekayasa
EXEMPLARY COUNTER:
Teknologi dan Rekayasa
QD(MSB)
D
1
2
3
4
5
J
CLK
K
Q
Q
QB
B
1
2
3
4
5
J
CLK
K
Q
Q
QA(LSB)
A
1
2
3
4
5
J
CLK
K
Q
Q
QC
C
1
2
3
4
5
J
CLK
K
Q
Q
Clock
QA
QB
QC
QD
ClockQD QC QB QA
MSB LSBDesimal
0123456789
101112131415
0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1
0123456789
101112131415
1. Asyncronuos forward counter using the 4-JK FF:
Timing diagram
Truth Table:
2. Asyncronuos back counter
Teknologi dan Rekayasa
QB
B
1
2
3
4
5
J
CLK
K
Q
Q
QD(MSB)
D
1
2
3
4
5
J
CLK
K
Q
Q
Clock
QC
C
1
2
3
4
5
J
CLK
K
Q
Q
QD(MSB)
D
1
2
3
4
5
J
CLK
K
Q
Q
Clock
QA(LSB)
A
1
2
3
4
5
J
CLK
K
Q
Q
QA(LSB)
A
1
2
3
4
5
J
CLK
K
Q
Q
Atau
QC
C
1
2
3
4
5
J
CLK
K
Q
Q
QB
B
1
2
3
4
5
J
CLK
K
Q
Q
Clock QD QC QB QA Desimal0 1 1 1 1 151 1 1 1 0 142 1 1 0 1 133 1 1 0 0 124 1 0 1 1 115 1 0 1 0 106 1 0 0 1 97 1 0 0 0 88 0 1 1 1 79 0 1 1 0 6
10 0 1 0 1 511 0 1 0 0 412 0 0 1 1 313 0 0 1 0 214 0 0 0 1 115 0 0 0 0 016 1 1 1 1 15
ClockQA
QB
QC
QD
Timing diagram
Truth Table:
3. Asyncronuos back and forward counter :
Ring Counter
Teknologi dan Rekayasa
Clock
D
JKFFC
1
2
3
4
5
J
CLK
K
Q
Q
BA
JKFFC
1
2
3
4
5
J
CLK
K
Q
Q
C
JKFFC
1
2
3
4
5
J
CLK
K
Q
Q
JKFFC
1
2
3
4
5
J
CLK
K
Q
Q
Clock D C B A
012345
0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 1
Truth Table
Ring counter
Johnson Counter
Teknologi dan Rekayasa
Clock
D
JKFFC
1
2
3
4
5
J
CLK
K
Q
Q
BA
JKFFC
1
2
3
4
5
J
CLK
K
Q
Q
C
JKFFC
1
2
3
4
5
J
CLK
K
Q
Q
JKFFC
1
2
3
4
5
J
CLK
K
Q
Q
Johnson Counter
Clock D C B A
012345678
000011110
000111100
001111000
011110000
Truth Table
The End
Teknologi dan Rekayasa
