Extreme Makeover for EDA Industry

Extreme Makeover

for EDA Industry

Daniel D. GajskiCenter for Embedded Computer Systems

University of California, Irvine

www.cecs.uci.edu/~gajski

Copyright 2004 Daniel D. Gajski 2

Past, Present and Future

Specs

Algorithms

Capture &Simulate

Specs

Algorithms

Describe &Synthesize

ExecutableSpec

Algorithms

Specify, Explore& Refine

Architecture

Network

SW/HW

Logic

Physical

SW? SW?

Design

Logic

Physical

Design

Logic

Physical

Manufacturing Manufacturing Manufacturing

1960's 1980's 2000's

Functionality

Simulate Simulate

Describe

Algorithms

Connectivity

Protocols

Performance

Timing

System Gap


Simulation based methodology

case X is when X1=> . . . when X2=>

Finite state machine

Controller

3.415

2.715

--

--

Look-up table

Memory

Simuletable but not synthesizable or verifiable


Arithmetic Algebra

a*(b+c) = a*b + a*c

< objects, operations>

Arithmetic algebra allows creation of expressions and equations


Model Algebra

B1

B2 B3

B1

B2 B3

PE1 PE2

=

<objects, compositions>

Model algebra allows creation of models and model equivalences


Specify-Explore-Refine Methodology

System specificationmodel

Cycle accurateimplementation model

SER

Intermediate models

Design decisions

Model refinement

Replacement or re-composition


Refinement

Model A

Refinementtool

Transforms:t1t2 . . .tn

Model B

Componentlibrary

Designerdecisions

Each designer decision

Several transformations

Model refinement


Verification

Model A

Model B

Componentlibrary

Verifytool

ti

Refinementtool


Designerdecisions

Transformations

New model

Verify equivalence


Synthesis

Model A

Model B

Estimationtool

Synthesistool

Componentibrary

Refinementtool


Estimate metric

Evaluate options

Design decision


Simulation

Model A

RefinementTool

Transforms:T1T2…Tn

Model B

EstimationTool

SynthesisTool

ComponentLibrary

SimulationToolVerify

Tool

Ti


System Design Environment

Model A

Model B

Estimationtool

Synthesistool

Componentlibrary

Simulationtool

GUI Verifytool

ti

Refinementtool



Y-Chart

Behavior(Function)

Structure(Netlist)

Physical(Layout)

Logic

Circuit

Processor

System

F(...)

F(...)

F(...)

F(...)


Finite-State-Machine with Data

o1 o2

o1 o2

o3

o2 o3

o4

o1

o6o5

s3

s1 s2

FSM

a b

x y

b c

z

DFG1

DFG3 DFG2

a c d

x w z

(Processor-level behavioral model: FSM +DFG)


Processor Architecture

Bus1

Bus2

Bus3

Datapath

Controlinputs

Next-statelogic

orAddress

generator

Outputlogic

orProgrammemory

Stateregister

orPC

Controloutputs

Register

Selector

Register

Datapathoutputs

RFCache

ALU

Signalstatus

Controller

Latch

Datamemory

IR

SR

Controlsignals

(Processor-level structural model: RTL components)


Processor Semantics

Objects:- RTL Components • Alus • Multipliers • Registers • RF- Connections • Buses • Wires

Composition:- Netlist

Objects:- States- Transitions- Statements

Composition:- Statements • Sequential • Parallel- Transitions • Conditional • Unconditional

Processor


Processor Synthesis

Op1 Op2

Op3

Op1 Op2

S1 S2

S3

FSMD model

Allocation

Rescheduling

Variable binding Operation Binding

Bus Binding

FSM Synthesis

RTL Processor

D

Q

D

Q

D

Q

Controlinputs

Next-statelogic

orAddress

generator

Outputlogic

orProgrammemory

Stateregister

orPC

Controloutputs

Controlsignals

Bus1

Bus2

Selector

Register

Datapathoutputs

ALU

Bus3

Datapath

Signalstatus

Controller

Register Memory

RF

SR

IR

Latch

Datamemory

Op2 Op3

Op4

Op6

Op1

Op5

Processor


Program-State Machine

Proc3

Proc4

Proc5

Proc1

Proc2

(System-level behavioral model: UML + C)


System Architecture

MemoryIP comp.

Interface Interface

Memory

Interface

Processor

Interface

Custom HW

BUS

(System-level structural model: system components)


System (Transaction-Level) Semantics

Objects:- Behaviors- Channels

Composition:- Hierarchy- Order • Sequential • Parallel • Piped • States- Transitions • TI • TOC, TOS, ...- Synchronization

Objects:- Components • Proc • IP • Memories • IF- Connections • Buses • Wires

Composition:(same as in Behavior Model)

SystemObjects:- Behaviors- Channels

Composition:- Hierarchy- Order • Sequential • Parallel • Piped • States- Transitions • TI • TOC, TOS, ...- Synchronization


System Synthesis

PSM model

Proc

Proc

Proc

Proc

Proc

Memory

Memory

µProcessor

Interface

Comp.IP

Bus

Interface

Interface

Interface

Custom HW

System architecture

Profiling

Allocation IF Synthesis

Refinement

Behavior Binding Channel Binding

System

Scheduling


SCE2

Specification model

Architecture modelEstimation

Profiling

Profiling data

Design decisions

Communication model

Arch. synthesis

Arch. refinement

Comm. synthesis

Comm. refinement

DecisionUser Interface (DUI)

Estimation results

Design decisions

Estimation

CA synthesis

Estimation results

Design decisionsCA refinement

Implementation model

Capture

RTL Comp.RTOS

ValidationUser Interface (VUI)

Sys. CompIPs

BusesProtocols

Compile

Commercial Tools

EstimationEstimation results

Verify

Check

Simulate

Select

Schedule

Partition

Map

Insert

Assemble

Comm.Libraries


Experiment on GSM Vocoder design (10K lines of code)

Conclusion Productivity gain >2,000X for industrial strength designs Compare 9-12 months (manual refinement) vs. 50+4 minutes (user decisions +

automatic refinement) Enables extensive design exploration (60/day)

Some Results

Simulation Speed

1

10

100

1000

10000

100000

Spec Arch Comm Impl

No

rmal

ized

Tim

e

Code Size

0

5000

10000

15000

20000

Spec Arch Comm Impl

Nu

mb

er o

f L

ines

CommImpl

AutomatedUser / Refine

ManualModified

lines

SpecArch

ArchComm

3,275914

30 mins / <2 mins5~6 mons

5 mins/ <0.5 min

3~4 mons.

6,146

15 mins / <1 min

1~2 mons.

Refinement Effort

Total 50 mins / <4 mins9~12 mons10,355

Source: J. Peng, PHD Thesis


Some Results• Simulation Speed & Code size

Code Size

0

500

1000

1500

2000

2500

3000

3500

Spec Arch Comm Impl

Nu

mb

er

of

Lin

es

Simulation Speed

1

10

100

1000

10000

100000

1000000

Spec Arch Comm Impl

No

rmal

ized

Tim

e

CommImpl

AutomatedUser / Refine

ManualModified

lines

SpecArch

ArchComm

751

492

20 mins / <1 mins3~4 mons

3 mins/ <0.5 min

1~2 mons.

1,278

5 mins / <0.5 min

~1 mons.

Refinement Effort

Total 28 mins <2mins5~7 mons2,521

• Refinement Effort

• Compare 5-7months (manual refinement) vs. 28 minutes (user decisions) + 2 minutes (automatic refinement)

Source: J. Peng, PHD Thesis


Conclusions• Extreme makeover is necessary for a new paradigm, where

– SW = HW = SOC = Embedded Systems– Simulation based chaos is not acceptable– Design methodology is based on scientific principles

• Model algebra is enabling technology for– System design– System modeling and simulation– System verification– System synthesis

• Formalism introduces simplicity that allows– Automatic model generation (No need for languages)– Exploration and synthesis (Simplifies design algorithms)– Equivalence verification (Guarantees equivalence)

Documents

Extreme Makeover for EDA Industry