Fall Project ReportECE 506
AIM1. Implementing a multiple voltage domain and study of AOCV2.
Static Timing Analysis3. Clock Domain Crossing Analysis
Multiple Voltage domain systemIn-order to define a multi voltage
system a simple design with two modules one working at 1 V and
other at 2V is created. The pre characterized NAND and Inverters
will be used in this design. For this to happen the library file
path will be modified in the encounter.conf file to include the
library file with the new standard cells for 2V. The design must
have a level converter in-order to convert the output from the low
voltage domain to the high voltage domain.
Multi Voltage DesignPD1PD2PM11 V0 VPM21 V2 VControl signal is
PM_INSTHere in the above design the instance in PD2 works in the
Power domain with 2V and rest of the gates works in default power
domain which is 1V.In-order to enable the design to work in
different voltage domain we will have to create either Unified
Power Format (UPF) or Common Power Format ( CPF). Here I proceeded
with creating a CPF file. State retention cell must be defined,
when PD2 is off the state of the cell must be held. Isolation cell
may not be required since PD2 output is not supplied to any other
module as input
CPF file#define the designset_design top#setup logic structure
for all domainscreate_power_domain -name PD1
-defaultcreate_power_domain -name PD2 -instances {inst_A}\-shutoff
_condition {!PM_INST}
#define static behavior of power domains and specify the timing
constraints
create_nominal_condition -name high -voltage
2.0create_nominal_condition -name low -voltage 1.0
create_power_mode -name PM1 -domain_conditions{PD1@high
PD2@low}create_power_mode -name PM2 -domain_conditions{PD1@high
PD2@high}
#setup state retention, isolation
rulescreate_state_retension_rule -name sr -domain PD2\-restore_edge
{!PM_INST}#define level convertors
requiredcreate_level_shifter_rule -name lvl_conv -from {PD1} to {
PD2}
end_design
Verilog code for the design Below is a sample code for the
design. However cadence library is not having cells for level
shifter. Hence will have to create a new one and characterize it
entirelymodule PD1 (Y0, B, A, C, OM_INST); output Y0, OUT1; input
B, A, C; wire INT1,INT2; nand2cell G1(Y, B, INT); notcell G2(INT,
A); nand2cell G3(Y, INT, C); notcell G4 (INT2,Y); and2cell G5
(OUT1, INT2, PM_INST); and2cell G6 (Y0, INT2,
PM_INST);endmodule
module PD2 (Y1, Y2, H, J, I); output Y1, Y2; input I, H, J; wire
INT3; nand2cell G1(Y1, H, I); nand2cell G2(Y2, J, I);endmodule
module TOP(Y0, Y1, Y2, B, A, C, H, J, PM_INST); output Y0, Y1,
Y2; input B, A, C, H, J, PM_INST; wire I; PD1 P1(Y0, OUT1, A, B,
C); PD2 P2(Y1, Y2, H, J, I);
LSCELL LS1(I, OUT1);endmodule
In-order to implement this design the encounter.conf must be
modified to include the lib path of the modified .lib file with
standard cells.
LEF(Library Exchange Format) file understanding:This describes
the physical layout in ASCII format and it contains design rules
and information of cells. A LEF file has mainly Technology
sectionSiteMacrosTechnology: This is described through LAYER and
VIA statements. TYPE: routing, cut(contact),
masterslice(poly,active)width, pitch, spacing rulesDirection
(horizontal or vertical)resistance and capacitance per unit
square
Each layer is described with its propertiesex:LAYER
layernameTYPE: cutSPACING: min distance between cuts in the same or
different netsSAMENET SPACING : this can be used to override the
SPACING value mentioned aboveEND layername
Similarly Cut layer, Implant layer, Masterslice layer, routing
layer etc can be described.
MANUFACTURINGGRID value;This is used for the geometry alignment.
Cells are placed in location values which are multiples of grid
value
VIA definition : This is used to define the vias from one metal
to the otherEx:
VIA M2_M1_via DEFAULTLAYER metal1;RECT: give coordinates;LAYER
via1;RECT: give coordinates;LAYER metal2;RECT: give coordinates;END
M2_M1_via
VIARULE.. GENERATE:This is used in cases where we need to define
special wirings which is not otherwise defined.MACRO
definition:This definition describes the attributes of a cell.
location of input pins, output pins, VDD and GND.
OBS statement:Used to define the obstruction in layout
PIN statementDefines a PIN in the layout. Attributes are
Direction, USE, SHAPE etc.
All the above specifications are used for Design rule checks by
verification tools.
I have gone through the syntax of Layer definition, Via
definition, VIARULE GENERATE, SMAENET SPACING statement, SITE
definition, MACRO definition, MACRO Obstruction statement, PIN
Statement etc and the syntax to define all these.
Power grid creation and APR1. Import Design
Verilog file is selected to import the design. This generates a
generic floor plan in the screen. The customisation is done using
the specify Floorplan option2. Specify FloorplanThis option helps s
to define the Aspect ratio, Core utilization, Or else we can
specifically give the width and height. ALos Core margins can be
set Core to IO or core to Die options. The distances can be given
by specifying the values required in the core to left, core to
right core to top and core to bottom boxes.
The above shows the floorplan with Core to IO boundary with
offset 10 from left right top and bottom.3. Add ringPpower planning
is th enext step as per our decision either we can go for only
rings or rings and stripe so as to provide Vdd and Gnd connections
across the chip. which reduces wiring and rc parasitics. For this
the global nets Vdd and Gnd are selected and metel layer for the
same is specified along with the width of rings.
4. Add stripe
Adding stripe will create vdd and gnd connection across the chip
either vertically or horizontally. The spacing between each stripes
can be specified.
5. Special routingThis is used to route the Vdd and Gnd
connections for each row of Standard cells, After this Std cells
will be placed
6. PlacementAfter routing the Vdd and Gnd connections STD cells
are placed using the placement tab.
7. Routing
Nanoroute option in Encounter
Design after APRThen the global routing is done after the
completion of placement of cells this will connect the cells
together as per the netlist connections.RC extraction
RC extraction step in the EncounterAfter routing parasitic are
extracted from the routed layout. This extracts the RC component
values from the design which can be later used to get the proper
timing of the designTiming checkTiming can be verified using the
timing tab in the encounter. the option for using RC parasitic ca
be selected in order to get the proper Timing specification of the
system. This can be verified with the initial specs to check
everything is working as expected at designated speed.
Clock treeIf your system is clocked you can display the clock
tree created using the Clock tab and Display clock option.
Clock tree highlightedIn order to avoid the DRC violations I
have changed the pin positions using the PIN editor of cadence
encounter.
Pin edit option of Cadence EncounterAfter Pin editing the DRC
violations were removed from the design
APR after pin editing(and b bus on metal3 sum at metal
5)Checking for timing violations after the pin editing. Timing of
the design was again checked and it resulted in positive slack
which is not a timing violation.
Synthesized clock from UI and again ran timing check which
resulted in some change in the parameters
Clock tree synthesized in the design
Since there are no timing violation for 100MHz frequency was
increased to 10Ghz which created DRC as well as timing
violations.
Timing for 10Ghz
APR of 64 bit adder at 10GHzRearranged pins to resolve the DRC
issue.
After Pin editing
Timing after rearranging the pins
In order to see the path violation, frequency was increased to
10Ghz from 100MHz and APR is done. which produced many timing
violations. The way to solve them are using the debug timing option
of encounter. Which gives a histogram and net wise delay details.
Schematic view can also be found from this as below.
selecting an instance and the corresponding schematic view of
it
Adding buffer using the Interactive Eco option
After the buffer insertion step the refreshed schematic view
appears as above. Checking timing after this to check whether this
has solved the issue or not.
optDesign postCTSThis command optimizes the timing by fixing
DRV's, reclaiming area and then fixes setup violations
Challenges faced
While adding buffers in the clock path to reduce the violations,
the schematic view didn't show any buffers added to the net.
AOCVAs the size of the transistors shrink, the effect of
variation is increasing. Now we can see on chip variation and wafer
to wafer variations.
Scope of Variation:GlobalWhich means Die to die, wafer to wafer
this variation is consistent throughout the die.On-Chip This type
of variation is local to each die and the effect is increasing as
the process node decreases.
Types of Variation:Random Variation: This affects individual
transistors. This can occur due to the variation in the doping,
gate oxide thickness variation etc.Systematic Variation: This type
of variation affects the local transistors and nets similarly. This
variation increases with length. This occurs due to the variations
in thickness, lithography, CMP etc. This alters the characteristics
of transistors.
Variation causes the characteristics of the transistors and dies
to change. Thus it becomes important to consider the variation
during design phase especially below 90nm. Main variations
affecting delay are Channel length (Le) variation and Threshold
voltage variation(Vt). And as mentioned above these two parameters
have their own random and systematic variation components.
Derating factor:Scaling factor applied either to the entire chip
or to particular nets to account for variation. Generally derating
factors are provided by the foundry/vendor or derived through
measurements.
Different OCV methods for derating factors:Traditional OCV: In
this to account for the worst case and safely model for variation
the worst case is considered for finding the derating factor and
this derating factor is applied to all the clock paths or the data
paths. This approach is pessimistic since in a chip all the paths
does not require adjustment.Local OCV:Location Based: This
considers the placement into consideration. Derating factor depends
on the diagonal of the bounding box that encloses all instances on
data path or clock path.Level Based:Derating factor is a variable
depending on the logic levels on a data path or clock path. If a
path has more logic levels and another path has less logic levels
then different derating factors will be applied for these paths
OCV derating factor tables: This is a table which describes the
level and location effects. This table is generally provided by
library teams. These tables are used with SDF's(Standard Delay
file) to figure out the derating factor.
At one timing check one table is applied to either data path or
clock path. Combination will be MAX Hold, Max Setup, MIN Hold, MIN
Setup.MAX SDF contains the delays under worst case scenario hence
derating factors are less than 1 and MIN SDF will have derating
factors greater than one since it accounts for the best delay
conditions. Logic levels are generally from 0 to 32 (level based)
and Distances are taken from 0 to 16000um. Single mode vs.
DoubleSingle mode: Either a data path or clock path is considered
and derating factor is applied at a timing check(setup or
hold)Double mode: In each timing check 1 table is applied to data
path and another table is applied to clock path.In order to figure
out how to turn the AOCV option off I have analyzed majority of the
files and scripts used and some commands too in the rc.tcl,
encounter.tcl files. In order to make the analysis as Advanced On
chip verification the setAnalysisMode command of encounter must be
used along with its -aocv option.setAnalysisMode CommandThis
command is used in the encounter.tcl file. This command is used to
set the type of timing analysis to be performed on the design. The
syntax of this command is as below
setAnalysisMode[-help][-reset][-analysisType {single | bcwc |
onChipVariation}][-asyncChecks {async | noAsync |
asyncOnly}][-caseAnalysis {true | false}][-checkType {setup |
hold}][-clkNetsMarking {beforeConstProp |
afterConstProp}][-clkSrcPath {true | false}][-clockGatingCheck
{true | false}][-clockPropagation {sdcControl | forcedIdeal |
autoDetectClockTree}][-aocv {true | false}][-cppr {none | both |
setup | hold}][-enableMultipleDriveNet {true |
false}][-honorActiveLogicView {true | false}][-honorClockDomains
{true | false}][-log {true | false}][-propSlew {true |
false}][-sequentialConstProp {true | false}][-skew {true |
false}][-timeBorrowing {true | false}][-timingEngine {statistical |
static | pathBasedSSTA}][-timingSelfLoopsNoSkew {true |
false}][-usefulSkew {true | false}][-useOutputPinCap {true |
false}][-warn {true | false}]
This command will set the constants to be propagated during the
building of the timing graph. These constants are obtained from the
timing constraint file or from the netlist information. This
command allow the system to accept module level or the system level
set_input_delay or and set_output_delay variables for the timing
analysis of the I/O's.[-analysisType {single | bcwc |
onChipVariation}]single: Encounter uses one set of PVT corners for
the timing analysisbcwc:Best case Worst case timing analysis.
Encounter uses one corner for the best case and one corner for the
worst case analysis. Both corners are considered at the same run.
setup check in this mode will use the maximum delay possible and
for the hold check uses the minimum delay possible.onChipVariation:
Calculates delay for one path based on maximum operating condition
and other based on minimum operating condition.[-aocv {true |
false}]This option sets the analysis mode to advanced on chip
verification
However the Library does not contain any AOCV based libraries
hence the AOCV analysis cannot be performed
The AOCV based timing for 8 bit adder
timedesign summary of 8 bit adder with AOCV option (Since no
AOCV libraries have been read, this analysis cannot be performed .
The analysis will continue without AOCV based derating
applied.)
Output of the APR of 8 bit adder with clock tree highlighted
CDC design:Very simple design is considered. For clk1 input is
given to internal output and for clk2 internal output is given to
the output
// At clk1 din is given to internal wire, at clk2 dout_internal
is passed t dout_reg
module CDC ( clk1, clk2, rst, din, dout); input clk1;input
clk2;input rst;output dout;input din;reg dout_internal;reg dout;reg
dout_reg;
always @ (posedge clk1)begin dout_internal
