Farzan Fallah Srinivas Devadas Laboratory for Computer Science MIT Farzan Fallah Srinivas Devadas Laboratory for Computer Science MIT Functional Vector

Farzan FallahSrinivas Devadas

Laboratory for Computer Science

MIT

Farzan FallahSrinivas Devadas

Laboratory for Computer Science

MIT

Functional Vector Generation for HDL Functional Vector Generation for HDL Models Using Linear Programming and Models Using Linear Programming and

3-Satisfiability3-Satisfiability

Functional Vector Generation for HDL Functional Vector Generation for HDL Models Using Linear Programming and Models Using Linear Programming and

3-Satisfiability3-Satisfiability

Kurt Keutzer

Department of EECS

UC Berkeley

Kurt Keutzer

Department of EECS

UC Berkeley

Outline

IntroductionFunctional test vector generation strategyNew hybrid SAT methodResultsOngoing work

Design Verification

Introduction

if (C) A = 1;else A = 2;$display(“%d”, A);

Design Verification

How do we solve the design verification problem?

Formal verification Who specifies correctness property?

Simulation How do you get the test vectors?

Introduction

Coverage Directed Simulation

Choose a coverage metric, e.g., line/branch/path

coverage. Automatically generate vectors that achieve

targeted coverage under chosen metric.

Introduction

Functional Vector Generation Strategy

We view HDL descriptions as interconnections of combinational modules which include Boolean and word-level operators.

XY

+f

G>

Z

W

c

d

x2

x0

0

1


Boolean operators: AND, OR, and INVERTER gates.

Word-level operators:

Comparison:

Addition/Subtraction:

Increment/Decrement:

Scalar multiplication:

Left/Right shift:

,,,

/

k /k

kk ,

mXZ mod

integer

X of valuemaximum0

10

0

Y

mY

mZ

YmZX


Any other operator must be converted into a collection of the previous operators.

Example can be modeled as,


can be modeled as,

and 4 constraints over Y and individual bits of X for each pi , where pi is a partial product.

YXZ

Z = 2n-1pn-1+ 2n-2pn-2+ … + p0


We choose path coverage metric.

A path is a set of alternating modules and signals.

m1 m2

S1 S2 S3

P={S1, m1, S2, m2, S3}


Sensitizing a sub-path through a module means the value of the input to the path should affect the value at the output.

A0

0

imSensitizing a path means sensitizing each module .


Sensitization of a sub-path through a module will require values at some of the module inputs.

Value of side-inputs for logic gates,

Side-inputs

AND1

OR0


Value of side-input for word-level operators (assuming unsigned numbers),

ACMAXB )(

AB

C

)(AMAXB

AB

>C

A

CMAXk

)(

Ak

C


b

ac>Y

X

Select a path. Write sensitization requirement on intermediate signals.

b = 1Constraints:

Write module input-output relationship for every module in the circuit.

c = a AND b

b = X > Y

Find a solution that satisfies the set of constraints.


How do we find a solution to the constraints? Use Boolean clauses to model all modules and solve resulting 3-SAT problem.

Use Boolean clauses and linear constraints to model modules and solve the problem using 3-SAT solver and integer program solver.

Both methods use Branch and Bound technique.

Y)(X)YX(

YX

XY

Z)YX(Y)Z(X)Z(

ZYX

YZ

XZ

3-SAT Approach

Use Boolean clauses to model input-output relationship of each gate.

X

Y

ZYX

3-SAT Approach

Solve the resulting 3-SAT problem to find a satisfying assignment for all input variables.

3-SAT approach is not efficient because word-level operators have to be modeled using Boolean operators.

New Hybrid Satisfiability Approach

11

00

b

ea h

XY

+f

g>Z

W0G256ZW

1)G1(256ZW

0WYX

c

d

x2

x0

0

1

We want to exercise a path in the circuit. Use linear word-level operators (Linear arithmetic constraints, LACs) to model data-path.

G

11

00

b

ea h

f

g

c

d

x2

x0

0

1

11

00

b

ea h

f

g

c

d

x2

x0

0

1

Choose values for side-inputs.

0c 1e

0G256ZW

1)G1(256ZW

0WYX


Control part is modeled using Boolean operations. ?? Choose values for side-inputs.

ec

)cgf()cg()cf(

0G256ZW

1)G1(256ZW

0WYX

Gates are modeled using Boolean clauses.


11

00

b

ea h

f

g

c

d

x2

x0

0

1

Gates are modeled using Boolean clauses.

)()()(

)()()(

)()(

)()(

)()()(

)()(

00

22

hedhehd

ebaebea

dxcdxc

dxcdxc

cgfcgcf

ec

Correlation: x0 is first bit of X x2 is third bit of X g is equal to G There is correlation between Boolean

variables and integer variables.

0G256ZW

1)G1(256ZW

0WYX


Essential variable: If there is a single variable in TRUE (complemented) form in a clause it must be set to 1(0).

Simplifying SAT

c must be set to 0.

Correlation: x0 is first bit of X x2 is third bit of X g is equal to G

0G256ZW

1)G1(256ZW

0WYX


)()()(

)()()(

)()(

)()(

)()()(

)()(

00

22

hedhehd

ebaebea

dxcdxc

dxcdxc

cgfcgcf

ec

Correlation: x0-X, x2-X, g-G

Simplifying SAT

New essential variables might be created.

Current assignment: c=0, e=1

0G256ZW

1)G1(256ZW

0WYX


)()(

)()(

)()(

2

2

hdhd

badx

dxgf

Simplifying SAT

Unate variable: If a variable only appears in true (complemented) form it can be set to 1(0).


Current assignment: c=0, e=1

We can set b to 1.

, b=1

Note that there was no integer variable correlated to b.

Use unate variable rule recursively.

0G256ZW

1)G1(256ZW

0WYX


)()(

)()(

)()(

2

2

hdhd

badx

dxgf

Use polynomial time sufficiency check for SAT infeasibility.


If SAT is infeasible, there is no solution for the constraints, otherwise we continue search for the solution.

Linear infeasibility

If linear relaxation of LACs is infeasible, there is no solution to the constraints. This can be checked in polynomial time.

0G256ZW

1)G1(256ZW

0WYX


Current assignment: c=0, e=1, b=1, f=0

)()(

)()( 22

hdhd

dxdx

Branching

Select a Boolean variable heuristically and set it to 1(0), if it fails to find a feasible solution, set it to 0(1).


Choose an input variable which appears in clauses most (x2).

Set x2 to 1.

0G256ZW

1)G1(256ZW

0WYX


Current assignment: c=0, e=1, b=1, f=0

)()(

)()( 22

hdhd

dxdx

Current assignment: c=0, e=1, b=1, f=0, x2=1

Set d to 1.


0G256ZW

1)G1(256ZW

0WYX


)()()( hdhdd

Simplifying SAT

Current assignment: c=0, e=1, b=1, f=0, x2=1, d=1

Branching

Set h to 1.


There is a correlation between x2 and X, use new integer variables and modify LACs.

3X0

31X0

Xx4X8X

01

37

01237

0G256ZW

1)G1(256ZW

0WYX


)(h

, h=1

3X0

31X0

X4X8X

01

37

0137

Branching

Find a solution to LACs using Integer Programming.

Correlation:x0-X, x2-X, g-G

30

310

0 256

1)1(256

48

01

37

0137

X

X

GZW

GZW

WYXX


Current assignment: c=0, e=1, b=1, f=0, x2=1, d=1, h=1

Branching

Free Boolean variables correlated to integer variables, are set to the appropriate values.

Solution

Boolean Variables: c=0, e=1, b=1, f=0, x2=1, d=1, h=1, x0=X, g=X

Integer Variables: X7-3=0, X1-0=0, Y=0, W=4, Z=0, G=1


Branching


Solution

Boolean Variables: c=0, e=1, b=1, f=0, x2=1, d=1, h=1, x0=0, g=X



Branching


Solution

Boolean Variables: c=0, e=1, b=1, f=0, x2=1, d=1, h=1, x0=0, g=1



ExampleHSAT 3-SAT

#Clauses/#LACs #Clauses Exp. Time/

Sat. TimeSat. Time

pport

schsmctla

ctlbc

mult16

17/18

141/24

1/24

1/60

0/104

<1 s

16 s

685

1341

1355

841

1.2/4.7 s

3.1/261 s

4.9/142 s

>1000 s

Results

<1 s

<1 s

<1 s

8466 >1000 s

Ongoing Work

Improvement on satisfiability checking using seamless integration of linear programming and satisfiability.

Currently we use conventional time frame expansion strategy for sequential HDL models. We are exploring more efficient algorithms.

We are working on generating functional vectors for a variety of code coverage metrics.

Future system overviewOngoing Work

Simulationdriver

(vectors)

Simulationmonitor(yes/no)

Simulationengine

Simulationmodel(HDL)

OCCOMCoverageAnalysis

LP-3SATVector

Generation

Is it enough?

Yes

No

Stop

Diagnosis ofUnverifiedPortions

OCCOM talk

Documents

Farzan Fallah Srinivas Devadas Laboratory for Computer Science MIT Farzan Fallah Srinivas Devadas Laboratory for Computer Science MIT Functional Vector