Feeling Comfortable with Logic Analyzers

Application Note 1337

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Contents

Introduction

Oscilloscope or Logic Analyzer? . . . . . . . . . . . . . . . . . . . . . . . . . . . .3What Is a Logic Analyzer? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Timing analyzer basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5State analyzer basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Using Digital Tools Efficiently . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17How to Connect to Your Target System . . . . . . . . . . . . . . . . . . . . . .20Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

If you use the right tools for the job, your attempts to conquer your digitaldebug challenges will be more rewarding and less time consuming.Before you can choose the right tool, it is important to understand thetools at your disposal and what they do best.

This application note gives you a quick overview of logic analyzerbasics. It doesn't cover many detailed measurements, but it does giveyou a good idea of what a logic analyzer can do. We explore questionslike "Why should I use a logic analyzer?" and "What will a logic analyzerdo for me?"

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Oscilloscope orLogic Analyzer?

When given the choice betweenusing a scope or a logic analyzer,many engineers will choose an oscilloscope. Why? Because a scopeis more familiar to most users.However, scopes have limitedusefulness in some applications.Depending on what you are tryingto accomplish, a logic analyzer mayyield more useful information.Because of overlapping capabilitiesbetween scopes and logic analyz-ers, either may be used in somecases. How do you determinewhich is better for your applica-tion? Let's review some basicguidelines.

When to use a scope

• When you need to see small voltage excursions on your signal

• When you need high time-intervalaccuracy

Generally, an oscilloscope is theinstrument to use when you needhigh vertical or voltage resolution.To say it another way, if you need to see every voltage excursion, likethose shown in Figure 1, you shoulduse a scope.

Many scopes, including the new-generation digitizing ones, can alsoprovide very high time-intervalresolution. That is, they can measurethe time interval between two eventswith very high accuracy. Overall, usean oscilloscope when you need parametric information.

Figure 1. Oscilloscope waveform

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When to use a logic analyzer

• When you need to see many signals at once

• When you need to look at signals in your system the same way your hardware does

• When you need to trigger on apattern of highs and lows on several lines and see the result

Logic analyzers grew out of oscilloscopes. They present datain the same general way that ascope does: the horizontal axis istime, the vertical axis is voltageamplitude. But, rather than pro-viding high voltage resolution or time-interval accuracy like ascope, a logic analyzer can captureand display hundreds of signals atonce, something that a scopecannot do. A logic analyzerreacts the same way as yourlogic circuit does when a singlethreshold is crossed by a signalin your system. It recognizes thesignal to be either low or high.

It can also trigger on patterns ofhighs and lows in these signals.

In general, use a logic analyzerwhen you need to look at morelines than your oscilloscope canshow you, provided you do notneed precise time-interval infor-mation. If you need to look atparametric information such asrise time and fall time, a logicanalyzer is not a good choice (seeFigure 2). Logic analyzers areparticularly useful for looking at time relationships or data ona bus – for example, a micro-processor address, data, or control bus. They can decode theinformation on microprocessorbuses and presents it in a meaningful form.

Generally, when you are past theparametric stage of design, andare interested in timing relation-ships among many signals andneed to trigger on patterns oflogic highs and lows, a logic analyzer is the right tool.

Figure 2. Oscilloscope and timing waveforms

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Now that we have talked aboutwhen to use a logic analyzer, let'slook in a bit more detail at whata logic analyzer is. Up to now, wehave used the term "logic analyz-er" rather loosely. In fact, mostlogic analyzers are really twoanalyzers in one. The first part isa timing analyzer, and the sec-ond part is a state analyzer.Each has specific functions thatwe will talk about in the follow-ing sections.

Timing analyzer basics

A timing analyzer is the part of alogic analyzer that is analogousto an oscilloscope. As a matter offact, you can think of them asclose cousins.The timing analyzer displaysinformation in the same generalform as a scope, with the hori-zontal axis representing timeand the vertical axis as voltageamplitude. Because the wave-forms on both instruments aretime-dependent, the display issaid to be in the time domain.

Choosing the right sampling method

A timing analyzer works by sam-pling the input waveforms todetermine whether they are highor low. It cares about only oneuser-defined voltage-threshold. Ifthe signal is above the thresholdwhen it samples, it will be dis-played as a high or 1 by the ana-lyzer. Any signal sampled that isbelow the threshold is displayedas a 0 or low. From these samplepoints, a list of ones and zeros isgenerated that represents a one-bit picture of the input wave-form. As far as the analyzer isconcerned, the waveform iseither high or low – it does notrecognize intermediate steps.This list is stored in memory andis also used to reconstruct a one-bit picture of the input wave-form, as shown in Figure 3.

What Is a Logic Analyzer?

Figure 3. Timing analyzer sample points

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Take a look at the display shownin Figure 4, These waveform dis-plays are actually the same sig-nal (a sine wave) displayed by adigitizing scope and a timinganalyzer. The timing analyzertends to square everything up,which would seem to limit itsusefulness. We should remember,however, that the timing analyzeris not intended to be a paramet-ric instrument. If you want tocheck the rise time of a signalwith an analyzer, you should usea scope. But if you need to verifytiming relationships among sev-eral or hundreds of lines by see-ing them all together, a timinganalyzer is the right choice.

For example, imagine that wehave a dynamic RAM in a systemthat must be refreshed every 2ms. To ensure that everything inmemory is refreshed within that2 ms, a counter is used to countup sequentially through all rowsof the RAMs and refresh each. Ifwe want to make certain that thecounter does indeed count upthrough all rows before startingover, a timing analyzer can be setto trigger when the counterstarts and display all of thecounts. Parametrics are not ofgreat concern here – we merelywant to check that the countercounts from 1 to N and thenstarts over.

Figure 4. The same signal displayed by an oscilloscope and a timing analyzer

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Figure 5. Timing analyzer sampling an input line

When the timing analyzer sam-ples an input line, it is eitherhigh or low. If the line is at onestate (high or low) on one sam-ple and the opposite state on thenext sample, the analyzer"knows" that the input signaltransitioned sometime inbetween the two samples. Itdoesn’t know when, so it placesthe transition point at the nextsample, as shown in Figure 5.This causes some ambiguity as towhen the transition actuallyoccurred and when it is dis-played by the analyzer.

The worst case for this ambiguityis one sample period, assumingthat the transition occurredimmediately after the previoussample point.

With this technique, however,there is a trade-off between reso-lution and total acquisition time.Remember that every samplingpoint uses one memory location.Thus, the higher the resolution(faster sampling rate), the short-er the acquisition window.

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Transitional sampling

When we capture data on aninput line with data bursts, asillustrated in Figure 6, we have toadjust the sampling rate to highresolution (for example, 4 ns) tocapture the fast pulses at thebeginning. This means that a timing analyzer with 4K (4096samples) memory would stopacquiring data after 16.4 µs, andyou would not be able to capturethe second data burst.

Note that in our usual debuggingwork we sample and store datafor a long time where there is noactivity. This uses up logic ana-lyzer memory without providingadditional information. We cansolve this problem if we knowwhen transitions occur and ifthey are positive or negative.This information is the basis fortransitional timing, which usesmemory efficiently.

To implement transitional timing,we could use a “transition detector”

at the input of the timing analyzeralong with a counter. The timinganalyzer will now store onlythose samples that are precededby a transition, together with theelapsed time from the last transi-tion. With this approach, we useonly two memory locations pertransition and no memory at allif there is no activity at theinput. This transitional timingtechnique is used in Agilent16800/900 Series logic analyzers.

In our example, we can capturethe second burst, and also thethird, fourth and fifth bursts,depending on how many pulsesper burst are present. At the sametime, we can keep the timing res-olutions as high as 4 ns (Figure 7).

We can now talk about ‘effectivememory depth’, which equals thetotal time data is captured dividedby the sampling period (4ns).

Note: This is a conceptualdescription of the transitionaltiming technique.

Figure 6. Sampling with a transition detector

Figure 7. Sampling at high resolution

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Glitch capture

Glitches in digital systems can be problematic. Glitches have anasty habit of showing up at themost inopportune times with themost disastrous results. How doyou capture a glitch that occursonce every 36 hours and sendsyour system into the weeds?Once again the timing analyzercomes to the rescue. Agilent logicanalyzers have glitch capture andtrigger capability that makes iteasy to track down elusive glitch problems.

A glitch can be caused by thecapacitive coupling betweentraces, power supply ripples,high instantaneous currentdemands by several devices, orany number of other events. A timing analyzer samples theincoming data and keeps track of any transitions that occurbetween samples, it can readilyrecognize a glitch. In the case ofan analyzer, a glitch is defined asany transition that crosses logicthreshold more than oncebetween samples. (Figure 8.)

The analyzer already keeps trackof all single transitions that occurbetween samples, as we discussedbefore. To recognize a glitch, we“teach” the analyzer to keeptrack of all multiple transitionsand display them as glitches.

While displaying glitches is auseful capability, it can also behelpful to have the ability to trigger on a glitch and displaydata that occurred before it. Thiscan help us to determine whatcaused the glitch. This capabilityalso enables the analyzer to cap-ture data only when we want it –when the glitch occurred.

Think about the example wementioned in the beginning para-graph of this section. We have asystem that crashes periodicallybecause a glitch appears on oneof the lines. Since it occurs infrequently, to store data all thetime (assuming we had enoughstorage capability) would resultin an incredible amount of infor-mation to sort through. Anotheralternative is to use an analyzerwithout glitch trigger capabilityand sit in front of the machinepressing the Run button andwaiting until you see the glitch.

Unfortunately, neither of theabove approaches are practicalalternatives. If we can tell theanalyzer to trigger on a glitch, itcan stop when it finds one, cap-turing all the data that happenedbefore it. We let the analyzer bethe babysitter, and when the system crashes, we have a recordof what led up to the error.

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Figure 8. A glitch

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Triggering the timing analyzer

Another term that should befamiliar to oscilloscope users is“triggering.” It is also used inlogic analyzers, but is oftencalled “trace point.” Unlike anoscilloscope that starts the traceright after the trigger, a logicanalyzer continuously capturesdata and stops the acquisitionafter the trace point is found.Thus a logic analyzer can showinformation prior to the tracepoint, which is known as nega-tive time, as well as informationafter the trace point.

Pattern triggerSetting trace specifications on atiming analyzer is a bit differentfrom setting trigger level andslope on an oscilloscope. Manyanalyzers trigger on a pattern ofhighs and lows across input lines.

Notice the menu in Figure 9. Wehave told the analyzer to startcapturing data when channels 0,2, 4 and 6 of ‘INT4’ are high (logical 1) and when channels1,3,5 and 7 are low (logical 0).Figure 10 shows the resultingdisplay with the line in the middleindicating the trace point. At thetrace point channels 0, 2, 4 and 6are all high while channels 1, 3,5, and 7 are low.

To make things easier for someusers, the trigger point on mostanalyzers can be set in binary(1's and 0's) hex, octal, ASCII, ordecimal numbering. For instance,to set the previous example inhex, the trigger specificationwould be 55 instead of 01010101. Using hex for the triggerpoint is particularly helpfulwhen looking at buses that are 4, 8, 16, 24, or 32 bits wide.Imagine how cumbersome itwould be to set a specificationfor a 24-bit bus in binary.

Figure 9. INT4 set to trigger on a pattern of highs and lows

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Figure 11. Edge-triggered shift register

Figure 10. Waveform with the trace point

Edge triggerEdge triggering is a familiar con-cept to those accustomed tousing an oscilloscope. When youadjust the trigger level knob on ascope, you could think of it assetting the level of a voltage com-parator that tells the scope totrigger when the input voltagecrosses that level. A timing ana-lyzer works essentially the sameon edge triggering except thatthe trigger level is preset to logicthreshold.

Why include edge triggering in atiming analyzer? While manylogic devices are level-dependent,clock and control signals of thesedevices are often edge-sensitive.Edge triggering allows you tostart capturing data as thedevice is clocked.

As a simple example, take thecase of an edge-triggered shiftregister that is not shifting datacorrectly. Is the problem withthe data or the clock edge? Inorder to check the device, weneed to verify the data when it is clocked – on the clock edge(Figure 11).

You can tell the analyzer to cap-ture data when the clock edgeoccurs (rising or falling) andcatch all of the outputs of theshift register. Of course, in thiscase we would have to delay thetrace point to take care of thepropagation delay through theshift register.

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State analyzer basics

In the first part of this applicationnote we talked about one of thetwo major parts of a logic analyzer– the timing analyzer. Next wewill talk about the other majorpart of a logic analyzer – thestate analyzer.

If you’ve never used a state analyzer, you may think it’s anincredibly complex instrumentthat would take a large timeinvestment to master. You mightsay to yourself, “What use could I have for a state analyzer? Idesign hardware.”

The truth is many hardwaredesigners find a state analyzer to be a very valuable tool, espe-cially when tracking down bugsin software and hardware. Astate analyzer can eliminate “finger-pointing” between hard-ware and software teams when a problem comes up. Plus thestate analyzer is not any moredifficult to understand than thetiming analyzer.

When to use a state analyzerIf we want to understand whento use a state analyzer, we need

to know first what a “state” is. A “state” for a logic circuit is asample of a bus or line when itsdata is valid.

For example, take a simple “D”flip-flop, like the one shown inFigure 12. Data at the “D” inputwill not be valid until a positive-going clock edge comes along.Thus, a state for the flip-flop iswhen the positive clock edge occurs.

Now imagine that we have eightof these flip-flops in parallel. Alleight are connected to the sameclock signal (Figure 13).

When a positive transitionoccurs on the clock line, all eightwill capture data at their “D”inputs. Again, a state occurseach time there is a positivetransition on the clock line.These eight lines are analogousto a microprocessor bus.

If we connected a state analyzerto these eight lines and told it to collect data when there is apositive transition on the clockline, the analyzer would do justthat. Any activity on the inputswill not be captured by the stateanalyzer unless the clock is going high.

Figure 12. D flip-flop

Figure 13. Eight D flip-flops in parallel connected to the same clock signal

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Figure 14. RAM timing waveform

This points up the major differ-ence between timing and stateanalyzers. The timing analyzerhas an internal clock to controlsampling, so it asynchronouslysamples the system under test. A state analyzer synchronouslysamples the system since it gets itssampling clock from the system.

As a rule of thumb, you mightremember to use a state analyzerto check “what” happened on abus and a timing analyzer to see“when” it happened. A state analyzer generally displays datain a listing format and a timing analyzer displays data as a waveform diagram. We have to be extremely careful not to mis-interpret the data when the logicanalyzer is capable of displayingstate data as a waveform diagramand timing data as a listing.

Understanding clocks

In the timing analyzer, samplingis under direction of a singleinternal clock. That makes thingsvery simple. However, in the worldof microprocessors, a systemmay have several “clocks.” Let'slook at a brief example.

Suppose for a moment that wewant to trigger on a specificaddress in RAM and see whatdata is stored there. Further,we'll assume that the system usesa Zilog Z80.

In order to capture addressesfrom the Z80 with our state ana-lyzer, we will want to capturewhen the MREQ line goes low.But to capture data, we will wantthe analyzer to sample when theWR line goes low (write cycle) orwhen RD goes low (read cycle).Some microprocessors multiplexdata and address on the samelines. The analyzer must be ableto clock in information from thesame lines but different clocks.

During a read or write cycle, the Z80 first puts an address onthe address bus. Next it assertsMREQ, showing that the addressis valid for a memory read orwrite. Last, the RD or WR line isasserted, depending on whetherwe are doing a read or write. TheWR line is asserted only after thedata on the bus is valid.

Thus, a timing analyzer acts as a demultiplexer to capture anaddress at the proper time andthen catch data that occurs onthe same lines.

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Triggering the state analyzer

Like a timing analyzer, a stateanalyzer has the capability toqualify the data we want to store.If we are looking for a specificpattern of highs and lows onthe address bus, we can tell theanalyzer to start storing when itfinds the pattern and to continuestoring until the analyzer’s memory is full. In the followingexample, we have set the triggerpoint as FFF03187 (hexadecimal)(Figure 15). In this case, we wantto find out what is in locationFFF03187, so we set the datatrigger as don’t cares (XXXX).

This tells the analyzer to triggeron address FFF03187 regardlessof what the data is at that point.

The analyzer captured addressFFF03187 and all following states.Notice that data is 554103E7 ataddress FFF03187 (Figure 16),and that all of the information isdisplayed in hexadecimal format.We could display it in binary, ifthat is helpful. However, it maybe more helpful to have the hexdecoded into assembly code.

If you specify that all informationon the buses is to be displayed inhex, you will get a display thatresembles the one in Figure 16.

Figure 15. Trigger setup for the state analyzer

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What do these hex codes mean?In the case of a processor, specifichex characters comprise aninstruction. If you are very famil-iar with the hex codes, you may beable to look at a hex listing likethe one in Figure 16 and knowwhat instruction it represents.Most of us, however, can't do that.For that reason, most analyzermakers have designed softwarepackages called disassemblers orinverse assemblers. The job ofthese packages is to translate thehex codes into assembly code tomake them easier to read.

For example, Figure 16 shows0000 41B0 and 0000 41B1. If we look those codes up in theMotorola PowerQUICC manual,we find that they represent memwrite 0x00 instructions. Ratherthan having to look up each code,the inverse assembler does it forus. Look at Figure 17 and noticethe difference.

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Figure 16. Data captured by the state analyzer

Figure 17. Hex codes translated into assembly code

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Understanding sequencelevels

State analyzers have “sequencelevels” that aid triggering andstorage. Sequence levels allowyou to qualify data storage moreaccurately than a single triggerpoint. This means that you canaccurately window in on the datawithout storing information youdon’t need. Sequence levels usu-ally look something like this:

1 find xxxx else on xxxx go to level x 2

then find xxxx else on xxxx go to level x 3

trigger on xxxx

Sequence levels are especiallyuseful for getting into a subrou-tine from a specific point in theprogram.

Selective storage saves memory and timeSequence levels make possiblewhat we call selective storage.Selective storage simply meansstoring only a portion out of alarger whole. For instance, sup-pose we have an assembly routinethat calculates the square of agiven number. If the routine is notcalculating the square correctly,we can tell the state analyzer tocapture that routine. We do thisby first telling the analyzer tofind the start of the routine.When it does find the startaddress, we then tell it to lookfor the ending address whilestoring everything in-between.When the end of the routine isfound, we tell the analyzer tostop storing (store no states).Figure 18 shows how selectivestorage works.

Figure 18. Selective storage

Using trigger functions Rather than defining eachsequence level from scratch, you can use pre-defined triggerfunctions. A library of commontrigger functions, such as “FindNth occurrence of an edge” and“Find event ‘n’ times,” provide asimple way to set up the analyzerto trigger on common events andconditions. Functions are availablefor both the state and timingacquisition modes.

You also can use pre-defined trigger functions as a startingpoint for creating custom func-tions. When you break down afunction, you gain access to allthe resource assignment fieldsand branching options. You canchange these fields to change thetrigger structure.

You might need to do this to cre-ate a custom trigger specificationor to create loops and jumps inyour trigger sequence.

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Figure 19. Example of symptoms and cause in different domains

So far we have talked about oscil-loscopes and state and timinganalyzers and their applications.If you are designing or servicingdigital hardware, you probablyhave applications for each one ofthe tools in your area. In thissection we’ll talk about how touse these tools together to isolatethe faults in your system fasterand more efficiently.

Symptoms and their causes

If you troubleshoot digital circuitryyou often have to ask yourself,“What causes this symptom?” Itmight be quite easy to identifythe symptom of a fault, but you

need to find the cause to fix theproblem. Many times, causes and symptoms are in differentdomains. For example, a glitchon a memory control line cancause wrong data to be read fromor written to memory. The symp-tom (wrong data) can be foundin the data domain by using astate analyzer and triggering onthe suspect memory address. The cause, however, cannot beidentified in the data domain. Itis also possible that the symptomis in the time domain (for example,a bad handshake signal on I/Olines), and the cause is in thedata domain (for example, wrongsoftware I/O routine).

Using Digital ToolsEfficiently

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Intermodule measurements

A measurement that involves morethan one measurement instru-ment is called an “intermodulemeasurement.” An intermodulemeasurement requires that allmeasurement tools are integratedin a single instrument and are ableto capture data simultaneously.Figure 20 shows the system configuration menu from a 16800Series logic analyzer with anintegrated oscilloscope display.This setup provides the ability totrace down a glitch in the oscillo-scope domain from a bad data inthe state analysis.

Cross-domain triggering

In our examples we talked abouttriggering a module (state, timinganalyzer or scope) on the symptomof the problem. Once the symptomoccurs and the appropriate ana-lyzer triggers, the module thatmonitors the cause has to startcapturing data. This is achievedby arming one module from thetrigger of the other module. Forfull functionality it is necessarythat each module can receive andsend trigger signals. The bus, onwhich these trigger signals aretransmitted, is called the "inter-module bus" or IMB (Figure 20).

Figure 20. System configuration menu and intermodule bus

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Figure 21. Setting up an intermodule measurement

Figure 22. Cross-domain measurements

Cross-domain time correlation Once we have successfully trig-gered all our measurement mod-ules and finished data capture,we need to look at the captureddata. We are all familiar with thewaveform display of a scope, andwe discussed how to present thedata captured by a state or tim-ing analyzer earlier. In order tocorrelate from one domain toanother, it is convenient to dis-play data from both domains onone screen. But how can we cor-relate between state and timingother than the trace point?Remember, the timing analyzeruses an internal sampling clockthat is asynchronous to the sys-tem, while the state analyzersamples synchronously to thetarget system. If we count the

time between the external statesamples, we have enough timeinformation to correlate fromany point of the timing analyzerwaveform to the appropriatelocation of the state analyzerlisting.

Application example In Figure 22 you see the stateanalyzer is used to trigger on acertain memory access. Both thetiming analyzer and scope aretriggered by the state analyzer toprovide timing information overmultiple channels as well asparametric information on fewerchannels. Note that the cursorsare used to correlate betweentime domain (scope and timinganalyzer) and data domain (state analyzer).

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So far we’ve talked about some ofthe differences between scopesand timing and state analyzers.Before we’re ready to applythese new tools, we should talkabout one more subject – theprobing system.

From using an oscilloscope,you're probably familiar withpassive probes. A scope probe isdesigned to gain easy access to thetarget system while minimizingthe signal distortion. Since wewant to look at parametric infor-mation like voltage levels andrise times, it is important thatthe probe doesn't load the circuitunder test significantly. A typicalscope probe has 1 MΩ impedanceshunted by 10 pF, depending onthe bandwidth required.

On the other hand, a logic ana-lyzer probe is designed to allow

connection of a large number ofchannels to the target systemeasily by trading off amplitudeaccuracy of the signal under test.Remember that a logic analyzeronly distinguishes between twovoltage levels! Traditionally, logicanalyzers used active probe podsthat had an integrated signaldetection circuitry for eightchannels capacitance, giving atotal of 16 pF per channel.

Resistive versus capacitive loading

How does the probe impedanceaffect my measurement?Resistive and capacitive loadingare the two main cause of signaldistortion. Resistive loadingaffects the amplitude of the output through a resistivedivider effect.

How to Connect toYour Target System

Figure 23. Resistor and capacitive loading error plot

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Capacitive loading affects thetiming of the signal under test byrounding and slewing the edges.Amplitude errors from resistiveloading are not significantenough to affect the performanceof most circuits, even when youare probing with 1-GHz scopeprobes with 10-kΩ resistance. Infact, most logic families can oper-ate correctly with as much as10% error in amplitude. Becausemost of these digital ICs exhibittypical output impedance in thelow hundreds of ohms or less,you can use a probe tip resist-ance measuring a few kΩ.

The capacitive loading of probesbecomes more important as clockrates continue to increase in newdesigns. Because of this newincrease of clock rates, circuitsare more sensitive to timingerrors of even a few nanosec-onds. The basic timing-errorimmunity, on the other hand, islimited by a circuit’s clock rate.A CMOS circuit that drives agiven load may operate correctlyeven with a higher clock rate, butthe extra capacitive loading of aprobe on that circuit can produceunexpected timing problems.

Table 1. Increases in CMOS gate delay due to probe capacitance

Capacitance Standard CMOS delta T High-speed CMOS delta T15 pF 25 ns 2.5 ns8 pF 13 ns 1.3 ns2 pF 3 ns 0.3 ns

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Probing solutions

Physical connections to digitalsystems for debugging must bereliable and convenient to deliveraccurate data to the logic analyzerwith minimum intrusion to thetarget system being debugged.Agilent offers a broad selectionof probes and accessories forconnection to target systems.

A common probing solution isthe passive probe with sixteenchannels per cable. Each channelis terminated at both ends with100 kΩ and 8 pF. You can bestcompare the passive probe elec-trically with the scope probe. Theadvantage of the passive probingsystem, besides small size andhigh reliability, is that you canterminate the probe right at thepoint of connection to the targetsystem. This avoids additionalstray capacitance due to thewires from the larger active podsto the circuit under test. As aresult, your circuit under testonly "sees" 8 pF load capacitanceinstead of 16 pF with previousprobing systems.

Analysis probe and other accessories Connecting a state analyzer to amicroprocessor system requiressome effort in terms of mechanicalconnection and clock selection.Remember, we have to clock thestate analyzer whenever data oraddresses on the bus are valid.With some microprocessors itmight be necessary to use externalcircuitry to decode several signalsto derive the clock for the stateanalyzer. An analysis probe pro-vides not only fast, reliable andcorrect mechanical connection toyour target system, but also thenecessary electrical adaptationlike clocking and demultiplexingto capture your system’s operation correctly.

Some microprocessors prefetchinformation from memory thatmay never get executed. Analysisprobes can also distinguishprefetched information from exe-cuted information. Furthermore,an analysis probe typically comestogether with a disassembler to decode the hexadecimal infor-mation into microprocessormnemonics, as discussed earlier.

Figure 24. An analysis probe

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This application note hasexplained what a logic analyzeris and does. Since most analyzersare made up of two major parts,timing and state analyzers, wehave covered them separately. Buttogether, they make up a powerfultool for the digital designer.

The timing analyzer is closely akinto the oscilloscope, but is bettersuited to bus-type structures orapplications where you are deal-ing with many lines. It also hasthe ability to trigger on patternsamong the lines, or on glitches.

A state analyzer is most oftenviewed as a software tool. Inreality, it also has many uses inthe hardware domain. Because it gets its clock from the systemunder test, it can be used to catchdata when the system sees it –on the system's clock.

Armed with this fundamentalknowledge, you can now use alogic analyzer with confidence to debug your digital designs.

Related Agilent literature

• Agilent 16800 Series Portable Logic AnalyzersData sheet, 5989-5063EN

• Agilent 16900 Series Logic Analysis System MainframesData sheet, 5989-0421EN

For copies of this literature, contact your Agilent representativeor visit www.agilent.com/find/logic

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© Agilent Technologies, Inc. 2006

Printed in USA, December 1, 2006

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