FemtoClock Crystal-to-HSTL ICS842256-24 … Sheets/IDT/ICS842256...PRELIMINARY DATA SHEET ICS842256CK-24 REVISION B JULY 15, 2010 1 ©2010 Integrated Device Technology, Inc. FemtoClock®

PRELIMINARY DATA SHEET

ICS842256CK-24 REVISION B JULY 15, 2010 1 ©2010 Integrated Device Technology, Inc.

FemtoClock® Crystal-to-HSTLFrequency Synthesizer

ICS842256-24

General Description

The ICS842256-24 is a 6 differential HSTL output Synthesizer designed to generate reference clocks for SPI-4.2 and XAUI/XGMII 10Gb Ethernet interfaces. Using a 31.25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of frequency select pins: 390.625MHz,312.5MHz, 195.3125MHz and 156.25MHz.

The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS842256-24, with low phase noise VCO technology, can achieve 1ps or lower typical rms phase jitter, easily meeting SPI-4.2 and 10Gb Ethernet jitter requirements. The ICS842256-24 is packaged in a small 32-pin VFQFN package.

Features

• Six differential HSTL output pairs

• Using a 31.25MHz crystal, the two output banks can be independently set for 390.625MHz, 312.5MHz, 195.3125MHz or 156.25MHz

• Selectable crystal oscillator interface or single-ended reference clock input

• VCO: 1562.5MHz

• RMS phase jitter at 156.25MHz (1.875MHz – 20MHz):0.56ps (typical)

• Full 3.3V output supply mode

• -0°C to 70°C ambient operating temperature

• Industrial temperature available upon request

• Available in both standard (RoHS 5) and lead-free (RoHS 6) packagesBlock Diagram

Pin Assignment

The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

VDDO_A

QA0

nQA0

QA1

nQA1

GND

QB0

nQB0

DIV_SELB1

DIV_SELB0

DIV_SELA1

DIV_SELA0

OEB

OEA

VDD

GND

QB

1

nQB

1

VD

DO

_B

GN

D

QB

2

nQB

2

QB

3

nQB

3

XT

AL_

OU

T

nXT

AL_

SE

L

RE

F_C

LK

MR

VD

D

PLL

_SE

L

VD

DA

XT

AL_

IN

ICS842256-2432 Lead VFQFN

5mm x 5mm x 0.925mmpackage body

K PackageTop View

OSC

PhaseDetector

VCO1562.5MHz

Feedback Divider ÷50 (fixed)

2

2

÷4 (default) ÷5÷8÷16

÷4÷8 ÷10 (default)÷16

0

1

1

0

QA0

nQA0

QA1

nQA1

QB0

nQB0

QB1

nQB1

QB2

nQB2

OEA

DIV_SELA[1:0]

DIV_SELB[1:0]

MR

OEB

PLL_SEL

nXTAL_SEL

REF_CLK

XTAL_IN

XTAL_OUT

Pullup

Pulldown

Pullup

Pulldown

Pulldown

Pullup:Pulldown

Pulldown

Pullup

QB3

nQB3


ICS842256-24 Preliminary Data Sheet FEMTOCLOCK® CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1 VDDO_A Power Output power supply pin for Bank A outputs.

2, 34, 5

QA0, nQA0QA1, nQA1

Output Differential Bank A clock output pairs. HSTL interface levels.

6, 12, 17 GND Power Power supply ground.

7, 89, 10

13, 1415, 16

QB0, nQB0,QB1, nQB1,QB2, nQB2,QB3, nQB3

Output Differential Bank B clock output pairs. HSTL interface levels.

11 VDDO_B Power Output power supply pin for Bank B outputs.

18, 27 VDD Power Core supply pins.

19 OEA Input Pullup Output enable pin for Bank A outputs. LVCMOS/LVTTL interface levels.

20 OEB Input Pullup Output enable pin for Bank B outputs. LVCMOS/LVTTL interface levels.

21,22

DIV_SELA0,DIV_SELA1

Input PulldownDivide select pins for Bank A outputs. See Table 3A.LVCMOS/LVTTL interface levels.

23 DIV_SELB0 Input PulldownDivide select pin for Bank B outputs. See Table 3B.LVCMOS/LVTTL interface levels.

24 DIV_SELB1 Input PullupDivide select pin for Bank B outputs. See Table 3B.LVCMOS/LVTTL interface levels

25 VDDA Power Analog supply pin.

26 PLL_SEL Input Pullup PLL select pin. LVCMOS/LVTTL interface levels.

28 MR Input Pulldown

Active HIGH Master Reset. When logic HIGH, the internal dividers are reset, causing the true outputs (QAx, QBx) to go low and the inverted outputs (nQAx, nQBx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.

29 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.

30 nXTAL_SEL Input PulldownCrystal select pin. Selects between the crystal or REF_CLK as the PLL reference source. When HIGH, selects REF_CLK, when LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels.

31,32

XTAL_OUT,XTAL_IN

Input Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4 pF

RPULLUP Input Pullup Resistor 51 kΩ

RPULLDOWN Input Pulldown Resistor 51 kΩ



Function TablesTable 3A. Bank A Frequency Table

Table 3B. Bank B Frequency Table

Inputs

Feedback DividerBank A

Output Divider

QAx, nQAxOutput Frequency

(MHz)Crystal Frequency

(MHz) DIV_SELA1 DIV_SELA0

31.25 0 0 50 4 390.625 (default)

31.25 0 1 50 5 312.5

31.25 1 0 50 8 195.3125

31.25 1 1 50 16 97.65625

Inputs

Feedback DividerBank B

Output Divider

QBx, nQBxOutput Frequency

(MHz)Crystal Frequency

(MHz) DIV_SELB1 DIV_SELB0

31.25 0 0 50 4 390.625

31.25 0 1 50 8 195.3125

31.25 1 0 50 10 156.25 (default)

31.25 1 1 50 16 97.65625



Absolute Maximum RatingsNOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

DC Electrical CharacteristicsTable 4A. Power Supply DC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 5%, TA = 0°C to 70°C

Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 5%, TA = 0°C to 70°C

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VIXTAL_INOther Inputs

0V to VDD-0.5V to VDD + 0.5V

Outputs, IO -0.5V to VDDO + 0.5V

Package Thermal Impedance, θJA 37°C/W (0 mps)

Storage Temperature, TSTG -65°C to 150°C


VDD Core Supply Voltage 3.135 3.3 3.465 V

VDDA Analog Supply Voltage VDD – 0.10 3.3 VDD V

VDDO_A, VDDO_B Output Supply Voltage 3.135 3.3 3.465 V

IDD Power Supply Current 160 mA

IDDA Analog Supply Current 10 mA

IDDO_A + IDDO_B Output Supply Current No Load 120 mA


VIH Input High Voltage 2 VDD + 0.3 V

VIL Input Low Voltage -0.3 0.8 V

IIHInput High Current

REF_CLK, MR, DIV_SELA[1:0], nXTAL_SEL, DIV_SELB0

VDD = VIN = 3.465V 150 µA

OEA, OEB,PLL_SEL, DIV_SELB1

VDD = VIN = 3.465V 5 µA

IILInputLow Current

REF_CLK, MR, DIV_SELA[1:0], nXTAL_SEL, DIV_SELB0

VDD = 3.465V, VIN = 0V -5 µA

OEA, OEB,PLL_SEL, DIV_SELB1

VDD = 3.465V, VIN = 0V -150 µA



Table 4C. HSTL DC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 5%, TA = 0°C to 70°C

NOTE 1: Outputs terminated with 50Ω to ground.NOTE 2: Defined with respect to output voltage swing at a given condition.

Table 5. Crystal Characteristics

NOTE: Characterized using an 18pF parallel resonant crystal.

AC Electrical CharacteristicsTable 6. AC Characteristics, VDD = VDDO_A = VDDO_B = 3.3V ± 5%, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points.NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.NOTE 4: Please refer to the Phase Noise Plot.


VOH Output High Voltage; NOTE 1 1 1.4 V

VOL Output Low Voltage; NOTE 1 0 0.4 V

VOX Output Crossover Voltage; NOTE 2 40 60 %

VSWING Peak-to-Peak Output Voltage Swing 0.6 1.4 V

Parameter Test Conditions Minimum Typical Maximum Units

Mode of Oscillation Fundamental

Frequency 31.25 MHz

Equivalent Series Resistance (ESR) 50 Ω

Shunt Capacitance 7 pF

Drive Level 1 mW


fOUT

Output Frequency Range

QAx, nQAx 97.65625 390.625 MHz

QBx, nQBx 97.65625 390.625 MHz

tsk(b) Bank Skew; NOTE 1 ps

tsk(o) Output Skew; NOTE 2, 3Outputs @ Same Frequency ps

Outputs @ Different Frequencies ps

tjit(Ø)RMS Phase Jitter, Random; NOTE 4

390.625MHz, (1.875MHz - 20MHz) 0.60 ps

312.5MHz, (1.875MHz - 20MHz) 0.58 ps

195.3125MHz, (1.875MHz - 20MHz) 0.58 ps

156.25MHz, (1.875MHz - 20MHz) 0.56 ps

tR / tF Output Rise/Fall Time 20% to 80% 400 ps

odc Output Duty Cycle 50 %



Typical Phase Noise at 156.25MHz

10Gb Ethernet Filter

Phase Noise Result by adding a 10Gb Ethernet filter to raw data

Raw Phase Noise Data

156.25MHzRMS Phase Jitter (Random)

1.875MHz to 20MHz = 0.56ps (typical)

Noi

se P

ower

dBc

Hz

Offset Frequency (Hz)



Parameter Measurement Information

3.3V Output Load AC Test Circuit

Output Skew

Output Rise/Fall Time

RMS Phase Jitter

Bank Skew

Output Duty Cycle/Pulse Width/Period

SCOPE

HSTL

Qx

nQx

GND

0V

VDD,VDDO_A,

VDDA

VDDO_B

3.3V±5%

3.3V±5%

tsk(o)

Qx

nQx

Qy

nQy

20%

80% 80%

20%

tR tF

VSWINGVOX

QA[0:1],QB[0:3]

nQA[0:1],nQB[0:3]

Phase Noise Mask

Offset Frequencyf1 f2

Phase Noise Plot

RMS Jitter = Area Under the Masked Phase Noise Plot

Noi

se P

ower

tsk(b)

QXx

nQXx

QXx

nQXx

Where X = Bank A or Bank B

tPW

tPERIOD

tPW

tPERIOD

odc = x 100%

QA[0:1],QB[0:3]

nQA[0:1],nQB[0:3]



Parameter Measurement Information, continued

Output Crossover Voltage

Applications Information

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS842256-24 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDO_A and VDDO_B should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin.

Figure 1. Power Supply Filtering

60%

50%

VOH

VOL

40%

VOX

QA[0:1],QB[0:3]

nQA[0:1],nQB[0:3]

VDD

VDDA

3.3V

10Ω

10µF.01µF

.01µF



Crystal Input Interface

The ICS842256-24 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 31.25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.

Figure 2. Crystal Input Interface

Overdriving the XTAL Interface

The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition,

matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal.

Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface

XTAL_IN

XTAL_OUT

X118pF Parallel Crystal

C133pF

C227pF

R2100

R1100

RS 43

Ro ~ 7 Ohm

Driv er_LVCMOS

Zo = 50 Ohm C1

0.1uF

3.3V

3.3V

Cry stal Input Interf ace

XTAL_IN

XTAL_OUT

Cry stal Input Interf ace

XTAL_IN

XTAL_OUT

R350

C1

0.1uF

R250

R150Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

VCC=3.3V



Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control PinsAll control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used.

REF_CLK InputFor applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground.

Crystal InputsFor applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground.

Outputs:

HSTL OutputsAll unused HSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.

Termination for HSTL Outputs

Figure 4. HSTL Output Termination

VDDO

Zo = 50

HSTL

+

-

ICS HiPerClockS

VDD

R250

R150

Zo = 50

HSTL

HSTL Driv er



VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific

and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology.

Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

SOLDERSOLDER PINPIN EXPOSED HEAT SLUG

PIN PAD PIN PADGROUND PLANE LAND PATTERN (GROUND PAD)THERMAL VIA



Power ConsiderationsThis section provides information on power dissipation and junction temperature for the ICS842256-24. Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS842256-24 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (160mA + 10mA) = 589.05mW

• Power (outputs)MAX = 40.84mW/Loaded Output pairIf all outputs are loaded, the total power is 6 x 40.84mW = 245.04mW

Total Power_MAX (3.465V, with all outputs switching) = 589.05mW + 245.04mW = 834.09mW

•

Total Power_MAX = 519.75mW + 415.80mW = 935.55mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.834W * 37°C/W = 100.9°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection

θJA vs. Air Flow

Meters per Second 0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29°C/W



3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the HSTL output pair.

HSTL output driver circuit and termination are shown in Figure 6.

Figure 6. HSTL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = (VOH_MAX /RL) * (VDD_MAX – VOH_MAX)

Pd_L = (VOL_MAX /RL) * (VDD_MAX – VOL_MAX)

Pd_H = (1.4V/50Ω) * (3.465V – 1.4V) = 16.52mW

Pd_L = (0.4V/50Ω) * (3.465V – 0.4V) = 24.32mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 40.84mW

VOUT

VDDO

Q1

RL50Ω



Reliability InformationTable 8. θJA vs. Air Flow Table for a 32 Lead VFQFN

Transistor Count

The transistor count for ICS842256-24 is: 2364

θJA vs. Air Flow

Meter per Second 0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29°C/W



Package Outline and Package Dimensions

Package Outline - K Suffix for 32 VFQFN Packages

Table 9. Package Dimensions

Reference Document: JEDEC Publication 95, MO-220

NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9 below.

Top View

Index Area

D

Chamfer 4x0.6 x 0.6 maxOPTIONAL

AnvilSingula tion

A

0. 08 CC

A3A1

Seating Plane

E2 E2 2

L

(N -1)x e (Ref.)

(Ref.)N & N Even

N

eD2 2

D2

(Ref.)N & N Odd

1

2

e2

(Ty p.)If N & N are Even

(N -1)x e (Re f.)

b

Thermal Base

N

OR

AnvilSingulation

N-1NCHAMFER

12

N-1

12

NRADIUS

N-1

12

N

AA

DD

CC

BB

44

4

44

4

Bottom View w/Type B ID Bottom View w/Type C IDBottom View w/Type A ID

There are 3 methods of indicating pin 1 cornerat the back of the VFQFN package are:1. Type A: Chamfer on the paddle (near pin 1)2. Type B: Dummy pad between pin 1 and N.3. Type C: Mouse bite on the paddle (near pin 1)

JEDEC Variation: VHHD-2/-4All Dimensions in Millimeters

Symbol Minimum Nominal MaximumN 32

A 0.80 1.00A1 0 0.05

A3 0.25 Ref.

b 0.18 0.25 0.30ND & NE 8

D & E 5.00 Basic

D2 & E2 3.0 3.3e 0.50 Basic

L 0.30 0.40 0.50



Ordering InformationTable 10. Ordering Information

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Part/Order Number Marking Package Shipping Packaging Temperature842256CK-24 ICS42256C24 32 Lead VFQFN Tray 0°C to 70°C842256CK-24T ICS42256C24 32 Lead VFQFN 2500 Tape & Reel 0°C to 70°C842256CK-24LF ICS2256C24L “Lead-Free” 32 Lead VFQFN Tray 0°C to 70°C842256CK-24LFT ICS2256C24L “Lead-Free” 32 Lead VFQFN 2500 Tape & Reel 0°C to 70°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.


DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are notguaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, thesuitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey anylicense under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDTproduct in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective thirdparty owners.

Copyright 2010. All rights reserved.

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FemtoClock Crystal-to-HSTL ICS842256-24 … Sheets/IDT/ICS842256...PRELIMINARY DATA SHEET ICS842256CK-24 REVISION B JULY 15, 2010 1 ©2010 Integrated Device Technology, Inc. FemtoClock®