FGT electronics integration – reminder/update

FGT Readout/DAQ Update, 20090511 1

FGT electronics integration – reminder/update

ethernettrig/clk

DDL fiber

Wiener MPOD controller

ISEG 8 ch HV-4 kV @ 2 mA

ARC module (APV Readout Controller) [ANL]

ARM (APV Readout Module) [IUCF]

208 V 1 φ

Wiener crate (FGT custom) 6U x 220mm cards

8 2

FGT Cables24 FEE signal & power combo24 HV coax(4 of each per disk)

Cable break connectors/boxes located just outside of west support cylinder, on TPC wheel. This point also provides FGT detector ground tie (to TPC wheel).

External FEE cable (each)Signal:15 twisted pairs (24AWG foam PE)Power:+1.8 V @ 0.90 A (fused for 3 A)-1.8 V @ 1.56 A (fused for 5 A)remote sense

Internal FEE cables : custom low-mass aluminum design with silicone & FEP extruded insulation, solder terminated (copper clad aluminum), 15pr 30AWG & 10c 22AWG

All standard cables will have the required CL2 or CMG rating. Custom cable shall be constructed to meet the UL-1581 Vertical Tray requirements, but not tested by UL

Estimated cable run 65 feet[ West cyl → TPC sec 2/3 boundary → sec 2/3 tray out of magnet → 2nd level platform ceiling tray → 2C7/8/9 ]Cable length to be minimized…

SGIS (to kill all FGT power)

Evaluated


FGT FEE – readout interface

Is defined by the cable connector board; this is the interface– IUCF has designed and fabricated a prototype cable connector board– Addresses the crucial question of whether the FEE – RDO interface can be carried

over long cables, permitting platform-mounted RDO

J 3 -2

1 7 E B H -0 4 4 -P

1 61 71 81 92 02 12 22 32 42 52 62 72 82 93 0

B _ A P V _ C L K -

J 1 -1

S S Q -1 1 1 -0 1 -S -D

11

33

55

77

99

1 11 1

1 31 3

1 51 5

1 71 7

1 91 9

2 12 1

U 3

N B 6 L 1 1 S M N

Q 01

Q 02

Q 13

Q 14

V C C 55

N C6

V E E 77

V E E 88

V TD9 D

1 0 D1 1 V TD1 2

V C C 1 31 3

V C C 1 41 4

V C C 1 51 5

V C C 1 61 6

E P1 7

U 5

N B 6 L 1 1 S M N

Q 01

Q 02

Q 13

Q 14

V C C 55

N C6

V E E 77

V E E 88

V TD9 D

1 0 D1 1 V TD1 2

V C C 1 31 3

V C C 1 41 4

V C C 1 51 5

V C C 1 61 6

E P1 7

B _ A P V _ C L K +

U 1

S C 1 8 I M 7 0 0 I P W

G P I O 01

G P I O 12

R E S E T3

V S S4

G P I O 25

G P I O 36

S D A7

S C L8

R X9TX1 0

G P I O 61 1

V D D1 2

W A K E U P1 3

G P I O 51 4 G P I O 41 5

G P I O 71 6

C L K _ A P V +C L K _ A P V -TR I G _ A P V +

B _ A P V _ TR I G +

C 1 1 . 0 U F

TR I G _ A P V -

B _ A P V _ TR I G -

J 1 -2

S S Q -1 1 1 -0 1 -S -D

22

44

66

88

1 01 0

1 21 2

1 41 4

1 61 6

1 81 8

2 02 0

2 22 2

A +1 . 2 5 V

J 2 -2

S S Q -1 1 1 -0 1 -S -D

22

44

66

88

1 01 0

1 21 2

1 41 4

1 61 6

1 81 8

2 02 0

2 22 2

J 2 -1

S S Q -1 1 1 -0 1 -S -D

11

33

55

77

99

1 11 1

1 31 3

1 51 5

1 71 7

1 91 9

2 12 1

A P V _ -V

A -1 . 2 5 V

C 3 1 . 0 U F

R 1 6 7 . 5 0 K

R 1 4 1 0 0

B _ A P V _ C L K -

A +1 . 2 5 V

C 4 1 . 0 U F

R 1 1 2 0 . 0 K

A +1 . 2 5 V

R 71 5 . 0

R 4 4 0 2

A -1 . 2 5 V

B _ C L K _ R TN +

B _ C L K _ R TN -

R 84 0 2

A +1 . 2 5 V

C 8 2 2 0 P F

C 1 4 4 7 0 P F

B _ C L K _ R TN +B _ C L K _ R TN -

A P V _ R S T

J 3 -1

1 7 E B H -0 4 4 -P

1234567891 01 11 21 31 41 5

A P V _ S C L

A P V _ O U T1 +

A

A P V _ O U T2 +

A P V _ O U T3 +

A P V _ O U T0 -A P V _ O U T1 -

A P V _ S C L

A P V _ O U T0 +

A P V _ O U T2 -A P V _ O U T3 -A P V _ O U T4 -

R 1 2 0 . 0

A P V _ O U T4 +

A P V _ O U T5 +

A -1 . 2 5 V

A P V _ +V

R 1 3 0 . 0

A P V _ O U T5 -

A

R 1 9 0 . 0

A P V _ O U T6 +A P V _ O U T6 -

A P V _ O U T0 -

A P V _ O U T1 -

A P V _ O U T2 -

A P V _ O U T7 +

A P V _ O U T3 -

A P V _ O U T7 -A P V _ O U T8 +

A

A P V _ O U T8 -

A

A P V _ O U T9 +A P V _ O U T9 -

A P V _ O U T4 -

A

A +1 . 2 5 V

A -1 . 2 5 VA +1 . 2 5 V

C 1 6 1 . 0 U F

C 1 7 1 . 0 U F

R 2 0 2 . 0

C 1 8 1 . 0 U F

R 1 81 . 2 7 K

R 22 . 0 0 K

R 32 . 0 0 K

J 3 -3

1 7 E B H -0 4 4 -P

3 13 23 33 43 53 63 73 83 94 04 14 24 34 4

C 1 31 . 0 U F

Q 2Z XTN 2 5 0 1 2 E Z

1

3 24

R 60 . 0

R 54 . 9 9 K

A

A +1 . 2 5 V

C 5 1 . 0 U F

B _ A P V _ C L K -

C 1 12 2 u F

R 1 4 9 . 9

C 1 22 2 u F

B _ A P V _ C L K +

Q 1Z XTP 2 5 0 2 0 D Z

1

3 24

R S 2 3 2 _ TX

C 9 1 . 0 U F



C 1 0 1 . 0 U F

A P V _ R S T

A

R S 2 3 2 _ R X

A P V _ R S T

R 93 . 0 1 K

A -1 . 2 5 V


U 4

A D R 1 5 8 1

3 12

-

+

U 2 A

L T1 8 0 7

12

3

84

R 1 5 1 0 0


A P V _ S D A

A +1 . 2 5 V

D S 1TL M G 1 1 0 0

A -1 . 2 5 V

-

+

U 2 B

L T1 8 0 7

5

67

R 1 0 1 0 0

A -1 . 2 5 V

R 1 71 0 0

C 62 2 u F

A P V _ S D A

A P V _ O U T6 +A P V _ O U T5 +

A P V _ O U T8 +A P V _ O U T7 +

A P V _ O U T9 +

A

C 72 2 u F

A P V _ S D A

A P V _ O U T5 -A P V _ O U T6 -

A P V _ O U T8 -A P V _ O U T7 -

A P V _ O U T9 -

B _ A P V _ C L K +

A P V _ S D A

A P V -V

C 22 2 u F

C 1 52 2 u F

A

LDO voltage regulator

CLK/TRG buffer

UART/I2C bridge


Connector board prototype

Mounts directly onto two MIT APV boards at outer radius of FGT Prototype uses bulky/massive cable connector just for convenience – actual connector

board will be directly terminated to Cu/Al cable– Soldered wires and custom plastic support frame / strain relief

Dimensions (prototype): 75 mm square Shown here with old (single APV) board for preliminary long cable tests; awaiting real

FGT APV boards for final tests

FGT Readout/DAQ Update, 20090511

Readout board frontend prototype and long cable test

Demonstrated basic operation of APV 170% of planned cable length Equalization filter designed and tested ADC (anti-alias) filter design in progress Tests with Struck ADC module and full FGT APV

board within next weeks

4

110 feetBelden #1424A

A typical APV event, 128 channels’ data(here only pedestals)

Slow controls PC


FGT readout crate electronics update

Working on selection of backplane to connect readout controller to APV readout modules– Plan to use standard commercial backplane with sufficient connectivity but define our

own simplistic protocol; just use the traces.– Two obvious choices : VME64x and cPCI

VME64xcPCI


FGT readout electronics update

Assuming 7-slot configuration– Available in both connector styles, a few advantages for cPCI thanks to higher pin

count of “hard metric” 2mm connector.– cPCI 32-bit has ~same number of bussed connections as VME64x but adds 32 pins

for signals to pass through backplane to transition (cable receiver?) card. • Direct cable connection to pass-thru pins a possibility.

– cPCI 64-bit replaces pass-thru pins by 32 extra bussed lines.– cPCI has request/grant signal pair per slot for readout control (all control in master),

whereas VME64x uses daisy chain– VME64x has one signal line (common clock to all boards), whereas cPCI has one

clock wire per slot (star distribution) Currently in process of requesting quotes to compare prices. Pin utilization estimate:

– 32 signals used for readout data– 16 signals used for control address/data– Another ~12 pins for clocks, resets, strobes and token passing


Comparison of signal usage maps

VME64x pin cPCI pin FGT function FGT signal description

LWORD*, A01-A15ACK64,all BRSV*, C/BE[4..0],INTA..D,ENUM A00-A15 Multiplex control address/data bus

AS* DEVSEL# CAS* control address strobe (low edge signals control cycle, timing is fixed)

A16 REQ64# CWRITE* control read/write

SYSCLK CLK[n] APVCLK Clock to APV chips (based on STAR clock)

DS1* TRDY# APVTRIG* Trigger to APV chips

DTACK* FRAME# CLK30MHZ Logic clock (readout and control)

D00-D15, BR0-BR3, AM0-AM4, A17-A23 AD[0]-AD[31] RD00 Readout data bus

SYSRESET* RST# RESET* APV readout module reset

IACKIN* REQ[n] RTOKIN* Readout token in from adjacent board (daisy-chain)

WRITE* N/A RTOKOUTFL* Readout token from master to first board in chain

IACK* N/A RTOKOUTL* Readout token copy for master to check sanity

IACKOUT* GNT[n] RTOKOUTM* Readout token out to adjacent board (daisy-chain)

DS0* IRDY# RTRIG* Readout trigger (event accept)

AM5, ACFAIL, IRQ7..1, SYSFAIL

INTP, INTS, IPMB*, LOCK#, M66EN,PAR, PERR, SERR, STOP Spare pin not defined for FGT

FGT Readout/DAQ Update, 20090511

Current tasks

Complete long cable test with full APV boards and external ADC

– This will include pulse height spectrum, test pulser, possibly test w/ charge-sharing prototype @ MIT

– Defines (confirms) the interface FEE – readout system• Rack allocation can proceed• Aluminum inner cables will be procured• MIT proceeds w/ final APV board design

– Defines the readout board (ARM) frontend circuits• With ADC chip selection, full readout board design will commence

Finalize crate backplane choice and pin assignments

– Crate procurement can proceed Finalize interfaces of ARC (controller) module including DAQ data format

– Full controller board design will commence

8

Documents

FGT electronics integration – reminder/update