Upload
others
View
6
Download
0
Embed Size (px)
Citation preview
12.5 FPGA Page 1
ECE 238L © 2006
Field Programmable Gate Arrays
FPGA
12.5 FPGA Page 2
ECE 238L © 2006
Using ROM as Combinational Logic
A B C F
0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1
tt1
BCAC
F
schem1
8 x 1ROM(LUT)
lut1
AB
C
F
12.5 FPGA Page 3
ECE 238L © 2006
Mapping Larger Functions To ROMsA B C D F
0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 11 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1
BC
D
F
LUT(B+C)
LUT(CD)
BC
DLUT
A’f1 + Af2
A
f1f2
Very similar to how we decomposed functions to implement with MUX blocks…
12.5 FPGA Page 4
ECE 238L © 2006
ROM vs. LUT
• A ROM can be used as a lookup table (LUT)
• An FPGA contains many, many such LUTs– 1,000’s of them
• A 3LUT has 3 inputs + 1 output• A 4LUT has 4 inputs + 1 output
• 3LUTs and 4LUTs are most common…
12.5 FPGA Page 5
ECE 238L © 2006
Mapping a Gate Network to LUTs
12.5 FPGA Page 6
ECE 238L © 2006
3LUT #1
Mapping a Gate Network to 3LUTs
3LUT #2
3LUT #3
12.5 FPGA Page 7
ECE 238L © 2006
4LUT #1
Mapping Same Network to 4LUTs
4LUT #2
12.5 FPGA Page 8
ECE 238L © 2006
Mapping Equations to LUTs
• Each of these equations require 1 LUT:F = aF = abcdF = a’b’c’d + a’bcd’ + a’b’c’d’ + a’b’cdF = a + b + c + dF = (a +b + c + d)(a’ + b’ + c’ + d’)
Not a function of equation complexity,is a function of # unique inputs
12.5 FPGA Page 9
ECE 238L © 2006
FPGAs – What Are They?
I/O Buffers
I/O Buffers
I/O B
uffe
rs
I/O B
uffe
rs
Programmable wiring areasProgrammable logic elements
(LEs)
An FPGA is a Programmable Logic Device (PLD)It can be programmed to perform any function desired.
I/O Buffers communicatebetween FPGA andthe outside world
12.5 FPGA Page 10
ECE 238L © 2006
Programmable Logic Elements (LEs)
• Typically contain a LUT, wires, and storage
4LUT
0
1D Q
inAinBinCinD
out
clk16
12.5 FPGA Page 11
ECE 238L © 2006
Programmable Logic Elements (LEs)
• Typically contain a LUT, wires, and storage
4LUT
0
1D Q
inAinBinCinD
out
clk16
This one provides a registered or unregistered function of the 4 input variables
12.5 FPGA Page 12
ECE 238L © 2006
Programmable Logic Elements (LEs)
• Typically contain a LUT, wires, and storage
4LUT
0
1D Q
inAinBinCinD
out
clk16
Black dots indicate programming bits(configuration bits)
12.5 FPGA Page 13
ECE 238L © 2006
Programmable Logic Elements (LEs)
• Typically contain a LUT, wires, and storage
4LUT
0
1D Q
inAinBinCinD
out
clk16
On power up, configuration bits are loaded into FPGAThis customizes its operation (LUT function, MUX selection)
12.5 FPGA Page 14
ECE 238L © 2006
Programmable Logic Elements (LEs)
• Typically contain a LUT, wires, and storage
4LUT
0
1D Q
inAinBinCinD
out
clk16
Typically, configuration bits are not changed during circuit operation(but, some FPGA’s are dynamically reconfigurable)
12.5 FPGA Page 15
ECE 238L © 2006
Another LE Structure
• Provides two outputs– One combinational, one registered
4LUT
0
1
0
1
D Q
inA
inBinCinDinE
outReg
outComb
clk16
12.5 FPGA Page 16
ECE 238L © 2006
One Configuration
4LUT
0
1
0
1
D Q
inA
inBinCinDinE
outR = reg(inB(inC+inD)
clk16
fn=inB(inC+inD)
=1
12.5 FPGA Page 17
ECE 238L © 2006
Another Configuration
4LUT
0
1
0
1
D Q
inA
inBinCinDinE
outR = reg(inA)
outC = inC’
clk16
fn=inC’
=1
=0
12.5 FPGA Page 18
ECE 238L © 2006
Yet Another Configuration
4LUT
0
1
0
1
D Q
inA
inBinCinDinE
outR = reg(inC’)
outC = inC’
clk16
fn=inC’
=1
=1
12.5 FPGA Page 19
ECE 238L © 2006
An LE With Carry/Cascade Logic
4LUT
inAinBinCinD
16
Carry/Cascade
Cin
Cout
0
1D Qout
clk
Can do two functions at once (cout and Cout)Carry/cascade logic optimized for add/subtract + wide AND,OR, …
Cin and Cout have dedicated connections to neighboringLEs fast carry chains fast arithmetic
12.5 FPGA Page 20
ECE 238L © 2006
An FPGA Architecture (Island Style)R
ow w
ires
Column WiresLogic Elements
Each LE is configured to do a function
Wire intersections are programmed to either connect or not
12.5 FPGA Page 21
ECE 238L © 2006
Programmable Interconnect Junction
Row wire
Column wire
=1 ON Connected
OFF=0 Unconnected
12.5 FPGA Page 22
ECE 238L © 2006
Example Problem
ZD0-D5 ND5 Z’N’
P
• Generate the N, Z, P status flags for a microprocessor
12.5 FPGA Page 23
ECE 238L © 2006
Example Problem
ZD0-D5 ND5 Z’N’
P
• Generate the N, Z, P status flags for a microprocessor
Will require 2 4LUTs Can be done with wiring only or with 1 4LUT
Will require 1 4LUT
12.5 FPGA Page 24
ECE 238L © 2006
6
11
7
12
8
13
9
14
10
15
1 2 3 4 5
D0D1
D2
D3D4D5
ZLUT #1: F1 = D0’• D1’• D2’• D3’LUT #7: F2 = F1•D4’•D5’ Z outputLUT #8: F3 = D5 N output LUT #9: F4 = Z’ • N’ P output
P
N
12.5 FPGA Page 25
ECE 238L © 2006
6
11
7
12
8
13
9
14
10
15
1 2 3 4 5
D0D1
D2
D3D4D5
ZLUT #1: F1 = D0’• D1’• D2’• D3’LUT #7: F2 = F1•D4’•D5’ Z outputLUT #8: F3 = D5 N output LUT #9: F4 = Z’ • N’ P output
P
N
12.5 FPGA Page 26
ECE 238L © 2006
6
11
7
12
8
13
9
14
10
15
1 2 3 4 5
D0D1
D2
D3D4D5
Z
P
LUT #1: F1 = D0’• D1’• D2’• D3’LUT #7: F2 = F1•D4’•D5’ Z outputLUT #8: F3 = D5 N output LUT #9: F4 = Z’ • N’ P output
N
12.5 FPGA Page 27
ECE 238L © 2006
6
11
7
12
8
13
9
14
10
15
1 2 3 4 5
D0D1
D2
D3D4D5
ZLUT #1: F1 = D0’• D1’• D2’• D3’LUT #7: F2 = F1•D4’•D5’ Z outputLUT #8: F3 = D5 N output LUT #9: F4 = Z’ • N’ P output
P
N
12.5 FPGA Page 28
ECE 238L © 2006
6
11
7
12
8
13
9
14
10
15
1 2 3 4 5
D0D1
D2
D3D4D5
ZLUT #1: F1 = D0’• D1’• D2’• D3’LUT #7: F2 = F1•D4’•D5’ Z outputLUT #8: F3 = D5 N output LUT #9: F4 = Z’ • N’ P output
P
N
12.5 FPGA Page 29
ECE 238L © 2006
Configuring an FPGA
• An FPGA contains a configuration pin– Configuration bits are shifted into FPGA using
this pin, one bit per cycle– Configuration bits in FPGA linked into a long
shift register (SIPO)
• Examples on following slides conceptual– Commercial devices slightly different
12.5 FPGA Page 30
ECE 238L © 2006
Structure of a 3LUT
ConfigurationStorage
Bits(Flip Flops)
LUT Output
LUT Inputs
b0b1b2b3b4b5b6b7
3
It’s just an 8:1 MUX
LUT inputs select which configbit is sent to LUT output
Programming LUT function setting configuration bits
12.5 FPGA Page 31
ECE 238L © 2006
How are the Configuration Bit Flip Flops Loaded?
D Q b70
1
CLKCONFIG
D Q b60
1
CLKCONFIG
……
A serial-in/parallel-out(SIPO) shift register
These are the configuration bitswhich the LUT selects from
12.5 FPGA Page 32
ECE 238L © 2006
Configuring the Programmable Interconnect
Row wire
Configurationbit b
Column wire
Arranged in a SIPOshift register also
12.5 FPGA Page 33
ECE 238L © 2006
Additional FPGA Features
Found in commercial FPGAs
12.5 FPGA Page 34
ECE 238L © 2006
Configurable Input/Output
• I/O buffers are at periphery of chip– Some will be inputs, some will be outputs
• Set when chip configured• Configurable I/O cell
– Input static discharge protection– Input signal conditioning (voltage levels, …)– Output drive
• Fast, slow• Tri-state
– Handles a variety of electrical standards• LVTTL• SGT• …
• Configured at same time rest of chip is configured
12.5 FPGA Page 35
ECE 238L © 2006
Configuration Storage
• Actual configuration storage is not flip flops– Use SRAM memory cells
• Many chips can be partially configured– While rest of chip is running
• Different technologies– Program once
• Fuse, anti-fuse configuration– Program multiple times
• SRAM-based configuration
12.5 FPGA Page 36
ECE 238L © 2006
Programmable Interconnections
• Expensive to put programmable connections at every wire junction– Commercial parts partially populate
junctions– No or little loss of routing flexibility
12.5 FPGA Page 37
ECE 238L © 2006
Hierarchical Routing
• Collection of short, medium, and long wires– Both rows and columns
• Signals use wires that go distance needed• CAD tools make determinations • Like alleys, streets, expressways in a city
– Longer distance more limited access points
12.5 FPGA Page 38
ECE 238L © 2006
Clustered LE’s
• Cluster: >= 1 LE• Example: clump of 4
– Dedicated wires within groups of 4 LE’s• Closely related to hierarchical routing• Higher performance• Different vendors different clustering
12.5 FPGA Page 39
ECE 238L © 2006
Embedded Function Units
• Place the following into the FPGA fabric:
multipliersmemoriesI/O interfaces (e.g. gigabit serial links or
ethernet PHY/MAC)CPU’s (PowerPC, ARM, …)
• Result: higher speed, higher density designs
12.5 FPGA Page 40
ECE 238L © 2006
FPGAs Compared To Other Technologies
12.5 FPGA Page 41
ECE 238L © 2006
Performance vs. Flexibility
Flex
ibilit
y
Performance
ASICs
CPUs & DSPs
FPGAs
Goal: the performance of ASIC’s with the flexibility of programmable processors.
ASIC = Application Specific Integrated Circuit
12.5 FPGA Page 42
ECE 238L © 2006
FPGAs vs. CPUs –Flexibility
• Any function can be programmed to run on a CPU– Programming is relatively simple to do
• Any function can also be configured onto an FPGA– Design is significantly harder
• It is digital logic design• Both CPUs and FPGAs can be reprogrammed
(reconfigured) in the field
• Advantage: CPUs
12.5 FPGA Page 43
ECE 238L © 2006
FPGAs vs. CPUs –Performance
• 10+ years of research 10x-100x performance advantage for FPGAs
• Custom hardware – No fetch-decode-memoryAccess overhead– Significant parallelism and pipelining
• Case in point: 1998 SONAR beamformer on an FPGA – BYU Configurable Computing Lab research– 2 x 109 FLOP/sec sustained– 10x-80x faster than comparable CPU technology
• Advantage: FPGAs
12.5 FPGA Page 44
ECE 238L © 2006
FPGAs vs. ASICs -Flexibility
• ASIC is a static hardware design– Wires and transistors fixed at manufacture time– Cannot be upgraded (reprogrammed) in the field
• FPGA can be configured (and reconfigured)– FPGA platform used for a variety of applications
• CCM = Custom Computing Machine (based on FPGAs)
• Advantage: FPGAs
12.5 FPGA Page 45
ECE 238L © 2006
FPGAs vs. ASICs –Performance
• Both ASICs and FPGAs are custom hardware designs
• FPGA configurability comes at a cost– FPGA density = 1/10th to 1/100th of an ASIC
• Result: – Higher cost chip for FPGA– Higher performance/silicon area for ASIC– For some/many applications:
• FPGA just not fast/big enough• Advantage: ASICs
12.5 FPGA Page 46
ECE 238L © 2006
FPGAs vs. ASICs –Cost
• Once the design is complete:– FPGAs can be programmed in seconds
• Negligible up-front costs• No penalty for small volume• Per part cost very high
– ASICs require time-consuming, expensive manufacturing process
• Fabrication facility >= $1G • Significant up-front costs • Penalty for small volume• Per part cost very low
• Advantage: ???? (depends on volumes and application)
12.5 FPGA Page 47
ECE 238L © 2006
FPGA vs. ASIC Production Cost Example
• FPGA– Non-recurring
expenses (NRE) = $0– Per-part cost = $20
(prices vary from a few $’s to $100’s)
– Cost to produce 100 = $2K
– Cost to produce 106 = $20M
• ASIC– NRE expenses = $5M– Per-part cost = $1
– Cost to produce 100 = $5M + $100 ≈ $5M
– Cost to produce 106 = $6M
Volume produced makes a big difference…
12.5 FPGA Page 48
ECE 238L © 2006
FPGAs vs. ASICs – Additional Points
• Manufacturing Time– FPGA = milliseconds for end customer– ASIC = weeks to months
• Fixing Bugs– FPGA = modify design + reconfigure FPGA– ASIC = modify design + remanufacture
• Advantage: FPGA
12.5 FPGA Page 49
ECE 238L © 2006
FPGAs vs. ASICs - Summary
• Two very different technologies– Flexibility: FPGA wins– Performance: ASIC wins– Risk: ?– Cost: ?
• Complex Decision – Only partially based on technical issues– Significant business issues
• Risk• Time-to-market• Market characteristics (elasticity, price sensitivity, …)
12.5 FPGA Page 50
ECE 238L © 2006
Design for FPGAs
1. Draw schematics or write HDL2. CAD tool maps to LUTs + FFs3. CAD tool generates bitstream4. Load bitstream configure the FPGA
12.5 FPGA Page 51
ECE 238L © 2006
Design for ASICs
1. Draw schematics or write HDL2. CAD tool map to physical silicon layout3. Send layout data to silicon fab4. Finished chip does intended function
• Step 1 fairly similar for FPGAs and ASICs– Major differences in later steps
12.5 FPGA Page 52
ECE 238L © 2006
FPGA/ASIC Vital Statistics
• A typical UG lab FPGA has:– 5,000-10,000 LUTs– 200-300 input/output buffers– Clock at ≈ 50 MHz
• A large modern CPU (Pentium circa 2004) has:– 125 million transistors– > 1000 input/output buffers– Clock at > 3GHz
12.5 FPGA Page 53
ECE 238L © 2006
For More Information
• FPGA companies’ WWW sites tend to have lots of information– Catering to a wide range of customers
• Novice to expert• Low volume to high volume
– Data sheets– Application notes– Success stories– CAD tools