Fig. 6-1 Conventional and Array Logic Symbols for OR …islab.soe.uoguelph.ca/.../chap6-mano.pdf · © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER

© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.

6-1

(b) Array logic symbol(a) Conventional symbol

Fig. 6-1 Conventional and Array Logic Symbols for OR Gate


6-2

k address lines

ReadWrite

Memory unit

2k words

n bits per word

n data input lines

n data output lines

Fig. 6-2 Block Diagram of Memory


6-3

Memory address

Binary Decimal

0000000000

0000000001

0000000010

0

1

2

1111111101

1111111110

1111111111

1021

1022

1023

10110101 01011100

10101011 10001001

00001101 01000110

10011101 00010101

00001101 00011110

11011110 00100100

Memory contents

•••••

•••••

Fig. 6-3 Contents of a 1024 × 16 Memory


6-4

TABLE 6-1Control Inputs to a Memory Chip

Chip selectCS

Read/Memory operation

011

�01

NoneWrite to selected wordRead from selected word

WriteR/W

Table 6-1 Control Inputs to a Memory Chip


6-5

(a) Write cycle

(b) Read cycle

Clock

Address

Memoryenable

Read/Write

Datainput

Clock

Address

Memoryenable

Read/Write

Dataoutput

20 ns

T1 T2 T3 T4 T1

Address valid

Data valid

75 ns

20 ns

T1 T2 T3 T4 T1

Address valid

Data valid

65 ns

Fig. 6-4 Memory Cycle Timing Waveforms


6-6

Select

•S

R •

Q

Q

•

•

B

RAM cell

C

C

B

Fig. 6-5 Static RAM Cell


6-7 Select

S

R

Q

Q

B

RAM cell

C

C

B

Select

S

R

Q

Q

RAM cell

X

Wordselect0

Wordselect2n – 1

Data in

Write logic

Read/Write

Bitselect

S

R

Q

Q

X

X

XWordselect0

Wordselect1

Wordselect2n – 1

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

(b) Symbol

RAM cell

RAM cell

RAM cell

(a) Logic diagram

Data outRead logic

•

•

•

•

•

•

•••

•••

•••

•

•

•

•

•

•

•

••

•

•

•

• •

•

•

•

Fig. 6-6 RAM Bit Slice Model


6-8Word select

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

(b) Block diagram

RAM cell

RAM cell

RAM cell

•

•

•

•••

•••

Data input

Chip select

Read/Write

Dataoutput

A3

A2

A1

A0

23

22

21

20

4–to–16Decoder 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A3

A2

A1

A0

Datainput

Dataoutput

(a) Symbol

Read/Write

Memoryenable

16 x 1RAM

•

Fig. 6-7 16-Word by 1-Bit RAM Chip


6-9

(b) Truth table

EN IN OUT

0

1

1

X

0

1

Hi-Z

0

1

(a) Logic symbol

IN

EN

OUT

Fig. 6-8 Three-state Buffer


6-10

IN1

X

X

X

0

1

0

1

0

1

IN0

X

0

1

X

X

0

1

1

0

(b) Truth table

EN1 EN0 OL

0

(S) 0

0

1

1

1

1

1

1

0

(S)1

1

0

0

1

1

1

1

Hi-Z

0

1

0

1

0

1

(a) Logic Diagram

IN0

EN0 •

IN1

EN1

• (S)

(S)

OL

Fig. 6-9 Three-state Buffers Forming a Multiplexed Line OL


6-11

••Data input

Read/Write •

X X X

•

A1 A0

RAM cell0

•

RAM cell4

•

RAM cell8

•

RAM cell12

•

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

RAM cell1

•

RAM cell5

•

RAM cell9

•

RAM cell13

•

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

RAM cell2

•

RAM cell6

•

RAM cell10

•

RAM cell14

•

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

RAM cell3

•

RAM cell7

•

RAM cell11

•

RAM cell15

•

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

Columndecoder

2–to–4 Decoderwith enable

21 20

0 1

Column select

2

Enable

3

Chip select

Dataoutput

Rowselect

Row decoder

A2

A3

• •

X

2–to–4Decoder

20

21

1

2

3

0

•

Fig. 6-10 Diagram of a 16 × 11 RAM Using a 4 × 4 RAM Cell Array


6-12

A0 Chip select

••

Data input 0

•

X

X

X

•

RAM cell0

•

RAM cell4

•

RAM cell8

•

RAM cell12

•

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

RAM cell1

•

RAM cell5

•

RAM cell9

•

RAM cell13

•

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

RAM cell2

•

RAM cell6

•

RAM cell10

•

RAM cell14

•

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

RAM cell3

•

RAM cell7

•

RAM cell11

•

RAM cell15

•

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

Columndecoder 1–to–2 Decoder

with enable

20

0

Column select Dataoutput 0

Rowselect

Row decoder

A1

A2

•

X

2–to–4Decoder

20

21

1

2

3

0

•

EnableDataoutput 1

Data input 1Read/Write

••

1

•

Fig. 6-11 Block Diagram of an 8 × 2 RAM Using a 4 × 4 RAM Cell Array


6-13

Select

B

DRAM cell

(a) (b) (c)

(d) (e)

(f) (g)

Select

D

C

QB

DRAM cell model

C

(h)

T

C

Fig. 6-12 Dynamic RAM Cell, Hydraulic Analogy of Cell Operation, and Cell Model

•


6-14

DRAMbitslice

DRAMbitslice

DRAMbitslice

Input/Output Logic

Column decoderR

ow d

ecod

erColumn addressregister

Row addressregister

Row timinglogic

Refreshcounter

Column timingLogic

Refreshcontroller

Row timinglogic

Data in/Data out

RAS

CAS

R/WOE

Row address

Column address

•

•

•

•

•

•

•

•

•

•

•

•

•

•

Fig. 6-13 Block Diagram of a DRAM Including Refresh Logic


6-15 Select

B

Select

Wordselect0

Wordselect2n – 1

••

Data in

Write logic

Read/Wr ite

Bitselect

Wordselect0

Wordselect1

Wordselect2n – 1

Read/Writelogic

Data in

Data out

Read/Write

Bitselect

(b) Symbol

DRAM cell

DRAM cell

DRAM cell

••• •

••

•

•

•

•

(a) Logic diagram

•••

•••

•

•

Data outRead logic

•

D

C

Q

•

DRAM cell model

•

D

C

Q

•

DRAM cell model

C

Senseamplifier

Fig. 6-14 DRAM Bit Slice Model


6-16

(a) Write cycle

(b) Read cycle

Clock

Outputenable

Read/Write

Datainput

Clock

Address

enable

Read/Write

Dataoutput

20 ns

T1 T2 T3 T4 T1

Data valid

20 ns

T1 T2 T3 T4 T1

Data valid

65 ns

RAS

CAS

RowAddress Address

Column

Output

Hi-Z

RAS

CAS

Address RowAddress Address

Column

75 ns

Fig. 6-15 Timing for DRAM Write and Read Operations


6-17

Input data

Address

Chip select

Output data8

16

DATA

ADRS

CS

8

64K x 8 RAM

Read/Write R/W

Fig. 6-16 Symbol for a 64K × 8 RAM Chip


6-18

Inputdata

DATA

Address

ADRS

CS

Output data

8

8

64K x 8 RAM

Read/Write

R/W

Memoryenable

DATA

ADRS

CS

64K x 8 RAM

DATA

ADRS

CS

64K x 8 RAM

DATA

ADRS

CS

64K x 8 RAM

Lines Lines 0-1517 16

2–to–4decoder

EN

0123

16

0-65,535

65,536-131,071

131,072-196,607

196,608-262,143

•

•

•

•

•

•

•

•

•

R/W

R/W

R/W

Fig. 6-17 Block Diagram of a 256K × 8 RAM


6-19

8

8 8

••

•

8

16

16DATA

ADRS

CS

64K x 8 RAM

R/W

DATA

ADRS

CS

64K x 8 RAM

8 8

16 input data lines

8 8

Address

Chip select

Read/Write

16 output data lines

16

R/W

Fig. 6-18 Block Diagram of a 64K × 16 RAM


6-20

k inputs (address) n outputs (data)2k x n ROM

Fig. 6-19 Block Diagram of ROM


6-21

5–to– 32decoder

0

1

2

3

28

29

30

31

A7 A6 A5 A4 A3 A2 A1 A0

I0

I1

I2

I3

I4

•••

Fig. 6-20 Internal Logic of a 32 × 8 ROM


6-22

TABLE 6-2ROM Truth Table (Partial)

Inputs Outputs

I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0

0000

1111

0000

1111

0000...1111

0011

0011

0101

0101

1011

0100

0010

0110

1001

0101

1101

0001

0100...1010

1110

0000

1001

0111

0110

1001

Table 6-2 ROM Truth Table (Partial)


6-23

0

1

2

3

28

29

30

31

A7 A6 A5 A4 A3 A2 A1 A0

I0

I1

I2

I3

I4

X X X X X

X X

X X X X

X X

X X

X X X X

X X X X

X XX

X X X X

•••

X Fuse intact

Fuse blown

5–to–32decoder

Fig. 6-21 Programming the ROM According to Table 6-2


6-24

TABLE 6-3Truth Table for Circuit of Example 6-1

Inputs Outputs

A2 A1 A0 B5 B4 B3 B2 B1 B0 Decimal

00001111

00110011

01010101

00000011

00001101

00010100

00100010

00000000

01010101

014916253649

Table 6-3 Truth Table for Circuit of Example 6-1


6-25

(a) Block diagram (b) ROM truth table

A0

A1

A2

B0

B1

B2

B3

B4

B5

0

8 x 4 ROM

A200001111

A100110011

A001010101

B500000011

B400001101

B300010100

B200100010

•

Fig. 6-22 ROM Implementation of Example 6-1


6-26

(a) Programmable read-only memory (PROM)

InputsFixed

AND array(decoder)

ProgrammableOR array

OutputsProgrammable

Connections

(b) Programmable array logic (PAL) device

Inputs ProgrammableAND array

FixedOR array

OutputsProgrammable

Connections

(c) Programmable logic array (PLA) device

Inputs ProgrammableOR array

OutputsProgrammable

Connections

Programmable

ConnectionsProgrammable

AND array

Fig. 6-23 Basic Configuration of Three PLDs


6-27

••

•

•

X Fuse intact

Fuse blown

A

B

C

X X

XX

X X

XX X X

X

X

X

X AC

BC

AB

ABC

C C B B A A X

X

0

1

1

2

3

4

F1

F2

Fig. 6-24 PLA with Three Inputs, Four Product Terms, and Two Outputs


6-28

TABLE 6-4Programming Table for the PLA in Figure 6-24

Product term

Inputs Outputs

A B C(T)F1

(C)F2

1 1 0 — 1 —2 1 — 1 1 13 — 1 1 — 14 0 1 0 1 —

ABACBCABC

Table 6-4 Programming Table for the PLA in Figure 6-24


6-29

Fig. 6-25 Solution to Example 6-2

PLA programming table

Outputs

Productterm

1

2

3

4

InputsA B C

1 1 –

1 – 1

– 1 1

0 0 0

(C)F1

1

1

1

–

(T)F2

1

1

–

1

AB

AC

BC

ABC

F1 = AB + AC + BCF1 = AB + AC + BC

0

1

B

C

A

1

1 0

0

0

00 01 11 10BC

A

1 1

0

F2 = AB + AC + ABCF2 = AC + AB + ABC

0

1

B

C

A

1

0 1

0

1

00 01 11 10BC

A

0 0

1


6-30

••

•

•

•

•

•

AND gates inputs

0 1 2 3 4 5 6 7 8 9Productterm

1

2

3

4

5

6

7

8

9

10

11

12

0 1 2 3 4 5 6 7 8 9

I1

I2

I3

I4

F1

F2

F3

F4

••

••

••

••

••

Fig. 6-26 PAL® Device with Four Inputs, Four Outputs, and a Three-wide AND-OR Structure


6-31

TABLE 6-5PAL® Programming Table for Example 6-3

Productterm

AND Inputs

OutputsA B C D W

123

10—

10—

01—

—0—

———

W �

456

1——

—1—

—1—

—1—

———

X �

789

0——

1—0

—1—

—10

———

Y �

101112

—10

——0

—00

—01

1——

Z �

ABCA BCD+

ABCD+

ABCD+B D+

WACD+

A B CD+

Table 6-5 PAL® Programming Table for Example 6-3


6-32

••

•

•

•

•

•

AND gates inputs

A A B B C C D D W WProductterm

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

W

X

Y

Z

••

••

••

••

••

X X X

X X X X

X

X X X

X X

X X

X X

X

XXX

X X X X

A A B B C C D D W W

All fuses intact(always = 0)

X Fuse intact

Fuse blown

X

X

Fig. 6-27 Connection Map for PAL® Device for Example 6-3


6-33

I/O control block

I/O control block

Programmable interconnect array

I/Ocontrolblock

I/Ocontrolblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Logicarrayblock

Fig. 6-28 Altera® MAX 7000™ Structure (Reprinted with Permission of Altera Corporation,© Altera Corp., 1991)


6-34

• • •

•••

- Configurable logic block (CLB)

- Input/Output Block (IOB)

- Switch matrix

Long linesSingle length

Fig. 6-29 Xilinx® XC4000™ FPGA Structure (Adapted with Permission of Xilinx, Inc.)


6-35

(a) Pass transistor control

(b) Multiplexer control

M

G

S D

M

S

MUX

0

1

(c) Look up table implementation

F(A, B, C)

A

B

C

M

M

M

M

M

M

M

M

Fig. 6-30 SRAM Bit Use in Xilinx® FPGAs


6-36

(b) Examples of Connections(a) Switch Matrix Transistors

1

2

Fig. 6-31 Example of Xilinx® Switch Matrix (Adapted with Permission of Xilinx®, Inc.)


6-37G1

G2

G3

G4

Look up Tablefor G'

G'

16 bits of SRAM

F1

F2

F3

F4

Look up Tablefor F'

F'

16 bits of SRAM

Look up Tablefor H' H'

8 bits of SRAM

MUX

DIN

F'

G'

H' S

MUX

G'

H'S

S/RControl

M M

M

M

M

H1 DIN S/R EC

PRED YQ

ECCLR

1

MUX

DIN

F'

G'

H' S

MUX

F'

H'S

S/RControl

MUX

S

M M

M

M

M

PRED XQ

ECCLR

1

Y

X

M

K (CLOCK)

- SRAM cell

•

•

•

•

••

•

•

••

• •

•

MUX

S

Fig. 6-32 Simplified Diagram of a Xilinx® Configurable Logic Block (Adapted with permission of Xilinx®, Inc.)


6-38

PRED

CLR

OUTPUT

Three-state TS

Output Data O

FPGAInterior

PRED

CLR

INPUT

Input Data 1

Input Data 2

I/OPIN

•

Fig. 6-33 Sketch of Xilinx® IOB Structure (Adapted with Permission of Xilinx®, Inc.)

Documents

Fig. 6-1 Conventional and Array Logic Symbols for OR …islab.soe.uoguelph.ca/.../chap6-mano.pdf · © 2001 Prentice Hall, Inc. M. Morris Mano & Charles R. Kime LOGIC AND COMPUTER