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Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

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Page 1: Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

Flynn’s Taxonomyof Computer Architectures

Source: Wikipedia

Michael Flynn 1966

CMPS 5433 – Parallel Processing

Page 2: Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

Flynn’s Taxonomy

Proposed in 1966

General 4 category system

Does not clearly classify all models in use today

There are combinations, also.

Page 3: Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

Four Categories - Terminology

S = Single

I = Instruction Stream

M = Multiple

D = Data Stream

SISD

SIMD

MISD

MIMD

Page 4: Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

SISD

Single Instruction, Single Data stream A sequential computer which exploits no parallelism in either the instruction or data streams. Examples of SISD architecture are the traditional single processor machines like a PC (currently manufactured PC's have multiple processors) or old mainframes.

Page 6: Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

SIMDSingle Instruction, Multiple Data streamsExploits multiple data streams against a single instruction stream to perform operations which may be naturally parallelized.

For example, an array processor or GPU.

Typical for splitting large data sets.

Page 8: Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

NOTE: Front-end processor

ONE processor starts the program– It sends code to the other processors

In diagrams, the front-end is represented by

which sends code to individual PU’s

which execute the remaining code.

Instruction Pool

PU

Page 9: Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

SIMD Code

Each processor executes the same code

Code may be variable based on processor id

Example: Sum elements of array A

for each Pi, i = 0 to 9 // “executed” by front-end

Ti = 0

for j = 0 to 9 // Pi sums its segment

Ti = Ti + A[i * 10 + j]

Page 10: Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

MISDMultiple Instruction, Single Data streamMultiple instructions operate on a single data stream. Uncommon architecture which is generally used for fault tolerance.

Systolic Array: process data & pass on to next PU

Examples include the Space Shuttle flight control computer.

Least common

Page 12: Flynn’s Taxonomy of Computer Architectures Source: Wikipedia Michael Flynn 1966 CMPS 5433 – Parallel Processing

MIMD

Multiple Instruction, Multiple Data streamsMultiple autonomous processors simultaneously executing different instructions on different data.

May send results to central location.

Distributed systems – can be shared memory space or distributed memory space.