FPGA based Space Vector PWM Control IC forThree Phase Induction Motor DriveR.K.PongiannanI N.Yadaiah , Member IEEE

Department of Electrical and Electronics Engineering Department of Electrical and Electronics EngineeringKumaraguru College of Technology, Coimbatore,TN,India JNTU College of Engineering,, Anantapur, AP, India

E- mail: pongiannan_rk@yahoo.co.in E - mail: yadaiahn@hotmail.com

Abstract - In conventional Digital motor controllers, thePWM gating signal generation, current control loop for statorcurrent regulation, dead time generation and othercomputational tasks requires high sampling rate to achieve FPEawide bandwidth performance. To relieve the controller fromthe time consuming computational task of PWM signalgeneration, a novel method of Space Vector PWM signalgeneration is implemented in FPGA using HardwareDescription Language VHDL. The designed Space VectorPWM control IC has been simulated using a single FPGA fromXilinx, inc. The output fundamental frequency can be varied Fig. 1. FPGA -DSP Based Control of digital ac drivesfrom 1.46 Hz to 1.5 kHz and the PWM switching frequencycan be set from 195 Hz to 49.92 kHz. The delay time of PWMoutput is programmable and the SVPWM control IC is generation and the execution of current control loop algorithmsreprogrammable. [3]-[5][8]. Only a limited time is left to control other functions of

the drive. Even though another such DSP can be employed toKey wods Sae ecoPMCVDLadPG.implement the special functions, the design procedure will be

complicated and requires long time to develop hardware andI. INTRODUCTION control software and also the system is not compact. Therefore, in

recent years, motor control and power conversion ICs employingThe nprdictddvelomen in ndutria drves ASICIFPGA technology are receiving more attention [6]-[10] and

over the past two decades [1] [2] is resulted from the process AnCFPGA-aedhPWM cro scemenfor acrestis shown indevelopments demanded by the automation industry. This is Fan FPGA-based PWM control scheme for ac drives is shown in

furter agmened wth icreaed seed f moernFig. land Fig.2. Dynamic and ever progressing developments in

furtheroaugmente withoionrolleasedit sp l prof om rn VLSI Technology have radically affected the design process andmicroprocessors, pmcroconroollers, digit signal Prcso the rapid prototyping of digital systems. FPGA is a new PLD

(DP) cope prganal logi deie (CPD) developed by Xilinx, Inc. with a maximum number ofapplication specific integrated circuit (ASIC) technology

deeoe by Xiix n.wt aiu ubro

app felcaio specificmainegrated circut(AC) tsedchntroloy configurable input/output blocks of 1200 and a speed of 550 MHzand ielproramablegat aray (PGA basd cntrlin virtex-5 family devices. The FPGA comprises of thousands oftechniques used in reduced insulated gate bipolar transistor(IGBT) drive package size coupled with ac motors leads to logic gates, the main blocks are configurable logic block (CLB)achievement of multiple machine configuration with and input output blocks (JOB).

minimal processdowntime. In the conventionaldrives,The FPGA based SVPWM based control of three phasemnionimaliprocuessdontim conveolloop n tioWMgenealtdriv the induction motor drive shown in Fig. 2 has current loop control,functionsimlikem uentedwithan control.loand hM geneiontare voltage and speed regulation is based on the switching patternshasti implementged wt aoodnalog icntreol.nisekind ouffctrob and the target induction machine parameters are considered. Thishas an advantage of good dynamic response but suffers by pae"FG bsdSacVctrPM onolIfrthethe~~~ ~drwak liecmlxt,lmte .ucin n h paper "FPGA based Space Vector PWM control IC for three

thedrawbacksy ike compeictyim u phase Induction motor Drive" is a novel digital circuit realizationdifcut inyscirui moediicantion in ac driveshasbecome scheme for the Space Vector PWM control IC employing a single

theinownsearday DP bseahduntrol insfacdrieshasime FPGA from Xilinx, Inc. The designed SVPWM control IC can bethe intensive araoeerhdeused either for ac motor drives or three-phase ac voltagecircuitry, software control and flexibility to adapt various.' . ~~~~~~~~~~~~reg_ulationsystems. The pa-per rest of the paper is org_anized asapplications .Hoevr PW geeainadcurn .oto follows: Section II describes space vector PWM concepts. Section

loo reuirshghampingrat toachevewid badwith III describes the design of FPGA based SVPWM IC, Architectureperformance. Thrfr,ms.opttoa eore and its components. Section IV gives the simulation results and

ofthe controller must be utilized for PWM gating signal scinVi h ocuin

1-4244-0726-5/06/$20.OO '2006 IEEE 2061

U , =U eXPj(n -1)Xt for n= 1,2,....6 (7)n~ UDCexL3

1 | 5;1 93 S5̂ 9 / / Xwhere,UDC is the DC link voltage

UDC U1 to U6 are active vectors andS 1 | 54 s SS S2 ;UO = U7= 0 are null vectors.

FPGiA halsed SVPWM coiitlol iliterface( wil Wl|Mlicroprocessor 1 DSP

U0(l 1 1) Ul(l 0 0) U2(1 1 0) U3(0 1 0)

Fig. 2. FPGA based SVPWM control

II. PRINCIPLE OF SPACE VECTOR PWMU4(0 1 1) U5(0 0 1 U6(1 01 17( 0 0)

The major purpose of the PWM inverter is to supply avariable-voltage variable-frequency three-phase voltage to Fig. 3. The switching configuration of a three phase PWM Inverterthe ac motor so that the resulting rotating magneto motiveforce has minimum harmonic distortion [8].The Space The stator voltage vector can be decomposed into twoVector Pulse Width Modulation (SVPWM) [8],[11]-[13] orthogonal components in a two-axis coordinate or as amethod is an advanced, computation intensive PWM combination of two basic vectors as in Fig 4. The SVPWMmethod and is probably the best among all the PWM strategy aims to minimize harmonic distortion by selecting thetechniques in the aspects of harmonic distortion and dc bus appropriate switching vectors and determining theirutilization. corresponding dwelling widths. If the reference vector is located

The operating principle of the space vector PWM is in sector I, then it is composed of voltage vector U1, U2 and zeroexplained by representing the space vectors. The motor voltage vectors as illustrated in Fig.5. Since voltage vectors Ul,stator voltage vector can be expressed as a combination of U2 are the basic vectors and U0, U7 are zero vectors, this givesthe inverter output phase voltages Ua ,Ub and Uc, which canbe expressed in vector form as: Uref = U1 (T1 / T3 ) + U2 (T2/ T3) (8)

Us= Ua + Y2Ub + yUC (1) where Tland T2 are the dwelling time for Uland U2 respectively.where, This voltage space vector can be described in rectangular

j. 2x ( coordinates as follows:7y exp - (2)

( p 2 (3) UDC+T UDCcos+T2jV 4 UDC sinO

Ua Um sin (wt) (4) = j) ji)UDC-asOUb=Um sin (wot - 120) (5)Uc Um sin(wot+ 120) (6)

Um is the amplitude of the fundamental component. The U3 U2

space vector Us rotates in a circular orbit at an angular IIvelocity Cl and the direction of rotation depends on the \Iphase sequence of the voltages. U4 v_

A. Reference Vector and Converter switching states I VI U,

A three- phase bridge inverter has 8 permissible V /switching states as Fig.3 depicts and their correspondingvoltage vectors are expressed as U5 U6

Fig. 4. Voltage vectors

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U2 III. FPGA BASED SVPWM CONTROL IC

In practical ac drive applications, the current control, voltageregulation and speed regulation are based on the SVPWMswitching patterns and, therefore, the PWM control circuit shouldbe compatible with a conventional microprocessors and needs a

Uref computer interface. The current control loop, voltage regulationand motor parameters and its variation are to be implemented in

(T2/Ts)U2 the microcroprocessor, which has the flexibility implementing thefloating-point function. This paper describes only the design of

(T11T5)U1 U1 Space Vector PWM control IC for three phase induction motordrives using Very high speed integrated circuit Hardware

Fig.5. Decomposition of voltage vectors in sector 1 Description Language (VHDL) and FPGA.

1 rIR rv v A. FPGA basedSVPWM Control ICArchitectureThe programmable FPGA-based SVPWM control IC

architecture is shown in Fig.7. This IC consists of the commandregisters for setting the frequency, amplitude, phase of the statorvoltage vector, the switching frequency and the delay time for thepower device [8],[14]. The internal structure of the designedSVPWM IC consists of a sin-table address decoder, duty-ratiocalculator, 2 to 3- axis converters, PWM waveform generator,

- > Time programmable delay-time controller and a sector detector.Fig. 6. Space Vector PWM pattern in 6 sectors The basic requirements for realizing the SVPWM scheme is to

first compute the orthogonal components of the voltage vector.Second, these 2-axis orthogonal components are converted to 3-

where, UDC1S dc link voltage, axis components, and then these three-phase PWM waveforms are

arom (9 converted to centralized encased PWM waveforms with minimalFrom "(9)," switching. Finally, the PWM gating signals to the power switches

=2 (Ts 12).a.(sin(60-)I(sin 60) ( 10) of the same phase leg of the inverter are inserted with adjustableT7 = (T

s/2) .a.( 0 ( 0 (1) time delay to protect the phase legs from short-circuiting.

T7=To = (Tg I2) - T2 - T (12) medlytprtcthpaslgsfosot-rutn.B. Orthogonal Voltage Vectors

TABLE I The SVPWM IC receives a rotating voltage vector withVOLTAGE VECTORS,SWITCHING VECTORS AND THE INVERTER amplitude and frequency. An internal sin/cos generator is used to

OUTPUT VOLTAGES produce PWM duty ratio. The command voltage vector isVol Switch ing Line to neutral decomposed into two orthogonal vectors U,(k) and Up(k) in the-tage vectors voltage Line to line voltage stationary -axis, and then they are converted to corresponding

vectors b l- U Uab U 1ca duty ratios d,(k) and dp(k).This duty ratio function is transformed

U0 a b c U U UIn0 U 0 Uc to 3 axes by 2 to 3-axis transformation using the relations[8], [14]U1 1 0 0 2/3 -1/3 -1/3 1 0 -1 d()d,()(3U2 1/3 1/3 -2/3 0 1 -1 da(k)=d(k) (13)U3 0 1 0 -1/3 2/3 -1/3 -1 I 0 db(k) = - 1/2 d (k) - 13 /2 d, (k) (14)U4 0 1 1 -2/3 1/3 1/3 -1 0 1

U5 0 0 1 -1/3 -1/3 2/3 0 -1 1 dc(k) = - 1/2 dp (k) +13 /2 d, (k) (15)U6 1 0 1 1/3 -2/3 1/3 1 -1 0

U7 1 T I 0 0 0 0 0 0 Digital implementation of "(14),"and "(15)," requires floating-The equivalent PWM waveforms which produce the point arithmetic, which complicates the design procedure. This is

required average flux consist of various combinations of the implemented using integer approximations using basic adder,basic vectors. Fig. 6. illustrates the PWM gating signals of subtractor and divider modules without affecting the resolution.the SVPWM scheme in each operating section. Table-Igives details of voltage vectors, switching vectors and thecorresponding output voltages.

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PWM _ Freq_data Dead time

Phase data | ll

Generator | tDP, PiPt-ll da , . Pl-~d

Freqdata |Orthogonal Delaytime p P2duty converter db DGenerator

generator Xq dc GeneratorP_ tP2

U - mag-data p,

l P3+

Tj P3~~~~~~~~~~~~~~3Rattio T2 >.*P

Calculator *

Fig. 7. FPGA based SVPWM control IC Architecture

C. Two Axis -3 Phase Voltage Converter maximum turn-off time. The output signals ta, tb, t, and td decideThe duty ratio function is transformed to 3 axes da(k), the switching pattern for positive, negative legs respectively. The

db(k) and dc(k) by 2- 3 axis transformation. An integer relationships of the gating signal are as follows:approximation is implemented [8] for the value +13 /2 in"(14),"and "(15),". For analysis, a 20 kHz PWM switching Tsignal with switching period of 50pts is considered. An 8-bitresolution of the PWM signal indicates a control clockperiod of around 0.2 hts. This period is usually much shorterthan the turn-off time of the PWM switches for motor drives T * ta Aand is acceptable in most applications. T 1 tb

D. Duty Ratio Controller andPWM Generator TTs Ts _

The duty ratios, T1 and T2 decide turn-on and turn-off_time of the power device and for every switching cycle theyare updated continuously based on the feedback. LThe three-phase duty ratios da(k), db(k) and dc(k) are ' tc

routed to the optimal PWM generator. This SVPWM Tongenerator produces PWM waveforms with minimum ,AT td ATswitching and the same duty-ratio equivalence. There aretwo zero vectors U0 and U7 in the basic switching vectors. Fig 8. PWM waveforms with delay timeHowever, only one of them with the longer dwelling time Ts-Tonshould be used during one switching period. Determining ta = (16)the proper zero vector depends on the duration of its 2dwelling time. The one with the longer dwelling time is t Ts+Ton (17)selected. 2E. Programmable Delay Time Generator Ts-(Ton + AT)

The phase legs of the inverter have to be protected from tc = 2(18)short circuit. Therefore, a programmable delay-time 2controller is introduced in the designed SVPWM IC as Fig.8 td T + (Ton + AT) (19)depicts. The turn-off time of power devices is usually longer 2than its turn-on time, and, therefore, an appropriate delay where, AT is the specified programmable delay time.time must be inserted between these two gating signals. The The delay-time controller generates the gating signals with thelength of this delay time is usually about 1.5 to 2 times the specified time delay.

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F. Macro source code B. Simulation ResultsThe SVPWM control IC has internal modules of 2 axis to

3 phase converter, sin/cos generator, orthogonal duty ratiogenerator, sector detection, PWM generator and OsIIIiII4ldIldilt [1 ihII4IIIIIS Iprogrammable delay time generator. The source code for "2 J_

-axis to 3-phase voltage" converter module is given B SANGIE6(h& J328 EADTfI E7 (hf1U4appendix - I. B r7~ (bex46 23

BVP7(chX)*8h 23IV. RESULTS IS _SUPIDT 22C

8 DAY7 (hfe)48 15The control scheme is simple in architecture and thus BflX7 *8

facilitates the realization of the developed SVPWM B IY7. (hx) #8 DCBV4TESA,3 (he O4g7

controller using FPGA based circuit design approach. The BVAH23U(e A

designed SVPWM control IC has been realized using a P 7......single FPGA (SPARTON).The implementation report is FU52HUMErshown in Table-Il and the internal chip view is shown in PSE -Fig. 9. Space Vector PWM switching pattern has been ---Eachieved for different switching frequencies varyingbetween 222 Hz and 40 kHz with a fundamental frequencyof 50 Hz. Results for fs = 222 Hz, fs = 20 kHz and fs = 40kHz with a fundamental frequency of 50 Hz are shown Fig. Fig. 10. a. SVPWM IC output waveforms for fs = 222 Hz and f= 50z10a, l0b and l0c respectively. Such a wide frequencycontrol with very high frequency-switching is only possible 1 11iL11 m.III IIIIIIIIdby utilizing the state-of-art VLSI digital circuit design _approach. From the result the switching pattern generated BANGLE6 xhk 1

PDEADTIXE (ho 04will reduce the harmonic content and switching losses. BS7 2(h) L _2_ _

A. Implementation report AX I JS <1T 28METarget Device family,Device SPARTAN ,XS20TQ14 EBDAY7 (i8ex 2U0

El DER7, (hix)tg 6TABLE II ( ) 0 0 DiC

IMPLEMENTATION REPORT1B V3ETA23 11XD61DÆ

Parts Size 6|NISEI.Number of CLBs 296/ 400, 74% a PUISE2 fi:771Number of bonded IOBs 39 /113, 34%CLB 4 input LUTs 523 PUI4.CLB 3 input LUTs 50 777Target Speed 3Total equivalent gate count for design 3699Maximum net delay 15.316 nsMaximum combinational path delay 152.271 ns Fig. 10. b. SVPWM IC output waveforms for fs = 20kHz and f= 50 Hz

iCL~~~Ui. C-. C4

BEALE6b 2B DEADTIE7(he0

1TS7~ (h 13 4

CLB- Configurable logic block I/O pad'

Fig . 9. SVPWM IC Internal Chip view Fig. 10.c. SVPWM output waveforms for fs =40 kHz and f = 50 Hz

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V. CONCLUSION APPENDIX - I

The designed Space Vector PWM control IC for A. The source code for "2 - axis to 3-phase voltage"induction motor drive has been simulated using a single converter module:FPGA. The output fundamental frequency can be variedfrom 1.46 Hz to 1.5 kHz and the PWM switching frequency libraryieee;can be set from 195 Hz to 49.92 kHz. The delay time of useieee.stdjogicj 164.all;PWM output is programmable. The designed SVPWM use ieee.stdjlogic-unsigned.all;control IC is reprogrammable. The switching pattern use ieee.stdjlogic_arith.all;generated will reduce the harmonic content, provides entity axis2_vc3phase isefficient as well flexible control and reduces the total size of port (cosk,mak,sink: in std_logic_vector(7 downto 0);the system. This SVPWM IC can be used for high dbk_in,dak_in in stdjlogic_vector(15 downto 0);performance ac drives and power conditioning equipment as dak_out,dbk_out,dck_out: out stdjlogic-vector(7 downto 0));a modulator. end axis2_vc3phase;

AcKNOWLEDGEMENT architecture ax_arch of axis2_vc3phase isThe authors would like to thank the Management of component mul8 is

Kumaraguru College of Technology, Coimbatore, Tamil port(A: in std_logic_vector(7 downto 0);Nadu and Jawaharlal Nehru Technological and University B: in std_logic-vector(7 downto 0);(JNTU), Hyderabad, Andra Pradesh, India for providing all mulout: out stdjlogic-vector(15 downto 0));infrastructural facilities during this work. end component;

REFERENCEScomponent divide2_4_8 is

[1] G. Thomas M. Jahns and Edward L. Owen "AC Adjustable-Speed port ( Data_in: in STD_LOGIC_VECTOR (15 downto 0);drives at the Millennium: How did we get here?" IEEE Transactionson Power Electronics, Vol. 16, No. 1, pp. 17- 25, 2001. SHIFT_1BIT_OUT: out STD_LOGIC_VECTOR (15 downto 0);

[2] J. C Bose.B.K., "Modem Power Electronics and Drives" Pearson SHIFT_2BIT_OUT: out STD_LOGIC_VECTOR (15 downto 0);Education (Singapore) Pte. Ltd., Third Indian reprint, 2003. SHIFT_3BIT_OUT: out STD_LOGIC_VECTOR (15 downto 0););

[3] Hui S. Y. R., "Microprocessor-Based Random PWM Schemes for end component;DC-AC Power Conversion" IEEE Transactions on Power Electronics,Vol. 12, No. 2, pp. 253-260, 1997.

[4] Cassiano Rech,Humberto Pinheiro, Hilton Abilio Grundling, Helio component Subtract8 isLeaes Hey and Joes Renes Penheiro, "Comparison of Digital ControlTechniques with Repetitive Integral Action for Low Cost PWM port (Subtra8-nl,Subtra8ln2: in std_logicvector ( 7 downInverters" IEEE Transactions on Power Electronics, Vol. 18, No. 1, to 0 );pp. 401-410, 2003. Subtra8Out: out stdjlogic-vector ( 7 downto 0 ))

[5] Vlatko Vlatkovic and Dusan Borojevic, "Digital Signal Processor end component;based Control of three phase Space Vector Modulated Converters"IEEE Transactions on Industry Electronics Vol. 41, No.3,pp. 326-332, 1994. component divide64 is

[6] Cirstea M.N, "A complete ASIC controlled Electric Drive System" ponent ivid IsIEEE Conference Proceeding, pp. 561-564, 1996. port ( Data_in: in STDLOGIC_VECTOR (15 downto 0);

[7] Old field J.V and R.C.Dorf, "Field Programmable Gate Array", SHIFT_6BIT_OUT: out STDLOGIC-VECTOR (15 downto 0));Wiley publishing co., New York, 1995. end component;

[8] Ying-Yu Tzou and Hau- Jean Hsu "FPGA Realization of SpaceVector PWM Control IC for 3 phase PWM Inverters" IEEETransactions on Power Electronics, Vol. 12 No. 6, pp. 953-963,1997. signal cosout,sinout : stdjlogic_vector(15 downto 0)

[9] Mauricio Tonelli, Pedro Battaiotto and Maria I.Valla, "FPGA signal dbk2,dbk4,dbk8,dak64: stdjlogic-vector(15 downto 0)Implementation of an Universal Space Vector Modulator" IEEE - beginIEICON, pp. 1172-1177, 2001.

[10] Rafael R. Ramos, Domingo Biel, Enric Fossas, Francesc Guinjoan"A ml : mul8 port map (cosk,mak,cosout);Fixed-Frequency Quasi-Sliding Control Algorithm-Application to m2: mul8 port map (sink,mak,sinout);Power Inverters Design by Means of FPGA Implementation" IEEE dak_out <= dbk_in;Transactions on Power Electronics, Vol. 18, No. 1, pp.344-355, 2003. _

[11] Joachim Holtz," Pulse width Modulation for Electronic Power dl: divide24-8 port map (dbk_in,dbk2,dbk4,dbk8);Conversion", Proceeding of the IEEE, Vol. 82, No. 8, pp. 1194 - d2: divide64 port map (dakjin,dak64);1214, 1994.

[12] Thomas G.Habetler, "A space -Vector based rectifier regulator for end ax_archAC/DC/AC converters", IEEE Transactions on Power Electronics,pp. 30-36, 1993.

[13] Keliang Zhou and Danwei Wang,"Relationship between Space-Vector Modulation and three-Phase Carrier-Based PWM: AComprehensive Analysis" IEEE Transactions on IndustrialElectronics, Vol. 49, No. 1, pp. 186-196, 2002.

[14] Charles H. Routh. Jr, "Digital System design using VHDL" PWSPublishing Company, Boston, 1998.

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