Frank Chang Recognized for Modern Cell Phone Technology ...sscs.ieee.org/images/files/newsletter_archive/sscs_newsletter_200605.pdf · Frank Chang Recognized for Modern Cell Phone

IEEE Solid-State Circuits Society Quarterly Newsletter

Volume 11Number 2May 2006

Solid-State Circuits Society Newsletter 1

Frank Chang Recognized for Modern Cell Phone Technology and WLAN Systems Mau-Chung Frank Chang Receives 2006 IEEE David Sarnoff Award

Dr. Mau-Chung Frank Changreceived the 2006 IEEE DavidSarnoff Award in a ceremony

during the Plenary Session of ISSCC2006 on 6 February, 2006. Dr. Changwas honored for the development ofheterostructure bipolar transistors(HBT) power amplifiers leading totheir commercialization in wirelesscommunications.

“Dr. Chang is regarded as the dri-ving force behind the development andcommercialization of GaAs-based het-erostructure bipolar transistors” said Dr. Michael Lightner, 2006 IEEE Pres-

ident and IEEE Board of Directors rep-resentative at the ceremony. “He took

what was once considered theoreticaltechnology and enabled reliable, readi-

Continued on page 2

Frank Chang Recognized for WLAN Systems . . . . . . . . . . . . . . . . . . . .1

Gabor Temes Honored for Analog Signal Processing Fundamentals . . .1

24 SSCS Members Elevated to IEEE Fellow Class of 2006 . . . . . . . . . . . .4

Congratulations New Senior Members .7Nguyen and Kitching Receive Raper

Award at ISSCC 2006 . . . . . . . . . . . .8McNeill, Coln and Larivee Receive

Winner Award at ISSCC 2006 . . . . .9JSSC CD to Change to DVD: The End

of an Era . . . . . . . . . . . . . . . . . . . .10ISSCC 2006 Panel on Classic Circuits 11Special Chapter Events . . . . . . . . . . .122006 Symposium on VLSI Circuits to

Emphasize Seven Design Areas . . . .14RFIC Symposium to Launch

Microwave Week . . . . . . . . . . . . . .15DAC Receives Record 1,007

Submissions . . . . . . . . . . . . . . . . . .17SSCS Sponsors 2nd Annual Organic

Microelectronics Workshop . . . . . . .182006 IEEE BCTM Meeting in

Maastricht, The Netherlands . . . . . .19SSCS Events Calendar . . . . . . . . . . . .20

IN

Gabor Temes Honored for AnalogSignal Processing FundamentalsGabor C. Temes Receives 2006 IEEE Gustav Robert Kirchoff Award

In a ceremony during the Plenary Ses-sion of ISSCC 2006, Dr. Gabor C.Temes received the 2006 IEEE Gustav

Robert Kirchoff Award for his fundamen-tal contributions to analog-signal-process-ing techniques. This IEEE Technical Field

Award recognizes outstanding contribu-tions to the fundamentals of any aspect ofelectronic circuits and systems that havelong-term significance or impact.

An IEEE Life Fellow and Professor orContinued on page 3

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May 2006 • Volume 11 – Number 22

ly-manufactured commercial devicescritical to the broadband, linear, effi-cient and low-cost power amplifiers inmost of today’s cellular telephones andwireless local area networks (WLANs)”he said.

Dr. Chang “pioneered the develop-ment and technology transfer of theGaAs HBT while a staff member atthe Rockwell Science Center in Thou-sand Oaks, California. He investigatedand resolved gain degradation prob-lems that had branded the transistortechnology as unreliable and difficultto fabricate under high-current opera-tion conditions," said Dr. Lightner.“Dr. Chang developed the emitterledge formation process and imple-mented effective monitoring methodsto manufacture highly reliable GaAsHBTs and power amplifiers. Today,about 80 percent of cellular tele-

phones and all WLAN systems use theGaAs HBT technology developed byDr. Chang for power amplification intransmitters,” he said.

Dr. Chang received a B.S. in physicsfrom National Taiwan University in1972, and a Ph.D. in Electrical Engi-neering from National Chiao-TungUniversity, Taiwan, ROC in 1979. Heis currently a full Professor at theElectrical Engineering Departmentand Director of the High Speed Elec-tronics Laboratory at UCLA. He is aFellow of the IEEE and a co-editor ofthe IEEE Transactions on ElectronDevices. Dr. Chang was also a guesteditor for the IEEE Journal of Solid-State Circuits in 1991 and 1992 andfor the Journal of High Speed Elec-tronics and Systems in 1994.

Before joining UCLA, he was theAssistant Director of the High Speed

Frank Chang Article, Continued from page 1

Electronics Laboratory at the RockwellScience Center (1983-1997). Duringthat period of time, he developed andtransferred the AlGaAs/GaAs HBTtechnology from the research laborato-ry to the production line (ConexantSystems). The HBT production hasnow grown into a multi-billion dollarbusiness worldwide.

Dr. Chang's research work has beenmostly in the development of high-speed semiconductor devices and inte-grated circuits for mixed signal com-munication and sensor system applica-tions. He was the principal investiga-tor at Rockwell to lead the US-DARPA ADC and DAC developmentfor direct conversion transceiver(DCT) and digital radar receivers(DRR) systems. He was the inventorof the multi-I/O reconfigurableRF/wireless interconnects based onFDMA/CDMA multiple access algo-rithms for inter- and intra-ULSI com-munications. His research group hasdemonstrated the world's first sourcesynchronous CDMA bus interfacewith reconfigurable multichip accesscapability. He also led the firstdemonstration of a 2Gsps 6bit ADC inCMOS, a 1Gsps 11bit THA in SiGeand a dual mode (CDMA/AMPS)power amplifier in SiGe for wirelesshandset applications.

He has authored over 200 technicalpapers and 10 book chapters, edited 1book, and hold 17 U.S. patents. Hewas honored with Rockwell's LeonardoDa Vinci (Engineer of the Year) awardin 1992, the National Chiao-TungUniversity's Distinguished AlumniAward in 1997, and National Tsing-Hua University's DistinguishedAlumni Award in 2002. He was namedan IEEE Fellow in 1996 for his contri-butions in ultra-high speed HBT inte-grated circuit development.

President:Richard C. JaegerAlabama Microelectronics CenterAuburn University, [email protected]: +1 334 844-1888

Vice President:Willy SansenKatholieke Universiteit LeuvenLeuven, Belgium

Secretary:David A. JohnsUniversity of TorontoToronto, Ontario, Canada

Treasurer:Rakesh KumarTechnology Connexions Poway, CA

Past President:Stephen H. LewisUniversity of CaliforniaDavis, CA

Other Representatives:Representative to Sensors Council

Darin YoungRepresentative from CAS to SSCS

Domine LeenaertsRepresentative to CAS from SSCS

Un-Ku Moon

Newsletter Co-editors:Lewis TermanIBM T. J. Watson Research Center (retired)[email protected]: +1 914 945-4160

Mary Y. LanzerottiIBM T. J. Watson Research [email protected]: +1 914 945 1358

Elected AdCom Members at LargeTerms to 31 Dec. 06:

Brian AcklandGary BaldwinTom LeeJan RabaeyJan Van der Spiegel

Terms to 31 Dec. 07:Bill BidermanDavid JohnsTerri FiezTakayasu SakuraiMehmet Soyuer

Terms to 31 Dec. 08:Wanda GassAli HajiniriPaul J. HurstAkira MatsuzawaIan Young

Chairs of Standing Committees:Awards David HodgesChapters Jan Van der SpeigelEducation CK Ken YangMeetings Anantha ChandrakasanMembership Bruce HechtNominations Stephen H. LewisPublications Bernhard Boser

For detailed contact information, see the Societye-News: www.ieee.org/portal/site/sscs

For questions regarding Society business, contact the SSCS Executive Office.

Contributions for the May 2006 issue of the e-News must be received by 15 May 2006 at the SSCS Executive Office.

Anne O’Neill, Executive Director Tel: +1 732 981 3400IEEE SSCS Fax: +1 732 981 3401445 Hoes Lane Email: [email protected], NJ 08854

IEEE Solid-State Circuits Society AdCom



Engineering at Oregon State University, Dr. Temes has pub-lished prolifically on analog and digital signal processing andmixed-signal integrated electronics, “progressing from classicalnetwork theory to active filter synthesis to monolithic filterand data converter design,” said Dr. Michael Lightner, 2006IEEE President and IEEE Board of Directors representative atthe ceremony. “Without his work on analog-to-digital convert-ers, DSL and cable-modem Internet connections would bemuch slower than they now are, and the data density of harddisk drives would also be lower than that in today’s systems,”he said.

“Dr. Temes’ research on filter design, optimization methodsand low-sensitivity filter structures has significantly helped theexplosive growth of analog signal processing in MOS integrat-ed circuit technologies during the last 30 years.” He may trulybe considered “one of the ‘fathers’ of the field of modern ana-log and mixed-signal circuits – a field of extraordinary indus-trial importance in the modern world.”

Dr. Temes received his undergraduate education at the Techni-cal University and Eotvos University in Budapest, Hungary, from1948 to 1956, and his Ph.D. in Electrical Engineering from Uni-versity of Ottawa, Canada in 1961. He received an honorary doc-torate from the Technical University of Budapest in 1991.

In addition to his appointment at Oregon State, Dr. Temeshas held academic positions at the Technical University ofBudapest, at Stanford University and at UCLA, and worked inindustry at Northern Electric R&D Laboratories (now Bell-Northern Research), as well as at Ampex Corp. He has served asDepartment Head at both UCLA and Oregon State University.

A Life Fellow of the IEEE, Dr. Temes served as Associate Edi-tor of the Journal of the Franklin Institute, Editor of the IEEETransactions on Circuit Theory, and Vice President of the IEEECircuits and Systems Society (CAS). In 1968 and 1981, he wasco-winner of the CAS Darlington Award, and in 1984 receivedthe Centennial Medal of the IEEE. He received the Andrew ChiPrize Award of the IEEE Instrumentation and Measurement Soci-ety in 1985, the IEEE Circuits and Systems Society EducationAward in 1987 and the Technical Achievement Award in 1998,and the IEEE Millennium Medal as well as the IEEE CAS Gold-en Jubilee Medal in 2000.

Co-editor and co-author of “Modern Filter Theory andDesign” (Wiley, 1973) and “Oversampling Delta-Sigma DataConverters” (IEEE Press, 1997), and co-author of “Introductionto Circuit Synthesis and Design” (McGraw-Hill, 1977), “Ana-log MOS Integrated Circuits for Signal Processing” (Wiley,1986), Dr. Temes has published approximately 300 papers inengineering journals and conference proceedings and con-tributed to several other edited volumes.

Gabor Temes Article, Continued from page 1

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The 7 IEEE Fellows of 2006 evaluatedby SSCS are:

Dr. Bhupendra AhujaDr. James (Brock) BartonDr. Tohru FuruyamaDr. William KrenikProf. Tadahiro KurodaProf. Richard SpencerDr. David Su

The 17 SSCS-member IEEE Fellows of2006 evaluated by other societies are:

Prof. Andreas AndreouProf. Steve ChungDr. Hector De Los SantosProf. Paul FranzonProf. Ramesh HarjaniProf. Qin (Alex) HuangProf. Andre IvanovProf. Bin-Da LiuDr. Frederick RaabDr. Resve SalehProf. Gianluca SettiProf. Naresh Shanbhag

Prof. Yu-Chong TaiDr. Tsuneo TokumitsuDr. Huei WangDr. Katsuyoshi WashioDr. Burnell West

Dr. Bhupendra AhujaIntersil Corporationfor contributions to design ofmixed signal complimentarymetal oxide semiconductor(CMOS) integrated circuits fortelecommunications and com-puter communications systems.

Bhupendra K. Ahuja received hisB.Tech. degree from Indian Institute ofTechnology, Kanpur , India , in 1973 andhis MS and PhD degrees in ElectronicsEngineering from Carleton University,Ottawa, Canada, in 1976, and 1978.

During his career at AT&T Bell Labo-ratories (1978 to 1980), he led the firstCMOS implementation of single-chip

CODEC with Switched-Capacitor filters.This product was manufactured in verylarge volume, eventually finding its wayinto majority of Line-Card of the 80’s.From 1980 to 1992, he worked at IntelCorporation developing more complexTelecom IC‘s and later on the first Pen-tium design.

One of his well known contributionsthat bears his name is a novel frequencycompensation technique for CMOS oper-ational amplifiers. It removes the limita-tions of Miller-Compensation, achieveswider bandwidth and better power sup-ply rejection. This technique, widelyknown as the “Ahuja Compensation,”was published in JSSC in 1983.

From 1992 to 2002, he worked at sev-eral small companies and startups devel-oping low power, high speed mixed ana-log chips for PC graphics controllers,ADSL line drivers, Digital Camera andSONET transceivers. Since 2003, he has

24 SSCS Members Elevated to IEEE Fellow in Class of 20067 SSCS Nominees Attain Highest IEEE Membership Grade

PEOPLE

Dr. Bhupendra Ahuja Dr. Tohru Furuyama Dr. William Krenik

Prof. Richard SpencerProf. Naresh ShanbhagDr. Tadahiro Kuroda

The IEEE Board of Directors selected 24 members of SSCS, including 7 evaluated by the Society, for elevation to the rank ofIEEE Fellow. There are a total of 271 Fellows in the Class of 2006. No more than one-tenth of one percent of the Institutemembership may be elevated to Fellow in a given year. The distinction recognizes extraordinary contributions to one or more

fields of IEEE interest.Dr. Michael Lightner, IEEE President and Board of Directors representative at ISSCC 2006, congratulated five Fellows eval-

uated by SSCS and Dr. Naresh Shanbhag, who was evaluated by the Circuits and Systems Society and chose to receive his plaqueat ISSCC. Dr. James (Brock) Barton and Dr. David Su were unable to attend.



worked at Intersil Corp. as Director ofEngineering on Precision Analog prod-ucts where he is leading the develop-ment of Ultra Low Power PrecisionFloating Gate Voltage Reference prod-ucts. Dr. Ahuja has published numeroustechnical papers and holds many patentsin the area of CMOS Analog IC designs.

Dr. James (Brock)BartonTexas Instruments for contributions to the designof digital signal processingintegrated ciruits.

Brock Barton is aTexas Instruments Fellow, in TI’s DSPSystems/Silicon Development organiza-tion. He received the B.S. and B.A.degrees in physics and mathematics,respectively, from the University ofTexas, Austin, in 1966. He received thePh.D. in solid-state physics from theMassachusetts Institute of Technology in1971. He joined TI in 1972 and hasworked in TI's Equipment Group, Cen-tral Research Laboratories, Semiconduc-tor Group, Semiconductor Process andDesign Center, and DSP Solutions R&DCenter, before moving to DSP Develop-ment. He was responsible for the designof TI's first standard cell library. He hasworked on a number of different pro-grams, including CCD imager andmemory design and development, andCMOS calculator chip product engineer-ing, prior to helping create TI's ASICtechnology. He was responsible for fuzzylogic R&D and 1V DSP chip design inthe DSPS R&D Center. More recently,he led the TI 65nm High PerformanceSRAM Power Management Team, andserves on the TI Technology RoadmapTeam. He is currently working in theAdvanced Architecture and Chip Tech-nology group, on silicon technology-related issues related to design with newprocess flows. He was Co-Chairman ofthe Technical Program Committee forthe 1996 IEEE/ACM International Sym-posium on Low Power Electronics andDesign (ISLPED'96), and Co-GeneralChairman of ISLPED'97. He is on theExecutive Committee for ISLPED,1996-present. He is the TI representa-tive to the MARCO C2S2 (Center forCircuit and Systems Solutions), 2003-present. He was Vice Chairman, IEEE

Solid-State Circuits Society, DallasChapter, 2000-01.

Dr. Tohru FuruyamaToshiba Corporation for contributions to highspeed dynamic randomaccess memory (RAM)design and technologies.

Tohru Furuyamareceived the B.S. degree

in physics from the University of Tokyo,Tokyo, Japan, in 1975, the M.S. degree inelectrical engineering from Cornell Uni-versity, Ithaca, NY, in 1984, and thePh.D. degree in information science fromthe University of Tokyo in 1988.

Dr. Furuyama led several commodityDRAM and Rambus DRAM develop-ments and the embedded DRAM(eDRAM) project for graphics applica-tions at the Semiconductor Device Engi-neering Laboratory, Toshiba Corp. Healso worked on research of new circuittechnologies including sense amplifiersand on studies of reliability issues, such asparticle induced soft errors, hot carrierrelated problems, and wafer level burn-intechnologies. From 1994 to 1996, he wasthe 64Mb DRAM design manager for theToshiba/IBM/Siemens trilateral jointDRAM development project at Burling-ton, VT. He was then a senior manager atthe System LSI Engineering Laboratory,Toshiba Corp, where he was responsiblefor the developments of Toshiba’s original“Media embedded Processor” (MeP),MPEG-4 codec LSI’s for mobile applica-tions that utilized the eDRAM technolo-gy he had established as a project leader.Since 2002, he has been a general manag-er of the SoC Research & DevelopmentCenter, Semiconductor Company, Toshi-ba Corp., where he has been supervisingthe wide range of R&D activities:advanced CMOS technologies, NANDflash memories, embedded memories,novel memories, embedded processors,various digital media related SoC, andsoftware developments.

Dr. William KrenikWireless TerminalsBusiness UnitGarland, TX for contributions to inte-grated circuits and technol-ogy for wireless products.

Bill Krenik received a BEE degreefrom the University of Minnesota in1984, an MSEE degree from SouthernMethodist University in 1987, and aPh.D. in Electrical Engineering fromthe University of Texas at Dallas in1993. Bill holds 38 U.S. patents withseveral more pending, he has publishednumerous technical papers and speaksregularly at industry and technical con-ferences. He is a registered professionalengineer in Texas.

Since 1984, he has been with TexasInstruments in Dallas in a variety ofmanagement and technical roles. He ispresently the Wireless Advanced Archi-tectures Manager with responsibility fordevelopment of advanced wireless tech-nology. Bill’s team assesses new tech-nology, participates in standards activi-ty, develops key technology for use infuture products, and supports new prod-uct activity in emerging market spaces.His research interests include communi-cations technology, cognitive radio, soft-ware defined radio, analog/RF ICdesign, and wireless handset technology.Prior to his present role, Bill held gen-eral management positions over TI’sRFIC and hard disk drive analog ICbusinesses.

Prof. Tadahiro KurodaKeio University, Yokohama,Kanagawa, Japanfor contributions to low-power and high-speed verylarge scale integrated(VLSI) design.

Tadahiro Kuroda (M'88-SM'00-F’06)received the Ph.D. degree in EE fromthe University of Tokyo in 1999. In1982, he joined Toshiba Corporation,where he designed CMOS SRAMs, gatearrays and standard cells. From 1988 to1990, he was a Visiting Scholar with theUniversity of California, Berkeley, wherehe conducted research in the field ofVLSI CAD. In 1990, he was back toToshiba, and engaged in the researchand development of BiCMOS ASIC's,ECL gate arrays, high-speed CMOS LSI’sfor telecommunications, and low-powerCMOS LSI’s for multimedia and mobileapplications. He invented a VariableThreshold-voltage CMOS (VTCMOS)technology to control VTH through sub-



strate bias, and applied it to a DCT coreprocessor and a gate-array in 1995. Healso developed a Variable Supply-volt-age scheme using an embedded DC-DCconverter, and employed it to a micro-processor core and an MPEG-4 chip forthe first time in the world in 1997. In2000, he moved to the Keio University,and he has been a professor since 2002.His research interests include low-power, high-speed CMOS design forwireless and wireline communications,human computer interactions, andubiquitous electronics. He has pub-lished more than 200 technical publica-tions including 50 invited papers, 18books/chapters, and filed more than 100patents. He served as a conferencechair for the Symp. on VLSI Circuits, avice chair for ASP-DAC, TPC chair forthe Symp. on VLSI Circuits, the invit-ed talk program chair for A-SSCC,sub-committee chairs for ICCAD andSSDM, and program committee mem-ber for Symp. on VLSI Circuits,CICC, DAC, ASP-DAC, ISLPED,SSDM, ISQED, and other internation-al conferences.

Prof. Naresh ShanbhagUniversity of Illinoisfor development of a com-munication-centric designparadigm for low powersystems on a chip.

Naresh R. Shanbhagreceived his Ph.D.

degree in Electrical Engineering fromthe University of Minnesota in 1993.He worked at AT&T Bell Laboratories atMurray Hill from 1993 to 1995, wherehe was the lead chip architect forAT&T's 51.84 Mb/s transceiver chipsover twisted-pair wiring for Asynchro-nous Transfer Mode (ATM)-LAN andvery high-speed digital subscriber line(VDSL) chip-sets. Since August 1995,he has been with the Department ofElectrical and Computer Engineeringand the Coordinated Science Laboratoryat the University of Illinois, where he isa Professor. His research interests are inthe design of integrated circuits and sys-tems for broadband communications,including lowpower/high-performanceVLSI architectures for error-control cod-ing equalization, as well as digital inte-

grated circuit design. He has numerouspublications in this area and holds threeUS patents. He is also a co-author of theresearch monograph “Pipelined Adap-tive Digital Filters” published by Kluw-er Academic Publishers in 1994.

Dr. Shanbhag received the 2001IEEE Transactions on VLSI Best PaperAward, the 1999 IEEE Leon K. Kirch-mayer Best Paper Award, the 1999Xerox Faculty Award, the Distin-guished Lecturership from the IEEECircuits and Systems Society in 1997,the National Science FoundationCAREER Award in 1996, and the 1994Darlington Best Paper Award from theIEEE Circuits and Systems Society.From 1997-1999 and from 1999-2002,he served as an Associate Editor for theIEEE Transaction on Circuits and Sys-tems: Part II and the IEEE Transactionson VLSI respecively. He has served onthe technical program committees ofvarious conferences.

Prof. Richard SpencerUniversity of Califor-nia, Davisfor contributions to inte-grated circuits for digitalcommunication and mag-netic recording.

Richard R. Spencerreceived the B.S.E.E. degree from SanJose State University in 1978 and theM.S. and Ph.D. degrees in ElectricalEngineering from Stanford Universityin 1982 and 1987, respectively.

Prof. Spencer has worked at AydinEnergy Division designing circuits forthe IF section of microwave transceiversand at Memorex Corporation designingdisc drive read/write electronics and anintegrated circuit process monitor chipand test system. At Stanford his researchconcentrated on circuit design for inte-grated sensors. He joined the Depart-ment of Electrical and Computer Engi-neering at UC Davis in 1986. Hisresearch focuses on analog circuit designfor RF and baseband communication.He is the primary author of Introduc-tion to Electronic Circuit Design, Pren-tice Hall, 2003.

Professor Spencer held the ChildFamily Professor of Engineeringendowed chair from 1999 to 2005. He

has received the UCD-IEEE Outstand-ing Undergraduate Teaching Awardfour times. He was Vice Chair forUndergraduate Studies from July 1,2000 to June 30, 2003. He was a co-organizer of the IEEE Solid-State Cir-cuits & Technology Committee Work-shop on Integrated Sensors in 1988,and has been a session chair for theInternational Solid-State Circuits Con-ference and the Symposium on VLSICircuits. He was a guest co-editor ofthe IEEE Journal of Solid-State Cir-cuits in December 1992. He was amember of the Program Committee forthe ISSCC from 1987-1993 and wasthe chair of the Sensors, Imagers, andDisplays subcommittee from 1995-1997. He has been an editor and Exec-utive Committee Member of the ISSCCsince 2004.

Dr. David SuAtheros CommunicationsCorporation for contributions to designof analog and mixed-sig-nal integrated circuits forcommunications systems.

David K. Su wasborn in Kuching, Malaysia, in 1961.He received the B.S and M.E. degrees inElectrical Engineering from the Univer-sity of Tennessee, Knoxville, in 1982and 1985 and the Ph.D. degree in Elec-trical Engineering at Stanford Universi-ty, Stanford, CA, in 1994. From 1985to 1989, he worked as an IC designengineer at Hewlett-Packard Companyin Corvallis, Oregon and Singaporewhere he designed full-custom andsemi-custom application-specific inte-grated circuits. From 1989 to 1994, hewas a Research Assistant with the Cen-ter for Integrated Systems, StanfordUniversity. From 1994 to 1999, he wasa Member of Technical Staff with theHigh Speed Electronics Department ofHewlett Packard Laboratories, PaloAlto, CA, where he designed CMOSanalog, RF, and mixed-signal ICs forwireless communications. Since Febru-ary 1999, he has been with AtherosCommunications, Sunnyvale CA, wherehe is the Senior Director of Analog/RFDesign, engaging in the design anddevelopment of integrated CMOS sys-



tems-on-a-chip for wireless communi-cations. He has also been with StanfordUniversity since 1997, where he is aconsulting Associate Professor. Hisresearch interests include the design ofRF, analog, mixed-signal, and data con-version circuits.

Dr. Su is a technical program subcom-mittee member of the ISSCC and an asso-ciate editor of the IEEE Journal of Solid-State Circuits. He was a co-recipient ofthe IEEE Journal of Solid-State Circuits2002 Best Paper Award and the 2004ISSCC Beatrice Winner Editorial Award.

SSCS Members – 2006 Fellows evalu-ated by other Societies are:

Prof. Andreas AndreouJohns Hopkins Universityfor contributions to energy efficient sensorymicrosystems.

Prof. Steve ChungNational Chiao Tung Universityfor contributions to reliability in ultra-thin-oxide complimentary metal oxide semiconduc-tor (CMOS) devices.

Dr. Hector De Los SantosNanoMEMS Research, LLCfor contributions to radio frequency (RF)and microwave micro electromechanicalsystems (MEMS) devices and applications.

Prof. Paul FranzonNorth Carolina State Universityfor contributions to chip-package codesign.

Prof. Ramesh HarjaniUniversity of Minnesotafor contributions to the design and computeraided design (CAD) of analog and radiofrequency circuits.

Prof. Qin (Alex) HuangNorth Carolina State Universityfor contributions to emitter turn-off thyristortechnology and its applications.

Prof. Andre IvanovUniversity of British Columbiafor contributions to intellectual property (IP)for system on a chip (SoC) testing.

Prof. Bin-Da LiuNational Cheng Kung Universityfor contributions to very large scaled integrat-ed (VLSI) processors for neural networks andvideo signal processing.

Dr. Frederick RaabGreen Mountain Radio Research Co.for contributions to modeling and design ofhigh-efficiency power amplifiers and radiotransmitters.

Dr. Resve SalehUniversity of British Columbiafor contributions to mixed-signal integratedcircuit simulation and design verification.

Prof. Gianluca SettiUniversity of Ferrarafor contributions to application of nonlineardynamics to communications, signal process-ing, and information technology.

Prof. Yu-Chong TaiCalifornia Institute of Technologyfor contributions to integrated nano/micro-electro-mechanical systems (MEMS) andnano/micro-fluidics for Lab-on-a-Chipapplications.

Dr. TsuneoTokumitsuEudyna Devices (formerly Fujitsu Quan-tum Devices Ltd.)for contributions to uniplanar and 3-dimen-sional monolithic microwave integrated cir-cuits (MMICs).

Dr. Huei WangNational Taiwan Universityfor contributions to broadband and millime-ter-wave monolithic millimeter-wave inte-grated circuits (MMICs) and radio frequen-cy integrated circuits (RFICs).

Dr. Katsuyoshi WashioCentral Research Laboratory, Hitachi,Ltd.for contributions to high-speed silicon and sil-icon germanium bipolar/Bi complimentarymetal oxide semiconductors (CMOS) deviceand circuit technologies.

Dr. Burnell WestCredence Systems Corporationfor contributions to high-performance auto-matic test equipment.

Congratulations New Senior Members17 Elected in February

Diego Barrettino Hawaii SectionJose De La Rosa Spain SectionAntoni Fertner Sweden SectionWesley Gee Central Georgia SectionMichael Gilsdorf Denver SectionBaher Haroun Dallas SectionW. Matthew Hogan Oregon SectionChulwoo Kim Seoul SectionTorsten Lehmann New South Wales Section

Marco Maccarrone Italy SectionDenis Masliah France SectionAndrew Mason Southeastern Michigan SectionRobert Montgomery Philadelphia SectionNovat Nintunze Oregon SectionMichael Oshima Santa Clara Valley SectionMark Santoro Santa Clara Valley SectionZhenhai Shao Singapore Section



Clark T. C. Nguyen (DARPA,Arlington, VA and University ofMichigan) and John Kitching

(NIST, Boulder, CO) received the JackRaper Award for Outstanding Technolo-gy Directions Paper at ISSCC 2006 fortheir ISSCC 2005 article “Towards Chip-Scale Atomic Clocks.”

Summary: Atomic clocks have thepotential to greatly enhance the timing,and ultimate performance, of many elec-tronic systems, such as parallel A/D con-verters, spread-spectrum communica-tions and GPS receivers. However, theirsize and power consumption have beenprohibitively large for use in man-portable applications.

This paper demonstrates a miniaturephysics package, shown to the right, for achip-scale atomic clock that includes a tinymicromachined cesium (Cs) atomic vaporcell, an 852nm VCSEL, a photodiodedetector, polarizing and focusing optics,heater elements to maintain Cs atoms in avapor state, and a micromechanical suspen-sion system that thermally isolates thevapor cell/heater structure to allow elevat-ed temperatures with low-power consump-tion. The system is implemented in a

MEMS-enabled size less than 10mm3,which is more than 700x smaller in volumethan the smallest atomic clock physicspackage in production, shrinking atomicclocks from their present-day table-topsizes down to only 1 cubic centimeter.When one shrinks the atomic cell to lessthan 10mm3, using the MEMS technology,the amount of power needed to keep theatoms in a vapor state can be reduced to less

than 10mW in a properly designed ther-mal control system. In effect, the smallerthe mechanical structure, the less power isneeded to heat up to a given temperature.The physics package described in the paperconsumes 75mW of power, which is 100xbetter than the present lowest power pro-duction atomic clock, but still not lowenough to meet the 30mW Chip-ScaleAtomic Clock (CSAC) total clock powergoal (which implies a ceiling of ~10m Wfor the physics package alone).

The accomplishments described inthis paper are a direct result of fundingunder the Defense Advanced ResearchProjects Agency’s CSAC program,which Nguyen ran for the past 3.5years. This program specifically aims totake advantage of the enormous minia-turization and thermal isolation oppor-tunities afforded by MEMS technologyto achieve an atomic clock that occupiesa volume less than 1 cubic centimeterand consumes less than 30 mW total,all while retaining an Allan deviationbetter than 10-11 at one hour, which ison par with much larger existing atom-ic clocks. To date, approximately oneyear after the paper was given, an atom-ic clock physics package has been

Nguyen and Kitching Receive Jack Raper Award at ISSCC 2006

TECHNICAL LITERATURE

From left: Tim Tredwell, ISSCC Executive Chair, John Kitching and Clark T. C. Nguyen.

MEMS technology is used for a chip-scale atomic clock with thermal isolation thatuses 30 mW.



achieved that consumes only 5mW toachieve the needed Cs vapor tempera-ture, and complete atomic clocks havebeen demonstrated that measure lessthan 10 cm3, consume less than 150mW of total power, and attain betterthan 5e-11 Allan deviation at 100 sec-onds. The program is now in its thirdphase, which is expected to culminatewith devices that actually meet thegoals of the CSAC program.

Interestingly, the main barrier toachieving the power goals of CSAC’satomic clocks is no longer heating of thephysics package, but actually now is theequally important power drains by theelectronics for the microwave oscillatorand for environmental control. These arealso discussed in the paper.

Prof. Clark T.-C. Nguyen received theB.S., M.S., and Ph.D. degrees from theUniversity of California at Berkeley in1989, 1991, and 1994, respectively, allin Electrical Engineering and ComputerSciences. In 1995, he joined the facultyof the Department of Electrical Engi-neering and Computer Science at theUniversity of Michigan, Ann Arbor, towhich he has very recently returned aftera 3.5 year leave in Washington, DC,where he served as the MEMS ProgramManager in the Microsystems Technolo-gy Office (MTO) of DARPA. His tech-nical interests at Michigan focus uponmicro electromechanical systems(MEMS) and include integrated vibrat-ing micromechanical signal processorsand sensors, merged circuit/microme-

chanical technologies, RF communica-tion architectures, and integrated circuitdesign and technology. Prof. Nguyenand his students at Michigan have gar-nered numerous Best Paper Awards atprestigious conferences, including the1998 and 2003 IEEE Int. ElectronDevices Meetings, the 2004 IEEE Ultra-sonics Symposium, the 2004 DARPATech Conference, the 2004 IEEE Cus-tom Integrated Circuits Conference, the2005 IEEE ISSCC, and the 2005 IEEEFrequency Control Symposium.

In 2001, Prof. Nguyen founded Dis-cera, Inc., a company aimed at commer-cializing communication productsbased upon MEMS technology, with aninitial focus on the vibrating microme-chanical resonators pioneered by hisresearch in past years. He served as VicePresident and Acting Chief TechnologyOfficer (CTO) of Discera from 2001 tomid-2002.

In mid-2002, Prof. Nguyen went onleave from the University of Michiganto join the Microsystems TechnologyOffice (MTO) of DARPA in Arlington,Virginia, where he served as a ProgramManager in MEMS technology. AtDARPA, from mid-2002 through 2005,Prof. Nguyen created and managed adiverse set of programs that includedMicroelectromechanical Systems(MEMS), Micro Power Generation(MPG), Chip-Scale Atomic Clock(CSAC), MEMS Exchange (MX), HarshEnvironment Robust MicromechanicalTechnology (HERMIT), Micro GasAnalyzers (MGA), Radio Isotope

Micropower Sources (RIMS), RF MEMSImprovement (RFMIP), Navigation-Grade Integrated Micro Gyroscopes(NGIMG), and Micro Cryogenic Coolers(MCC).

Dr. John Kitching received his BSc. inphysics from McGill University in 1990.He went on to obtain a MSc. And PhD.in Applied Physics from the CaliforniaInstitute of Technology in 1992 and1995, respectively. His thesis topic wasan investigation of amplitude and fre-quency noise properties of semiconductorlasers subjected to optical feedback. From1995 to 2003, he was with JILA/TheUniversity of Colorado and also held aguest-researcher appointment in theTime and Frequency Division at theNational Institute of Standards and Tech-nology, NIST. Since 2003, he has been aphysicist in the Time and FrequencyDivision at NIST. His research interestsinclude atomic clocks and frequencystandards, quantum interference effectsin atomic systems, and applications ofsemiconductor lasers to problems inatomic physics and frequency control.Most recently, he and his team pioneeredthe development of microfabricatedatomic devices for use as frequency refer-ences, magnetometers and other sensors.

He has received several awards includ-ing the 2005 EFTF European Young Sci-entist Award and the Department ofCommerce Silver Medal. He has pub-lished over 40 papers in refereed journals,has given numerous invited talks and hasbeen awarded two patents.

McNeill, Coln and Larivee Receive Lewis WinnerOutstanding Paper Award at ISSCC 2006John McNeill, Worcester Polytechnic Institute, [email protected]

John McNeill, Associate Professorof Electrical and Computer Engi-neering at Worcester Poly

technic Institute (WPI) andMichael Coln and Brian Larivee ofAnalog Devices (ADI) received theLewis Winner Award at the 2006ISSCC for their 2005 ISSCC paper “Asplit-ADC architecture for determinis-tic digital background calibration of a16b 1 MS/s ADC.”

Chip SummaryThe “split-ADC” architecture enablesthe use of a deterministic digital calibra-tion procedure that operates continuous-ly in the background and requires fewerthan 10,000 conversions to completecalibration. This architecture, demon-strated in a 16b, 1 MS/s algorithmicADC, is shown in the figure to the left.The analog sub-system of the ADC wasimplemented in 0.25 µm CMOS, con-

Architecture uses FPGA for digital cali-bration algorithm for ADC.



sumes 105 mW, and has a die size of 1.2X 1.4 mm2.

Dynamics of the ProjectAlthough this project started in the sum-mer of 2002, McNeill’s relationship withAnalog Devices began a decade earlier. Asa PhD student at Boston University from1991-1994, he worked with Larry DeVito’sPLL group to develop a theoretical frame-work for understanding jitter in ring oscil-lators and guiding design to meet specificnoise requirements; this work was pub-lished in the Journal of Solid-State Circuitsin 1997 (dx.doi.org/10.1109/4.585289).

When McNeill's turn for a sabbaticalleave from WPI came up in the 2002-3 aca-demic year, he contacted DeVito and askedif he knew of any good problems to work onat ADI. At the same time, Mike Coln inADI's Precision Nyquist Converter Groupwas looking for a "breakthrough" in ADCdesign: an innovative architecture thatwould explicitly take advantage of CMOSscaling by relaxing requirements on analogcircuitry and moving as much complexityas possible into the digital domain. Work-

ing in Coln's group at ADI, McNeill com-pleted the top-level architecture design inthe fall of 2002; circuit design and layoutwere completed by the fall of 2003. AsMcNeill returned to his teaching andresearch duties at WPI in 2003, Brian Lar-ivee carried out the process of integratingthe analog test chip with the FPGA imple-menting the digital calibration algorithm.The test and evaluation process was com-pleted in time to submit the paper forISSCC in September 2004.

The collaborative relationship betweenWPI and Analog Devices is continuing inresearch toward applying the split ADCconcept to other types of ADCs. In addi-tion to funding from ADI for this work,McNeill was also awarded a grant fromNSF in 2005 to support further research.

John McNeill joined the ECE faculty atWPI in 1994. Since 1998, he has beendirector of the Center for Analog and MixedSignal Integrated Circuit Design at WPI,(http://ece.wpi.edu/analog/center.html), aconsortium of industry sponsors supportingundergraduate projects and graduateresearch in the area of analog and mixed sig-

nal integrated circuit design. In 1999 hereceived the WPI Trustees’ Award for Out-standing Teaching. He received an A.B.from Dartmouth College in 1983, an M.S.from the University of Rochester in 1991,and a Ph.D. from Boston University in1994. From 1983 to 1990 he worked inindustry in the design of high speed, highresolution analog-to-digital convertersand low noise interface electronics used inhigh speed, wide dynamic range imagingsystems.

Mike Coln joined Analog Devices in1988, after earning a PhD from MIT. Sincethen, he has been involved in design, lead-ership, and mentoring roles, contributingto all areas of precision data converterdevelopment within the company. A hold-er of 12 patents, Coln was the chief archi-tect of ADI’s PulSAR® analog-to-digital-converter (ADC) family, which overcameperceived architectural barriers then box-ing-in the specifications of speed, resolu-tion, power consumption, and size of suc-cessive-approximation converters. The Pul-SAR self-calibrating architecture was thefirst to enable 16-bit ADCs to reachthroughput of 1 Msps (million samples persecond), and it resulted in the first SARADC to reach 18-bit resolution. In 2005,Coln was named an Analog Devices Fellow,the highest level of achievement for a tech-nical contributor at Analog Devices, Inc..

Brian Larivee has been working forAnalog Devices since 2003 as a designengineer for the Precision Nyquist Con-verters group. He received the BSEE andMSEE degrees from the University ofMichigan in May 2002 and December2002, respectively. His developmentinterests are in the areas of Nyquist-rateconverter design and low-power analogintegrated circuit design techniques.

From left, Tim Tredwell, ISSCC Executive Chair, Brian Larivee, Dr. Michael Coln, Dr.John McNeill.

JSSC CD to Change to DVD: The End of an EraCD of JSSC, 20th Issue Will Be The Last

The annual CD containing theprevious two years of the Jour-nal of Solid-State Circuits arti-

cles will be issued in June 2006 andmailed to subscribers. It provides 2004and 2005 Journal articles in pdf for-mat. For those who didn’t subscribeto the CD, a separate purchase can beentered through the IEEE Store.shop.ieee.org/ieeestore/product.aspx?p

roduct_no=JD3755D The memberprice is $150.

The CD will be replaced by the SSCSArchival DVD. Since 2001, SSCS hasissued a complete archival DVD, whichincludes all the articles of the IEEE Jour-nal of Solid-State Circuits from the firstissue through 2005, plus completedigests from four conferences: Three arecomplete from their beginnings through

2005 (ISSCC, Custom Integrated Cir-cuits Conference and the Symposium onVLSI Circuits), while the Proceedings ofEuropean Solid-State Circuits Conference(ESSIRC) covers 1997 through 2005. Allare full-text searchable with ASTAwaresearch engine provided on the disk.

Starting in 2007, the DVD willreplace the annual CD update and canbe obtained beginning with the 2007



member renewal cycle. Purchasing theDVD as a subscription during renewalwill result in receiving it as soon as theproduct is manufactured in early Feb-ruary.

The JSSC is the best archive of tech-nology advances in integrated circuits,

with original research and expandedarticles based on outstanding presenta-tions from premier conferences. Onceagain in 2005 the Journal tops the list ofmost downloaded articles out of 193technical publications in Xplore. JSSChas been readers’ top choice since Xplore

began keeping download counts fouryears ago. 38% more JSSC articles aredownloaded than the next most popularjournal. More than 10 times the numberof JSSC articles are downloaded than foreach of 137 other transactions and mag-azines hosted online by IEEE.

ISSCC 2006 Panel on Classic CircuitsAn ISSCC 2006 Evening Panel

Un-Ku Moon and K. Nagaraj, SSCS AdCom Members, [email protected], [email protected]

In a packed standing room only ses-sion, moderator Bill Redman-Whiteopened the “Present (and Future)

Classic Circuits with Less than 25 Tran-sistors” evening panel by asking the ques-tion “what makes a real classic circuit?”While the audience quietly mulled overtheir own favorites and possibilities, thenumber 25 was quickly forgotten by thepanel members.

Barrie Gilbert pulled out probablythe most interesting item. He provid-ed the silver lining by not only pre-senting the best circuit of the evening(below, left), but also by making it col-orful and humorous with the KERMITterminology. Who would rememberwhat it stood for, other than it had todo with something KERMultITan?We certainly enjoyed being remindedof the power of what just a few bipolartransistors can do.

Tom Lee was funny and entertainingas always and presented “the Rodney

Dangerfield of circuits” (biasing: theynever get any respect), which we felt wasthe second best circuit in the eveningpanel.

Other panelists presented Class ABoutput stage (Klaas Bult), linear V-I con-verter (Takahiro Miki), “infinite gain” viapositive feedback stages (Bob Dobkin),and companding integrator (Yannis Tsi-vidis, shown below, right). We went tothe panel looking for gems, and ended upa little disappointed, wondering why noone talked about something as basic andpowerful as a two stage amplifier or afolded cascode amplifier.

Then the evening panel kicked into asecond round of what effectively endedup being a contest of “circuits with as fewtransistors as possible”. Perhaps weshould thank Scott Wurcer for launchingthis contest with a single JFET-resistorcombination constant current source.These lighter moments of the secondround are what the audience is likely to

remember and have enjoyed the most.Barrie Gilbert’s talking about what onecan do with just a single diode later led toYannis Tsividis poking fun at BarrieGilbert’s one diode circuit also needing asupply, a current source, and switches.His tongue in cheek accusation of BarrieGilbert’s one diode circuit needing aswitched-capacitor signal processing sys-tem for it to work was clearly enjoyed bythe audience as well as Barrie Gilbert.Yannis Tsividis’s own truly single transis-tor amplifier based on MOS channel par-asitic RC was fun, but obviously notpractical.

The element of controversy that canmake for a spicy panel was missing, butthe friendly competition of single-tran-sistor circuits and routine teasing amongthe panel members made up for whatotherwise may have been an ordinary ses-sion. The audience was entertained andwill certainly remember that one applica-tion-free single transistor amplifier.

Best circuit of the evening, presented by Barrie Gilbert. Companding integrator, presented by Yannis Tsividis.



CHAPTERS

Special Chapter EventsSSCS Extra Subsidies Support Meetings in Central Texas and Taipei

SSCS chapters are eligible forextra subsidies to support eventssuch as workshops and mini-con-

ferences that are not financed by theannual Chapter Subsidy. In 2006,these two IC events are being support-ed, as well as the IEEE Siberian Sec-tion Congress to take place at the endof July:

Austin Conference on IntegratedSystems & CircuitsInaugural Meeting on 17-19 May 2006By Mike Seningen, CTS CAS/SSC JointChair

Austin, the Silicon Hills of the USA, isa hotbed of electronic design, withmost of the world's major companiessituated in or around the immediatearea. The Austin Conference on Inte-grated Circuits promises to bringtogether people with a mutual interestin presenting, learning, and debatingthe hot issues facing the semiconduc-tor industry in a forum for the dissem-ination of technical information andthe advances in electronic technologyat chip, board and system levels, cover-ing design, CAD methodology, andtest. The meeting is sponsored by theUT Electrical Computer EngineeringDepartment and the Austin TechnicalCouncil.

Jeffrey Scott, who co-founded SiliconLaboratories in August 1996 and servedas Vice President of Engineering and asa Director from the company’s inceptionto 2003, will deliver the keynoteaddress. Mr. Scott holds a B.S. in electri-cal engineering from Lehigh Universityand an M.S. in electrical engineeringfrom the Massachusetts Institute ofTechnology. Possible titles for hiskeynote are: “Where Will Chips beDesigned in 2010” or “How is Semicon-ductor spelled in Chinese?”

More information may be found atthe conference website: www.acisc.org.

Short Course on High-speedLink DesignBy The IEEE SSCS Taipei Chapter

With the Extra Chapter Subsidy fromthe IEEE Solid-State Circuits Society,the Taipei Chapter successfully orga-nized a two-day short course event inFebruary, 2006 entitled “EfficientHigh-speed Link Designs: Challenges,Solutions, and Future Directions.” Theinvited speaker was Prof. Gu-Yeon Weiof the Electrical Engineering Depart-ment, Harvard University.

The short course consisted of twoone-day lectures held in Hsinchu andTaipei on February 23 and 24, respec-tively. This course attracted approxi-

mately 60 attendees in Hsinchu, and 50attendees in Taipei.

Hsinchu is the epicenter of Taiwan’ssemiconductor industry, with many ICdesign companies established in theHsinchu Science Park. As a result, pro-fessional engineers were the majority atthe Hsinchu lecture. Some attendeesfrom central Taiwan even drove morethan two hours to attend the course.The audience at the Taipei lecture camefrom various Universities and researchinstitutes.

Both lectures started at 10 o’clock inthe morning and ended at 4:30 PM, witha lunch break at noon. After an introduc-tory overview of the high-speed linkdesign fundamentals, Prof. Wei went onto talk about the challenges of efficienthigh-speed link designs. In particular, hefocused on the design methodologies ofequalization and adaptation, anddescribed several circuit and systemarchitectures to address these design chal-lenges. In the last part of his lecture, Prof.Wei shared his views on future researchtrends in high-speed link design. Theengineers and students who raised ques-tions about high-speed link design in theQ&A sessions at the end obtainedinsightful feedback from the speaker.This short course was well-received.Many attendees considered its contentvaluable to their research and work.

Photo taken after the lecture in National Taiwan University,Taipei. From left to right: Prof. Tsung-Hsien Lin, Prof. Gu-Yeon Wei, Prof. Shen-Iuan Liu (Chair of the IEEE SSCS TaipeiChapter), Prof. Hen-Wai Tsao, and Prof. Yi-Jan Chen.

Prof. Wei lecturing at National Chiao-Tung University, Hsinchu.



Rebirth of the Benelux ChapterChandrakasan Speaks on Design of Ultra-Low Power Systems

Jan Craninckx, Chapter Chair, [email protected]

On March 24th, the SSCSBenelux chapter invited Prof.Anantha Chandrakasan to speak

about the ultra-low power systems workby his group in the Microsystems Tech-nology Lab at the Massachusetts Instituteof Technology. His talk covered a lot ofexciting results obtained with sub-threshold operation of digital circuitsthat dramatically reduce the power dissi-pation of digital integrated circuits.Also, system-level techniques for powerreduction with fine-grain power gatingand ultra-dynamic voltage scaling wereshown, as well as a 3-D integration tech-nique for FPGAs that increases the con-nection density and hence its power.

Abstract:Energy efficiency is a key design con-sideration in wireless systems. Energyefficient system design requires system-atic optimization at all levels of thedesign abstraction ranging from processtechnology and logic design to archi-tectures, algorithms and networking.The energy expended per operationcontinues to improve as the power sup-ply voltages are scaled. Sub-thresholdcircuit design provides a major oppor-tunity to dramatically reduce the powerdissipation of digital integrated cir-

cuits. The opportunities and challengesassociated with sub-threshold designwill be presented. Idle-mode power(i.e., leakage) must also be carefullymanaged in sub-90nm CMOS and willrequire the use of techniques such asfine-grain power gating and ultra-dynamic voltage scaling. 3-D integra-tion also presents an interesting oppor-tunity for power savings - the potentialpower savings of this technology will bepresented for a 3-D FPGA circuit. Spe-cific examples of power management inintegrated circuits will be presented,focusing on wireless sensor networksand impulse based ultra-widebandcommunications as drivers.

Prof. Chandrakasan is an SSCS Distin-guished Lecturer. His biography may befound in the SSCS News of March 2006www.ieee.org/portal/pages/sscs/06Mar/DL_Program.html.

This event was the first held by thenew chapter chair, Jan Craninckx(IMEC, Belgium). "I want to thank theprevious chair, Raf Roovers (Philips,the Netherlands), for the work he hasdone in the past, and we appreciate thefact that he will stay active in the futureto help us revitalize the chapter. TheBenelux area has always been very suc-cessful in solid-state circuits. There are

very good universities (KU Leuven, TUDelft, TU Eindhoven, TU Twente, etc.)that provide an excellent education fornew electrical engineers and obtain veryhigh quality research results from theirPhD students, which are presentedevery year at all major conferences(ISSCC, ESSCIRC, CICC, etc.). Theinter-university research instituteIMEC, with its new 300mm fab, is aworld-class technology research organi-zation with major achievements inadvanced digital and analog design.Amongst the large number of compa-nies present in the area, AMI Semicon-ductor in Belgium and of course Philipsin the Netherlands are the best known."

Invitation to VolunteerSince so many excellent engineers workin Benelux, the SSCS Benelux chapterlooks forward to becoming a vibrantforum where people meet each otherand exchange ideas. Having volunteerson the team from a broad background,including Belgium and the Nether-lands, industry and academics, willallow us to achieve this goal. The chap-ter extends an invitation to all whowould like to help. People interestedcan contact me at "Craninckx Jan"[email protected]

From left, Hugo Deman (KUL/IMEC,Prof. Chandrakasan, Jan Craninckx

Dr. Chandrakasan addressing the SSCS Benelux chapter on 24 March, 2006.



CONFERENCES

2006 Symposium on VLSI Circuits to Emphasize SevenDesign AreasMeeting in Hawaii on 15-17 June Will Overlap the VLSI Technology Symposium

The 2006 Symposium on VLSI Cir-cuits, meeting on 15-17 June,2006 at the Hilton Hawaiian Vil-

lage in Honolulu, Hawaii and the VLSITechnology Symposium, at the same hotelon 13-15 June, enable technologists andcircuit and system designers from aroundthe world to interact and exchangeideas.The close affiliation of these twoconferences, a tradition since 1987, givesattendees "a unique opportunity to spanthe entire VLSI discipline," says BruceGieseke, 2006 Symposium Chair. "TheSymposium is full of rich and excitingpapers."

After two full-day tutorial courses on14 June, this year's Circuits Symposiumprogram will focus on seven topic areas:

Wireless CommunicationFive sessions on RF integrated circuitsfor wireless communications willinclude Cellular, WLAN, UWB, Satel-lite/Mobile Broadcasting and Radarapplications. The presentations willcover a broad range of wireless systemchip and building block designs, rang-ing in operation frequency from 400 to800 MHz in the case of a DVB-H tunerall the way to 182Ghz in the case of amillimeter wave Schottky diode detec-tor. Circuit design techniques usingboth low-voltage standard CMOS tech-nologies and high performance SiGeBiCMOS technologies will be discussed.

Opportunities and challenges for RFintegrated circuit designs continue toarise as new technologies and wirelessstandards emerge. Sharp Corporationwill present a direct conversion DVB-HTuner operating from 400 to 800 MHz,with 184mW power consumption, real-ized in a 0.5um SiGe BiCMOS technol-ogy. The IC includes a distortion com-pensated variable-gain low- noise ampli-fier and an offset cancellation loop forthe base-band section. Several contribu-tions explore the realization of millime-

ter wave integrated circuits in CMOStechnology. Researchers from the Uni-versity of Florida will present a 24GHztransmitter with on-chip antenna and a182GHz Schottky diode detector. Ateam from National Taiwan Universitywill discuss a 40GHz voltage-controlledoscillator and a 50GHz distributedamplifier. The University of Californiaat Los Angeles will contribute a 60GHzCMOS receiver.

In addition to the emerging applica-tions, advances continue for cellular,WLAN, UWB connectivity and for RFbuilding blocks. Columbia Universitywill present a 0.5V 900MHz CMOSreceiver that demonstrates the criticalRF front-end blocks operating from anultra-low supply voltage. The Universi-ty of California at Berkeley will discussan EDGE RF transmitter using Carte-sian feedback implemented in CMOSwhich overcomes some of the obstaclestowards a true single chip phone realiza-tion. Intel Corporation will present amulti-band discrete-time receiverimplemented in a 90nm digital CMOSprocess. The UWB session includesboth MB-OFDM and pulse-based RFtransceiver designs. Finally, recentadvances in oscillator and dividerdesigns will also be presented at thesymposium.

Data Converters and AnalogTechniquesThe ever-increasing importance of dataconverters is reflected by this year'sSymposium program, which will startwith a data converter short course and aplenary talk on the future roles of dataconverters, followed by four sessions inthe areas of Nyquist ADCs, over-sam-pled ADCs, and data converter tech-niques for embedded systems.

A 500MS/s 5b ADC is one of the firstADCs in 65nm to be presented byresearchers from MIT, which describes a

technique to reduce switching energyfor embedded UWB systems. Also thetrend continues towards wide band-width in over-sampled ADCs. Therewill be a full session on delta sigmaADCs where Hughes Research Labs willpresent a 1.4GHz IF band-pass modula-tor at a 4GHz sample rate.

1V (and below) analog design contin-ues to be an area of active interest andsignificant advancement in recent years.An example of such work will be pre-sented by Columbia University featur-ing a 0.5V track-and-hold circuitachieving 60dB SNDR. On the ADCfront, researchers from Shizuoka Univer-sity will present 1V 10-b 100MS/s ADCwith only 30mW power. The ADC fea-tures a low-power class-AB amplifier toachieve low steady-state current imple-mented in 90nm CMOS.

Other analog program includes papersessions on image sensors and real-worldinterfaces. CMOS image sensors willhave a dedicated session this year whereMicron will present the world's largestsingle die CMOS image sensor yielding4Kx4K pixels of 16 million pixels.

Multi-Gbps InterfacesThe demand for increased bandwidthhas resulted in the development of highspeed interfaces capable of driving dataacross long cables and channels as well asshort-haul links for memory-CPU com-munication in computers. Four techni-cal sessions address issues ranging fromclock generation techniques to equaliza-tion circuit design approaches and chan-nel effects.

As the drive to higher data rates con-tinues, equalization techniques arebecoming prevalent to combat channelloss and inter-symbol interference athigh frequencies. UCLA and IBM showa low power (5 mW at 6 Gbps) receiverfor short-haul applications. A soft deci-sion feedback equalization technique is



used instead of the conventional hard-decision (data slicer based on edge-trig-gered flip-flop) architecture to relax thecritical path, thus saving power.

Researchers from National TaiwanUniversity present a 38.5GHz clockgenerator that enables high speed trans-ceiver design. RMS jitter of 0.24ps at38GHz is achieved with 52 mW powerconsumption.

Performance and power of 1.6 to 9.6Gbps server, desktop, and mobile I/Olines in a 1.2 V 90nm CMOS process isanalyzed in a paper by Intel. They showthat a novel combination of voltage-modedriver (equalized or un-equalized) and RXequalizer delivers the lowest power(12.1mW/Gbps at 7.2Gbps), offering alow power option for short distance links.

Digital Circuit TechniquesAs logic technology is moving towards65 nm and below, on-die variations inthe electrical characteristics of transis-tors and interconnect are presenting dif-ficult challenges to circuit designers.

This year’s contributions in the areaof digital circuits focus on

• in-situ die monitoring for process andsupply and process variations, and

• power and leakage managementtechniques applied to a range ofentertainment, multimedia andcommunications processors.

An in-situ measurement scheme formapping supply-noise is describedwhich measures 69 mV local supplynoise with 5 ns time resolution in a 3Gcellular phone processor from Hitachi.

Many papers describe the use of paral-lel processors for attaining high compu-tational throughput. The circuits anddesign methodology of the massivelyparallel processor from Renesas is basedon a matrix architecture, which enhances

the performance of multiply-accumulateoperations up to 30 GOPS/W.

A paper from Keio University demon-strates low system power from applica-tion specific architecture optimization.By using a hardware accelerator coupledwith a programmable processor core, areal-time face detection core is achievedin 0.79mm2 Si using 0.13um CMOStechnology. It can detect 8 faces perframe at 30 fps, while consuming merely29mW at 1.2 V supply voltage.

SRAM for Ultra-deep submicrontechnologiesNine papers on next generation SRAMsfrom industry and academia will addresscritical issues related to SRAM cell sta-bility and architectural features at 65nm and beyond.

Two key papers are from IBM andIntel. The IBM paper describes a 32MbSRAM designed for 65 and 45 nm tech-nologies. It features read-and-write-assist circuit techniques that expand theoperating voltage range and improvemanufacturability across technology plat-forms. Intel’s paper describes a 16-wayset associated, single-port 16MB cachefor the dual-core Xeon processor using a0.624 um2 cell in a 65 nm 8-metal layertechnology. Sleep transistors are used inthe SRAM array. Techniques to protectthe cache from latent defects and infantmortality failures will be discussed.

Non-Volatile Memory Architec-ture and CircuitsThis year's non-volatile memory sessionwill cover two new flash memory archi-tectures as well as two new emergingtechnologies, including a 500 MHz SOCMRAM by NEC Corporation and a newCBRAM by Infineon Corporation. Whatis a CBRAM? Come to the VLSI Sympo-

sium memory session and learn about thisnew technology, as well other papers. Tofurther scale the NOR flash array, SharpCorporation will discuss its new contact-less virtual ground array architecture withan interesting 32 cell stack string.

Spansion will provide details abouttheir 1.8V 90nm 1Gb OrNAND flashmemory solution to the growing remov-able and embedded data market. Thispaper discusses their product and mem-ory architecture that was squeezed into81 mm2. Their paper will also discusshow this 2 bit/cell MirrorBit memory isable to achieve near regular NANDwrite rates of 3 to 11 MB/S.

Who says non-volatile memories areslow? NEC Corporation will presenttheir MRAM of capable of 500MHz andhigher on a 130nm CMOS/240nmMRAM SOC process. They will intro-duce two new MRAM cell architecturesable to achieved this very high speed per-formance as well as lower write current.

Evolving DRAM technologiesFor SOC (System-On-a-Chip) applica-tions, minimum operational voltage isbecoming very critical for DRAM’s. Allfour DRAM papers will report new cir-cuit techniques and technologies to meetlow operating voltage requirements.

Renesas will report a high perfor-mance TwinCell RAM technology inSOI process at 90nm.

Toshiba will report the first ever 6F^2128 Mb single transistor gain cell-basedhigh density RAM in SOI, which providesa bit yield of 99% and reduced power.

IBM will report a 3T DRAM cellwith a gated diode for enhanced speedand data retention time.

Further information can be found onthe Symposium web site: www.vlsisym-posium.org/index.html.

RFIC Symposium to LaunchMicrowave Week, 11-13 June, 2006Luciano Boglione, RFIC 2006 TPC Co-Chair, [email protected]

The RFIC (Radio Frequency Inte-grated Circuits) Symposium isrenowned as the foremost IEEE

technical conference dedicated to the lat-

est innovations in RFIC development ofwireless and wire line communicationICs. It is co-sponsored by SSCS.

This year's RFIC Symposium, on 11-

13 June at the Moscone Convention Cen-ter in San Francisco, will launchMicrowave Week 2006, the largestworld-wide RF/Microwave enclave of the



year. The IEEE MTT-S InternationalMicrowave Symposium (IMS) will coin-cide with RFIC, from 11-16 June, alongwith the 67th Automatic RF TechniquesGroup (ARFTG) Conference, whose spe-cialty is measurements, on 16 June. Morethan 1000 papers will be presented in all.

Plenary Session on Wireless andMobile Communications ICs andSystemsA plenary session on Sunday evening willkick off the formal technical program.This year, three distinguished speakerswill share their views on the future ofwireless and mobile communications ICsand systems: Mr. Stefan Wolff, Vice Pres-ident RF-Engines at Infineon Technolo-gies, Mr. Kent Heath, Director, CellularOperations, Radio Products Division, atFreescale Semiconductor, and Dr. Aro-gyaswami Paulraj, Founder and ChiefTechnology Officer at Beceem Communi-cations and Professor, Stanford University.

Plenary 1: "RF-Modems the RealApplication for RF CMOS"

Stefan WolffAs Vice President ofInfineon Technologies,Stefan Wolff overseesthe company's CellularRF Engine business unitand has been involved in

its RFIC business since the earlynineties. After beginning his career atthe Robert Bosch group as a RF engineerfor Mobile Phones, he joined SiemensSemiconductor, where he was responsiblefor the marketing of RF ICs. Prior tojoining Infineon, Mr. Wolff headed theSan Diego RF design centre of SiemensMobile Phones.

Abstract: Over the last decade, wire-less connectivity has become an integraland essential part of our lives. The plainmobile phone of the early nineties hasevolved into the mobile multimedia ter-minal as consumers demand cell phonesthat provide a comprehensive set ofadvanced features enabling voice, dataand video services. Handset manufactur-ers have to accommodate their productsto fast-changing market requirements.The semiconductor supplier has to pro-vide a cost effective and flexible platformthat enables handset manufacturers todifferentiate their products quickly

while maintaining a low-cost develop-ment effort.

The vast majority of today's cellphones require at least a multibandradio. In the near future, multimodemultiband 2G and 3G operation will bea part of main stream products includingwireless LAN, Bluetooth®, GPS andDVB-H as well. Infineon Technologieshas focused its RF expertise on providingthe next wave of highly integrated, highperformance and easy to use RF CMOSradio subsystems. Infineon Technologiesdemonstrates the maturity of RF CMOSwith respect to RF performance by pro-ducing e.g. a six-band WCDMA /UMTS transceiver; the RF CMOS capa-bility enabled the world’s first singlechip cell phone: EGold-Radio. RF-modems will be the next leap in integra-tion. These RF-SoCs will simplify thehandset development process by separat-ing radio hardware and the protocolstack from the application layer.

Plenary 2: "Architectural Implica-tions of Multimode, MultibandCellular Radios"

Kent HeathKent Heath joinedFreescale Semiconduc-tor in March, 2004 asdirector of the AnalogCellular IC businessunit, where he is

responsible for power management anduser interface ICs, RF transceivers, poweramplifiers, RF subsystems and DVB-Hcomponents targeted for the cellularhandset market. Prior to joiningFreescale, he was senior director of strat-egy and business development for the RFSolutions Division at Skyworks Semicon-ductor. From 1997-2000, he was directorof Motorola Semiconductor's WirelessSubscriber Systems Group (WSSG,Japan) after previous engineering man-agement positions at Xerox, GeniscoTechnology, and LectroMagnetics Inc.Mr. Heath is a BSEE and MBA graduateof Southern Methodist University inDallas. He belongs to the SemiconductorIndustry Association in Japan (SIAJ) andthe Society of Mechanical Engineers(SME), and has been an active member ofthe IEEE for over 20 years.

Abstract: This talk explains howcombinations of System-on-Chip(SoC)-

and System-in-Package(SiP)-level inte-gration may be employed to meet theaccelerating cost and size reduction needsof OEMs and carriers. These technologiesexemplify trends toward high levels ofintegration and multiple radio technolo-gies in a single RF lineup.

Solutions to the challenge of inte-grating multiple radio technologies ina single RF chip range from elaborateIII-V technologies to SiGe-basedmethodologies, BiCMOS nodes andRFCMOS-based solutions. Some ofthese technologies are single-chipsolutions, while others are combina-tional approaches using various plat-forms for SiP-level integration. Thistalk addresses the various approachesavailable and the potential implica-tions to the mobile communicationsindustry.

Plenary 3: "Multiple Antenna Tech-nology in Mobile Broadband -New Challenges for RF Designers"

Dr. ArogyaswamiPaulrajDr. Arogyaswami Paulrajsupervises the StanfordUniversity Smart Anten-nas Research Group,working on applications

of space-time wireless communications.The many key fundamentals he has devel-oped have drawn research attention to thisnew field. Dr. Paulraj has won severalawards for his engineering and research con-tributions, most recently the IEEE SP Soci-ety Technical Achievement Award 2003.He is the author of over 300 research papersand a textbook on wireless communica-tions. He also holds 24 patents. Dr. Paulrajis a Fellow of the IEEE and a Member of theIndian National Academy of Engineering.

Abstract: Multiple antenna wirelesshas emerged as a key technology thatsignificantly improves coverage andthroughput. Multiple input - multipleoutput (MIMO) is a configuration thatuses multiple antennas at both ends ofthe link. This talk on MIMO in mobilebroadband begins with a survey ofmobile broadband applications, marketsand standards with special reference tomultiple antenna technology. It describesthe typical design of a next generationmobile broadband system that usesMIMO-OFDMA and highlight design



areas that are impacted by MIMO andquantifies the performance enhancementoffered by multiple antennas in mobilebroadband. Finally, it describes the RFdesign challenges related to multipleantennas at both terminals and base sta-tions, and addresses mutual coupling andits impact on RF performance, transmit-receive RF calibration necessary for thetransmitter to learn the channel, RFpower drain and power managementachieved by controlling the number ofactive RF chains, and PAPR reduction. Asurvey of emerging multiple antenna RFproducts concludes the talk.

Sunday Evening ReceptionThe RFIC reception begins immediatelyafter the plenary, making Sundayevening a highlight of both technical

activities and social festivities. Thishighly attended, enjoyable social eventallows attendees to meet with oldfriends, discuss the latest events in theRFIC field and interact with profession-als in the wireless community.

Technical ProgramThe RFIC technical program starts onSunday with tutorials and workshopsfocused on RF technology, design andsystems, and continues on Monday andTuesday with paper presentations, panelsessions and an interactive forum.

The panel sessions at lunch time arealways captivating. On Monday, one dis-tinguished group of panelists will discussthe subject “4G: Do We Really Need 1Gbits/s?” and another distinguished setof panelists will debate “SoC vs. SiP:

Dollars & Sense” on Tuesday.The interactive forum on Tuesday

afternoon is an excellent opportunity forattendees to meet authors face to face todiscuss their presentations in detail.

If you are not sure about investingtime and money to attend the RFIC, askany professional or academic: They willconfirm to you that this is the conferenceto attend in the area of RF integrated cir-cuits. See you in San Francisco, June11th, 2006!

For more information, see the RFIC web-site, www.rfic2006.org., the IEEE MTT-SInternational Microwave Symposium (IMS)website www.ims2006.org/ims2006_tech-program.htm, and the 67th Automatic RFTechniques Group (ARFTG) Conferencewebsite, (www.arftg.org/#Upcoming%20Events).

DAC Receives Record 1,007 Submissions43rd Conference to Meet in San Francisco, 24-28 July 2006

The Design Automation Confer-ence received 864 technicalpaper proposals, 13 tutorial pro-

posals, 78 panel submissions and 52student contest designs for its 43rdannual meeting at the Moscone Centerin San Francisco, according to a pressrelease this January. DAC is the premierforum for the electronics industry’s“hottest trends,” it said, with atten-dance regularly exceeding 10,000developers, designers, researchers, man-agers and engineers from leading elec-tronics companies and universitiesaround the world.

“Hot Areas” are System-LevelDesign, DFM and PowerSystem-level design, Design-for-Man-ufacturability (DFM), and power arethe “hot areas” in this year’s submis-sion pool, said Ellen Sentovich, DACGeneral Chair, due to the fact thatconsumer electronics and computerapplications continue to drive theindustry, along with “still-increasingtime-to-market pressures that implythe need for advances in designingfaster, denser chips, for reducingpower consumption, and for tapingout quickly:”

System-Level ProgressDiscussions about the best tools thatallow designers to work at a level aboveRTL will speak to questions about

• resolving language/standards con-troversies

• unifying disparate, often comple-mentary approaches

• emergence of a global vision.

DFMPapers on integrated flows and enable-ments that bridge the gap betweendesign and manufacture for the cost-effective continuation of Moore’s Lawbeyond the 65 nm. node will point tocollaboration among the electronic

design automation (EDA) and semicon-ductor industries and suppliers.

Power ChallengesThe increasing use of dynamic analysisand tools for tackling all levels of design,from voltage blocks at the architecturallevel to leakage control for high-speedparts, will be important developments towatch at the conference.

Beyond the Die Integration Packaging“In the last few years,” said Grant Martinand Sachin Sapatnekar, co-chairs of thisyear’s TPC, “we have seen a growing needfor advanced design technologies to solveproblems at the package, hybrid, board,and whole-system levels” and “a growingresponse” to this need with “new tools andmethods, including co-design approachesbetween all levels of design integration.”As a result, the DAC program will include“beyond-the-die” integration packaging --chip-package co-design, system-in-pack-age (SIP), new integration techniques,such as 3D and stacked designs, and every-thing in the design area that goes beyondthe die-design, simulation, physical lay-out, and analysis and optimization at thepackage, hybrid board, backplane, rackand whole-system levels.



Theme Day to Focus on Entertainment, Games andMultimediaWednesday’s program on 26 July willaddress “the growing convergence ofentertainments platforms for gaming andthe digital home, the continued role ofgraphics processors as key EDA industrydrivers and San Francisco’s hotbed of soft-ware and content development,” said Ms.Sentovich.

Start-Up ExhibitorsStart-up companies will represent newdevelopments in analog, verification, sys-tem-level IC design, and DFM.

Annual Student Design ContestJointly sponsored by the Design Automa-tion Conference (DAC) and the Interna-tional Solid State Circuits Conference(ISSCC), the prestigious DAC StudentDesign Contest has been co-chaired for sev-eral years by Bill Bowhill, Senior PrincipalEngineer, Intel Massachusetts, and AlanMantooth, Professor of Electrical Engineer-ing at the University of Arkansas. The totalprize money this year is expected to beclose to $15,000, shared between the first,second and third place winners. They willreceive travel assistance to attend the meet-ing, where their winning submissions willbe displayed as posters at the DAC Univer-

sity Booth on the exhibit floor. They willalso have the opportunity to present theirwork at a special poster session at ISSCC2007. “The DAC/ISSCC Student DesignContest is unique in the industry for theopportunities it offers to its winners andsponsors,” said Mantooth. “The contestprovides competition between graduateand undergraduate students at universitiesand colleges worldwide, while also givingthem a chance to demonstrate their experi-ence to sponsor company representativeswho serve as judges.”

More information about DAC 2006may be found at the conference website:www.dac.com.

The second annual Organic Micro-electronics Workshop will takeplace in downtown Toronto on 9-

12 July, 2006. It is an unusual interdisci-plinary conference, established by theAmerican Chemical Society (ACS), theIEEE Components Packaging and Manu-facturing Technology Society (CPMT)and the Materials Research Society tobring the communities into lively discus-sion across boundaries. Invited speakersare from around the globe, and representboth industrial and academic communi-ties, with heavy representation from com-panies trying to develop commerciallyattractive devices.

Organic microelectronics, a topic ofgreat interest for over a decade, comprisesboth fundamental properties and applica-tions for technology. The Workshopemphasizes applications for technology.This year’s papers will span theoretical,materials, interface analysis, device fabri-cation, and commercialization issues.

The five-session technical programwill focus on organic transistors, LEDs,and photovoltaics. Posters will be pre-sented after the Monday and Tuesdayafternoon sessions.

TFT Circuits Monday, 10 July, a.m.TFT – Printing Monday, 10 July, p.m.Materials Tuesday, 11 July, a.m.Photovoltaics Tuesday, 11 July, p.m.OLED/TFT for Wednesday, 12 July,

Displays a.m. and p.m.

TFT Circuits and PrintingTwo of the sessions making up a full dayare devoted to thin film transistor circuitsand printing. Applications here includebackplanes for displays that may be basedon electrophoretic or liquid crystal technol-ogy. Organic based RFIDs are an attractivepossibility. RFID technology is becoming

widespread and many are interested in lowcost “chips” that can be cheaply printed onvarious packaging materials.

MaterialsThe development of new materials is a crit-ical aspect. Included are both small mole-cule materials and various polymers. Thelatter may be useful for their semiconduc-tor properties or as emissive materials inorganic light emitting displays (OLEDs).Displays are covered for both aspects inaddition to the discussion of materials.

PhotovoltaicsLow cost photovoltaics are under investi-gation, especially for portable electronicsvia solution deposition processes and theyare discussed in one session.

Finally, a few talks are intended toraise “real world” issues, and perhaps stircontroversy, by addressing competingtechnologies. Ample time is set aside fordiscussion and posters are invited. Thereare no evening sessions so that attendeescan enjoy the attractions of Toronto.

More information may be found at theWorkshop website: www.organicmicro-electronics.org

SSCS Sponsors 2nd Annual Organic MicroelectronicsWorkshop 23 Invited Papers Focus on TFT Circuits and Printing, Photovoltaics and OLED/TFT for Displays

Ed Chandross ([email protected]), Ananth Dodabalapur ([email protected]) & Shelby Nelson ([email protected]), Technical Chairs



You want to be at theIEEE Bipolar/BiCMOSCircuits and Technology

Meeting 2006 (BCTM) if you'reinterested in leading edgeprocesses, devices, and circuitsused in state-of-the-art telecomand power control systems.Bipolar/BiCMOS technologies,particularly SiGe HBT BiCMOS, play akey role in these systems.

We are extremely fortunate this yearto have the 2000 Nobel Prize winner inPhysics, Dr. Zhores Alferov (photo, left)as our keynote speaker. Dr. Alferovreceived the Nobel prize for “DevelopingSemiconductor Heterostructures Used In

High-Speed And Optoelectron-ics.” Don’t miss this opportuni-ty to hear Dr. Zhores describehis historic contribution tosemiconductor devices and tech-nology in the keynote address.

The conference begins with ashort course on Sunday, October8, followed by two full days of

contributed and invited papers.Exhibitors offering key technologies rel-evant to the BCTM community will bepresent for the entire conference. Theannual Workshop on Compact DeviceModeling for RF/Microwave Applica-tions organized by TU-Delft follows theconference on Wednesday.

The 2006 BCTM short course is ded-icated to on-chip Passive Componenttechnologies and features three renownedexperts.

Achim Burghartz from IMS Stuttgartwill present an overview of RF passiveson silicon.

G.P. Li from UC Irvine will address MEMSfor wireless and biomedical applications.

Youri Tretiakov from RFMD will pre-sent passive device design, modeling andmeasurement (including packaging effects).

The invited papers include a fullmorning session on Emerging Technolo-gies, featuring the latest in new andspeculative devices and materials.

See you in Maastricht this Fall!

2006 IEEE Bipolar/BiCMOS Circuits and TechnologyMeeting (BCTM) in Maastricht, the Netherlands, 8-10October Nobel Prize Winner Dr. Zhores Alferov to Deliver Keynote Address

John Long, BCTM General Chair, [email protected]

SSCS Digital Archive DVD Set



445 Hoes Lane Piscataway, NJ 08854

SSCS SPONSORED MEETINGS2006 Symposium on VLSI Circuitswww.vlsisymposium.org15–17 June, 2006Honolulu, HawaiiPaper deadline: passed Contact: Phyllis Mahoney, [email protected] Business Center for Academic Societies,Japan, [email protected]

2006 (CICC) Custom Integrated Circuits Conferencewww.ieee-cicc.org10–13 September, 2006San Jose, CA, USAPaper deadline: passedContact: Melissa Widerkehr, [email protected]

2006 (A-SSCC) Asia Solid-State Circuits Conferencewww.a-sscc.org13–15 November, 2006Hangzhou, Zhejiang Province, ChinaPaper deadline: 5 June 2006Contact: [email protected]

2007 (ISSCC) International Solid-StateCircuits Conferencewww.isscc.org11– 15 February, 2006 San Francisco Marriott Hotel, San Francisco, CA, USAPaper deadline: 15 September 2006Contact: Courtesy Associates, [email protected]

SSCS PROVIDES TECHNICAL CO-SPONSORSHIP 2006 Radio Frequency Integrated Circuits Symposium www.rfic2006.org11–13 June, 2006San Francisco, CA, USAPaper deadline: passed

2006 Symposium on VLSI Technology www.vlsisymposium.org13–15 June, 2006 Honolulu, HawaiiPaper deadline: passed

2006 Design Automation Conferencewww.dac.com24–28 July, 2006San Francisco, CA, USAPaper deadline: passed

2006 European Solid-State CircuitsConferencewww.esscirc2006.org/18–22 September, 2006Montreux, SwitzerlandPaper deadline: passed

2006 International Symposium on Low-Power Electronic Deviceswww.islped.org4–6 October, 2006Tegernsee, GermanyPaper deadline: passed

2006 Bipolar/BiCMOS Circuits andTechnology Meetingwww.ieee-bctm.org9–10 October, 2006Maastricht, NetherlandsPaper deadline: passed

2006 International Conference on Computer Aided Design www.iccad.com/future.html 5–9 November, 2006San Jose, CA, USA Paper deadline: passed

2006 Compound Semiconductor ICConferencewww.csics.org/12 – 15 November, 2006San Antonio TX Paper deadline: 15 May 2006

2007 International Conference on VLSIDesign www.vlsiconference.com/

3–7 January, 2007Bangalore, IndiaPaper deadline: TBD

2007 Design, Automation and Test in Europewww.date-conference.com/conference/next.htm16–20 April, 2007Acropolis, Nice, FrancePaper deadline: TBD

SSCS EVENTS CALENDARAlso posted on www.sscs.org/meetings

IEEE SOLID-STATE CIRCUITS SOCIETY NEWSLETTER is published three times per year, January, May,and September by the Solid-State Circuits Society of The Institute of Electrical and Electronics Engineers,Inc. Headquarters: 3 Park Avenue, 17th Floor, New York, NY 10016-5997. $1 per member per year(included in society fee) for each member of the Solid-State Circuits Society. This newsletter is printed inthe U.S.A. Postmaster: Send address changes to IEEE Solid-State Circuits Society Newsletter, IEEE, 445Hoes Lane, Piscataway, NJ 08854. ©2006 IEEE. Permission to copy without fee all or part of any materi-al without a copyright notice is granted provided that the copies are not made or distributed for directcommercial advantage and the title of publication and its date appear on each copy. To copy materialwith a copyright notice requires specific permission. Please direct all inquiries or requests to IEEE Copy-rights Manager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. Tel: +1 732 562 3966.

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Frank Chang Recognized for Modern Cell Phone Technology ...sscs.ieee.org/images/files/newsletter_archive/sscs_newsletter_200605.pdf · Frank Chang Recognized for Modern Cell Phone