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Finite State Machines using HDL
● Here we will learn:
– What is a FSM
– What are the major types of FSM
– How to represent a FSM
– Writing RTL of FSM in Verilog
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Each transition edge is labeledwith the value of the input
(shown in red) and the value of
the output (shown in blue).
The machine starts in state Si.
In this example, the output isthe exclusive-or of the two
most-recent input values; thus,
the machine implements an
edge detector, outputting a one
every time the input flips and azero otherwise. More complex
Mealy machines can have
multiple inputs as well as
multiple outputs.
State diagram for a simple Mealy machine with
one input and one output
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Input values are in red;
output values are in blue.
The machine starts in state
Si. In this example, the
output is the XOR of the
two most-recent inputvalues; thus, the machine
implements an edge
detector, outputting a one
every time the input flips
and a zero otherwise. Morecomplex Moore machines
can have multiple inputs as
well as multiple outputs.
State diagram for a simple Moore machine with
one input and one output
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module evenOdd(o1, i1, clk, rst);
// Declare unique states
parameter s1 = 0;
parameter s2 = 1;
// Input/Output declarations
output o1;
input i1;
input clk, rst;
reg o1;
// Declare the state variable
reg state;
// Body of the FSM
….
….
endmodule
// Body of the Moore FSM
always @(posedge clk ) begin
// Reset logic
if (rst) begin
state <= s1;
o1 <= 0;end
// State transition and output logic
else begin
case (state)
// 'Even' state
s1: begin
// Output logic
o1 <= 0;
// State transition logic
if (i1) begin
state <= s2;
end
end
// 'Odd' state
s2: begin
// Output logic
o1 <= 1; // State transition logic
if (i1) begin
state <= s1;
end
end
endcase
end
end
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module evenOdd(o1, i1, clk, rst);
// Declare unique states
parameter s1 = 0;
parameter s2 = 1;
// Input/Output declarations
output o1;
input i1;
input clk, rst;
reg o1;
// Declare the state variable
reg state;
// Body of the FSM
….
….
endmodule
// Body of the Mealy FSM
always @(posedge clk ) begin
// Reset logic
if (rst) begin
state <= s1;
o1 <= 0;end
// State transition and output logic
else begin
case (state)
// 'Even' state
s1: begin
if (i1) begin
// Output logic
o1 <= 1;
// State transition logic
state <= s2;
end
end
// 'Odd' state
s2: begin
if (i1) begin
// Output logico1 <= 0;
// State transition logic
state <= s1;
end
end
endcase
end
end
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Workshop
1. Express the following FSMs in Verilog RTL.
2. Verify your design by writing a test-bench.
