Upload
others
View
15
Download
0
Embed Size (px)
Citation preview
Fully Depleted SOI Technologies y p gBich-Yen Nguyen
AcknowledgementsAcknowledgementsSOITEC Team:• Jean-Michel Bidault • Nicolas Daval
IBM Team:• Kangguo Cheng• Ali KhakifiroozNicolas Daval
• Frederic Allibert• Ludovic Ecarnot • Konstantin Bourdelle
Ali Khakifirooz• Bruce Doris• Ghavam Shahidi
• Walter Schwarzenbach• Mariam Sadaka • Phuong Nguyen
Carlos Mazure
STM Team:• Qing Liu • Franck Arnaud
Nicolas Planes• Carlos Mazure • Olivier Bonnin • Christophe Malevillle• Justin Wang
• Nicolas Planes• Giorgio Cesana
Global Foundries :Justin WangCEA/Leti Team:• Olivier Weber • Francois Andrieu
Global Foundries :• Scott Luning
• Maul Vinet• Olivier Faynot
2MOS-AK/GSA Workshop, April 11-12, 2013
• CMOS Landscape Beyond 28nm Node
• Value propositions of the Planar Fully Depletet SOI Technology
• Performance and Power Benchmarking
• FDSOI Device and Substrate RoadmapFDSOI Device and Substrate Roadmap
• Summary
MOS-AK/GSA Workshop, April 11-12, 2013
CMOS Landscape Beyond 28nm
4MOS-AK/GSA Workshop, April 11-12, 2013
Challenges of Continued CMOS Scaling
• Increased standby power dissipationSource: IBM, T.C. Chen, ISSCC 2006
• Increased standby power dissipation
• Amplified Vth variability
⇒Impact Yield
5
⇒Impact Yield⇒Limit Vdd scaling
MOS-AK/GSA Workshop, April 11-12, 2013
Leakage Power is still a Major Issue Despite the Use of Hi-K DielectricUse of Hi K Dielectric
High-K/Metal Gate StackStack
SiON/Poly Gate Stack
6
Source: IBS
MOS-AK/GSA Workshop, April 11-12, 2013
New Device Architectures
2003 2005 2007 2009 2011
90nm
65nm
45 nm
32nm
22nm
Strained Silicon
High-K / Metal Gate
F ll D l t d Introd ction of Ne
Introduction of New Materials
Fully Depleted Devices
Introduction of New Device Architecture
7MOS-AK/GSA Workshop, April 11-12 2013
Fully Depleted Technology Landscape
Intel IBM STM
Foundries –16/14 nm
Foundries Foundries
MOS-AK/GSA Workshop, April 11-12, 2013
Value Propositions of the PlanarFully Depleted SOI TechnologyFully Depleted SOI Technology
9MOS-AK/GSA Workshop, April 11-12, 2013
Alternate FD Device Architectures: Planar FDSOI or Vertical Multi-Gate FinFET-SOI
G G
Minimum Design
DisruptionMax l bilit
S D
Bulk Si
Buried OXS DG
S DGDisruption scalability
Bulk SiBuried oxide
Conventional Planar Bulk Transistor
Planar Single-or double Gate FDSOI
Vertical Multiple-Gate FinFET SOI
Buried oxide
MOS-AK/GSA Workshop, April 11-12, 2013
The End of Conventional MOSFET- The Era of FD Device Architecture
22nmPlanar
11MOS-AK/GSA Workshop, April 11-12, 2013
Planar ETSOI Structure and Advantages
Junctions
Gate Material
Film & BOX
Isolation Body Bias
Thin Silicon Channel
‐‐ ‐ Hybrid BulkGround Plane
• Total dielectric isolation– Lower S/D capacitances
– Lower S/D leakages
• No channel doping, no pocket implant– Improved VT variation
• Ultra thin BOX optiong
– Latch-up immunity
• Ultra thin Body (TSi~1/3LG)– Excellent short channel immunity
Ultra thin BOX option– Back bias control
• Ground plane implantationV dj
y
– =>Low SCE, small SS & DIBL– VT adjustment
Source: STM J. Hartmann,, GSA Apr. 2012
MOS-AK/GSA Workshop, April 11-12, 2013
Threshold Voltage MismatchMeasurement Benchmarking
8
m)
Measurement
60% R d ti60% R d ti2.5
3Bulk platformFDSOI MOSFETs
ST 65nmST 45nm
IBM 90nm
Benchmarking
246
vt(m
V.µm
60% Reduction60% Reduction
1.5
2
AV
t (mV
.um
)
Intel 45nm
Intel 65nm
ST FDSOI
HitachiFDSOI
IBM alliance32nm
Bulk 1Bulk 2
Bulk 3Bulk 4
PDSOIDSOI nMOS
pMOS
0A v 50% Reduction50% Reduction
0.5
1
10 20 30 40 50 60
This workST GAA
IMEC FinFET
FDSOI
Source: Thean et al, F l IEDM2003
PDFDSOI MOS
Avt = q √ 2 Nch Wdep / Cox
10 20 30 40 50 60
Gate length L (nm)
Square Vd=1V circle Vd=50mVSource: O. Weber et al, Leti CEA, IEDM2007
• Device matching important to SRAM/Analog circuits (eg. Current mirrors)
• FDSOI (undoped channel) features 50-60% mismatch
Freescale, IEDM2003 Leti CEA, IEDM2007
13
• FDSOI (undoped channel) features 50-60% mismatch improvement over bulk CMOS and PDSOI (doped channel)
MOS-AK/GSA Workshop, April 11-12, 2013
Scaling rules down to 8nm nodeTCAD with Electrostatic considerationsTCAD with Electrostatic considerations
8
10
)
TSOI (thick BOX=145nm)
TSOI (UTBOX case)TBOX= 25nm
6
8d
TS
OI (
nm
) TSOI (UTBOX case)
NanoWire
25nm
10nm
7 55nm Tsi
2
4
Re
qu
ire
d NanoWire 7.5nm
TBOX= 145nm
0
2 6 10 14 18 22L (nm)
DIBL=100mV/V
• Scalability possible down to LG~10nm, thanks to UTBOX
LG (nm)
Courtesy of CEA-LETI O Faynot et al IEDM 2010;
14
Courtesy of CEA LETI, O. Faynot et. al. IEDM 2010;
MOS-AK/GSA Workshop, April 11-12, 2013
Multi-VT Solution with Dual Metal Gate/GP
0,6
0,8LVT RVT HVT SHVT
Logic SRAM
BOX
TiN
nMOS
BOX
TaAlN
pMOS
N-GP P-GP Metal
LVT
BOX
TiN
nMOS
BOX
TaAlN
pMOS
N-GP P-GP Metal
LVT
BOX
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
TiNHVT
BOX
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
TiN
BOX
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
TiNHVT
0
0,2
0,4
ld v
olta
ge (V
)
GP-N GP-P
GP-PGP-N
nMOS
BOX
TiN
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
change
GP change
RVT
BOX
TiN
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
change
GP change
RVT
BOX
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
TiNSHVT
BOX
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
TiN
BOX
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
TiNSHVT
-0,6
-0,4
-0,2
Thre
shol
GP-P GP-NGP-NGP-P
pMOS GP change metal
change
-0,8
g
TiN TaAlN/TaN
O. Webber et al., IEDM’10
• Multi Vt requirement for SoC can be achieved for FDSOI device qusing dual WF metal-gate and ground-plane approach without back-bias
MOS-AK/GSA Workshop,, April 11-12, 2013
Body Bias: Speed & Power ControlFDSOI Workshop San Francisco, Feb. 2012
1.FDSOI
1616MOS-AK/GSA Workshop, April 11-12,, 2013
Multi-VT Modulation for ETSOI with Back Bias
Leti- VLSI 2010 Q. Liu, ST, VLSI 2010
• VT tuning with BOX = 10nm and VBB , GP • N and PMOS: VT modulation of ≤200mV for 10nm BOX• No degradation of Ion-Ioff trade-off with back-bias up to• No degradation of Ion-Ioff trade-off with back-bias up to
+/-2V
17MOS-AK/GSA Workshop, April 11-12, 2013
C2 - Confidential 18
C2 - Confidential 19
ETSOI Structure by IBM
Lg= 25nmTsi= 6nm
B - SiGe
In-situ boron doped SiGe S/D:
K. Cheng et al, IBM, VLSI 2009
In-situ boron doped SiGe S/D:⇒Lower S/D resistance⇒Reduces parasitic capacitance
20MOS-AK/GSA Workshop, April 11-12, 2013
20nm FDSOI Performance Improvement VLSI 2011
K. Cheng et al, IBM, VLSI 201120nm FDSOI on Thick BOX
• Ion for both N- and PMOS improved by optimizing S/D resistant and Tinv.
C2 - Confidential 21• 20nm FDSOI RO delay at 0.9v improved by 20% as compared
to those of 28nm Bulk RO at 1vMOS-AK/GSA Workshop, April 11-12, 2013
Boosting FDSOI Performance with subtrate & strain engineering – IBM, A. Khalifizoor-VLSI 2012
More perf gain
• DC performance of FDSOI is comparable to state of the art planar bulk devices
22
planar-bulk devices• Smaller Lg and junction area => better AC performance
MOS-AK/GSA Workshop, April 11-12, 2013
C2 - Confidential 23
C2 - Confidential 24
FDSOI in a Nutshell
• FD SOI solves most of the CMOS scaling challenges
• FD SOI is SoC friendly
• FD SOI design is equivalent to Bulk• FD SOI design is equivalent to Bulk
• FD SOI process cost equivalent to Bulk LP (28nm)
• FD SOI is a scalable technology
• FD SOI is risk-free alternative to FinFET for LP/G productsFD SOI is risk free alternative to FinFET for LP/G products
25MOS-AK/GSA Workshop, April 11-12, 2013
Planar FD SOI Value Proposition
FD SOI b i f i h d l hi h f • FD SOI brings a easy manufacturing path to develop high performance and low power CMOS process derivatives– Simple planar technology and transistor architecture– High performance at low supply voltageHigh performance at low supply voltage– Easy way to build different VTs for SoC design– On top of poly biasing, body biasing bring tremendous flexibility to the SoC
design
• FD SOI enables time effective technology and design solutions – Re-use of most of the Bulk process FEOL modules, BEOL is fully identical
Mi ti di it l B lk lib i d d i t FD SOI i h t i ti – Migrating digital Bulk libraries and designs to FD SOI is a re-characterization and signoff
– FD SOI wafer easily etched to implement bulk structures and IPs– EDA flow and design techniques remain identical as Bulkg q
• FD SOI delivers a same performance as those 28nm HP technologies, without back bias (BB) or higher performance with BB at the cost of a 28 LP 28nm LP process
26MOS-AK/GSA Workshop, April 11-12, 2013
Pl FDSOI B lkPlanar FDSOI vs. Bulk Performance/Power Benchmark
27MOS-AK/GSA Workshop, April 11-12, 2013
CONFIDENTIAL
CONFIDENTIAL
CONFIDENTIAL
IBM Research
RO Comparison (ETSOI vs. FinFET)610-6
FinFET
/µm
) ETSOIRO DelayVDD
Ioff = 200nA/µm
10-7 0.7V
FP (
A/
finFET*ETSOI
RO Delay (ps/stage)
VDD
10-8
+ I
OF
V 0 9V 13.511.20.7V
8.50.9V
7 9 11 13 15 1710-9
0.7V0.8V
I OFFN VDD= 0.9V 13.511.20.7V
7 9 11 13 15 17Delay (ps/stage)
ETSOI RO is faster than state of the art finFET
*C. Auth, et al. Presented at Symp. VLSI Tech., 2012
3126
ETSOI RO is faster than state-of-the-art finFET Courtesy of Bruce Doris, IBM K. Cheng et al. IEDM 2012
MOS-AK/GSA Workshop, April 11-12, 2013
Yield Learning Equivalent to Bulk Process
MOS-AK/GSA Workshop, April 11-12, 2013
Pl FDSOI Ad ti dPlanar FDSOI Adoption and Roadmapp
33MOS-AK/GSA Workshop, April 11-12, 2013
CONFIDENTIAL
CONFIDENTIAL
FD SOI Migration Path
28nm FDSOI 14nm FDSOI
28nm SLP 20nm LPM113CPP90Mx
90CPP64Mx
113CPP 90CPP
2011 2012 2013 2014
113CPP90Mx
90CPP64Mx
Courtesy of ST
• Low risk and effective TTM strategy to migrate Bulk platforms to FD SOI• Straightforward path to re-characterize 20nm LPM design environment
36
Straightforward path to re characterize 20nm LPM design environment to 14nm FD SOI
MOS-AK/GSA Workshop, April 11-12, 2013
Soitec FD-2D Substrate Options
Ultra‐Thin Top Silicon Layer
Base Silicon
Ultra‐Thin Buried Oxide
Ultra‐Thin Top Silicon Layer
Base Silicon
Ultra‐Thin Buried OxideGS D
Base Silicon
Ultra‐Thin Top Silicon Layer
Base Silicon
Ultra‐Thin Buried Oxide
Soitec FD-2D
GS D
Base Silicon
Sampling now: SOI + strain
Soitec FD-2DEvo14 with sSOI
Soitec FD-2DE 28
Sampling now
GS D
Base Silicon
Soitec FD 2DEvo20
Sampling now
28 nm
In prod now
15 nm / 14 nm
Evo28
22 nm / 20 nm
37
28 nm 15 nm / 14 nm22 nm / 20 nm
MOS-AK/GSA Workshop, April 11-12, 2013
FD-2D Substrate Uniformity: Thin SOI & Thin Box
SOI12nm
+4Å
SOI Thickness Range @ 3.13 A
Base wafer
BOX
120Å
+2Å
+4Å
6 sigma
Wafer-to-wafer thickness (Å)
BOX Mean @ 250 ±6 AW2W Range < 7 A
-2Å
-4Å
6 sigma
W2W hi k 120 5 A
0
20
40
60
Per
cent
age
252.1 AMax
247.2 AMean
244.5 AMin
BOX Thickness Mean
252.1 AMax
247.2 AMean
244.5 AMin
BOX Thickness Mean
Wafer to wafer thickness (Å) W2W thickness 120 ±5 A
ints
SO
I ro
l (Å
)
225 230 235 240 245 250 255 260 265 270 275BOX Thickness Mean
40
60
cent
age
4 4 AMean
2.7 AMin
BOX Thickness Range
4 4 AMean
2.7 AMin
BOX Thickness Range
Within wafer thickness (Å)
All
waf
ers,
all
poth
ickn
ess
cont
r
0 1 2 3 4 5 6 7 8 9 10BOX Thickness Range
0
20Per
c
6.8 AMax
4.4 AMean
6.8 AMax
4.4 AMean
12 April 2013 38
1 year production at prime spec
A
MOS-AK/GSA Workshop, April 11-12, 2013
SSummary
39MOS-AK/GSA Workshop, April 11-12, 2013
Planar FD SOI Summary1. FD SOI provides outstanding benefits for high performance, battery powered
devices
Leading edge performance across the full Vdd range– Leading edge performance across the full Vdd range– Good speed vs leakage trade-off– Record Vdd min for logic and SRAM– Full flexibility in IP design with dynamic voltage scaling and biasingy g y g g g– Better performances than a G process at the cost of an LP technology
2. FD SOI offers a low risk design and manufacturing path for CMOS process derivatives at 28, 20 and 14nm
– No major disruption from current Bulk CMOS process manufacturing – Same EDA flow and design techniques as planar Bulk– Digital designs easy to re-characterize on FD SOIDigital designs easy to re characterize on FD SOI
3. Industry first Fully-Depleted SOC using 28nm FDSOI technology was demonstrated by STM/STE with 3GHz performance
4. 28nm and 14nm FD SOI will be available in foundries in 2013 and 2014, respectively
MOS-AK/GSA Workshop, April 11-12, 2013
FD-SOI provides unique value
FasterTransistors run at higher frequencies up than bulk CMOS enabling faster processors
This puts more powerful devices in the hands of the end user
CoolerTransistors are more power efficient than bulk CMOS with lower leakage and much wider range of operation points down to lower voltages
Simpler
and much wider range of operation points down to lower voltages
End user devices run cooler and last longer.
SimplerThe manufacturing process for FD-SOI is much simpler than alternatives and making extensive use of existing fab infrastructure
Design porting from bulk is simple and fast
Chi hit t d t ti i l d ft i i l f d i
41 (10)
Chip architecture and construction are simpler and software is simpler for devices manufacturers
MOS-AK/GSA Workshop, April 11-12, 2013
Thank You