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Gate Driver Timing Specification
Requirements for WBG Devices
Ryan Schnell
Applications Engineer
iCoupler® Isolated Gate Drivers
Analog Devices, Inc.
Agenda
► Wide Bandgap Devices and Their Implications
► The Ideal “Gate Driver”
► Key Timing Metrics and Why They Matter
2
Wide Bandgap Devices
3
Material Bandgap Energy (eV)
Silicon 1.1
Silicon Carbide 3.3
Gallium Nitride 3.4
► Wide bandgap devices are named due to much higher bandgaps than traditional silicon.
► Above 4 eV is (usually) considered an insulator
Breakdown Voltage
Ro
n
Si L
imit
SiC
Lim
it
GaN
Lim
it
Better
[1] DOE 2013
[1]
Wide Bandgap Devices - Benefits
4
► Higher voltage blocking for lower on
resistance
Allows for a more efficient on state
Lower conduction losses
► Faster switching edges
Allows for smaller “IV triangle”
Lower hard switching losses even at same
switching frequencies
► Allows for faster frequencies
Smaller passive components
Slow edges Faster Edges
Frequency CapabilityS
i IG
BT
Si
MO
SF
ET
SiC
MO
SF
ET
Ga
N M
OS
FE
T
Play Spaces
5
Switching Frequency
Po
wer
Level
Si MOSFET
GaN
SiCIGBT
Voltage
Pro
du
ct
Ran
ge
Si MOSFET
GaN SiC
IGBT
~650 V
Adapted from [2] Yole 2015 and [3] Titech 2018
[2] [3]
GaN Reverse Diode Action
6
► GaN exhibits a “diode like” action when reverse biased [4]
► “Diode drop” voltage is large (3-4 V)
► Voltage drop is present during hard switched deadtimes
Leads to significant power loss
► Significant even at higher bus voltages
Due to efficiency targets
Vds
Deadtime
Vbus
reverse bias
[4] GaN Systems 2016
The “Ideal” Gate Driver
Input
Output 1
7
► No timing disparity
► Level shifts control signal to power switch levels
► “Robust”
► (Example ignores EMI)
Controller
Power Device
?
“Ideal” Gate Drivers in a Half-bridge
8
► No timing disparity
► Level shifts control signal to power switch levels
► Provides level translation
Input
Output 1
Output 2
Vhalf-bridge
VBUS
VHS
VLS
Effect of Timing Mismatch
9
► Half-bridge legs:
If both switches are off, efficiency could suffer
If both switches are on, shoot-through occurs
Could be catastrophic!
Vhalf-bridge
VBUS
VHS
VLS
VDRIVER
► Single Switch Topologies:
Open loop values could be off
Closed loop largely compensated out
Key Timing Metrics
10
► Forward Path Metrics
Propagation Delay
Jitter
Rise/Fall Time
Pulse Width Distortion
Propagation Delay Skew
► Protection Timing Metrics
Reaction to overcurrent
Propagation Delay
11
► Delay from input to output of gate driver
► Must be much lower than controller bandwidth
► Theoretically can be compensated in controller
► Propagation delay, in itself, does not cause shoot-
through
This assumes both channels have EXACTLY the same
propagation delay
Input
Output 1
Output 2
Propagation Delay Propagation Delay
Input
Output 1
Propagation Delay Max
Propagation Delay Min
OUTPUT
INPUT
tDLH
tR
90%
10%
VIH
VIL
tF
tDHL
14
96
7-0
18
► Can be defined 50%
to 50% or VIH/L to
10/90%
Jitter
12
► Cycle to cycle reproducibility of propagation delay on a single part, at one operating point
► Jitter metrics are folded into the min/max propagation delay, PWD, and skew
► Can produce small ripple on converter outputs, but jitter is usually small and can be ignored
Input
Output 1
Rise/Fall Time
13
► Rise and Fall time are gate drive strength metrics
► SiC and GaN has lower gate charges for comparable Si devices
► Rise and Fall times can be tuned by gate resistors in most drivers
Pulse Width Distortion
14
► Difference between rising and falling delays, usually on a single part
Causes duty cycle change
Can be dealt with in controller in most cases
Input
Output 1
LtoH Prop Delay HtoL Prop Delay
Propagation Delay Skew
15
► Very important, but often ignored
► Difference between edges of two different channels reacting to
the same input and operating conditions.
► Defined as per part (multiple channel), or part-to-part
► Skew is always smaller than total bounds of min/max
propagation delay
Input
Output 1
Skew
Output 2
Setting Deadtime Bounds
16
► Goals
No shoot-through
Shortest deadtime possible
► It is tempting to set deadtime based on min/max prop delay across all conditions
This is leaving performance unused
► Skew allows a much tighter deadtime to be set
Great advantage for GaN (reverse diode action)
► Pulse width distortion is NOT the same thing as skew
Setting deadtime based on PWD alone can lead to shoot-through
Input 1
Output 1
Output 2
Deadtime
Input 2
Max HtoL Prop Delay
Min LtoH Prop Delay
Vhalf-bridge
VBUS
VHS
VLS
Short Circuit Withstand Times
► Typical short circuit withstand times for Si MOSFETs and
IGBTs are typically specified at 10 µs.
► SiC MOSFET short circuit withstand times have been
reported as low as 4 µs [5]
► GaN normally off short circuit withstand times have been
reported as low as 1.8 µs [5]
17
Ch. 1 Vi+ Ch. 3 nFault
Ch. 2 Gate Out Ch. 4 Desat
Traditional Desat Detection
[5] Badawi et al. 2016
Summary
18
► GaN and SiC promise great advantages to Si MOSFETs and IGBTs
► GaN reverse diode characteristic necessitates shorter deadtimes
► This drives “tighter” timing specs, not necessarily “faster” timing specs
Propagation delay skew is the unsung hero, and sometimes isn’t even specified in datasheets
► GaN and SiC shorter short circuit withstand times demand faster protection speeds
References
19
[1] Advanced Manufacturing Office, “Wide bandgap semiconductors: pursuing the promise,” DOE/EE-0910, April 2013, US Department of Energy
[2] Dia.pe.titech.ac.jp. (2018). SiC power device - Hatano_&_Kodera_Lab. @ Titech. [online] Available at: http://dia.pe.titech.ac.jp/HTML5_ENG/research/sicdevice.html
[3] Yole Développement. ‘Status of the Power Electronics Industry 2015’, France, February 2015
[4] GaN Systems Inc.”GN001 Application Brief: How to drive GaN Enhancement mode HEMT”, Canada 2016.
[5] N. Badawi, A. E. Awwad and S. Dieckerhoff, "Robustness in short-circuit mode: Benchmarking of 600V GaN HEMTs with power Si and SiC MOSFETs," 2016 IEEE
Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI, 2016, pp. 1-7.
Thank you
20