IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 4, APRIL 2014 1567

Letters

Magnetically Isolated Gate Driver With Leakage Inductance Immunity

Khairul Safuan Muhammad and Dylan Dah-Chuan Lu

Abstract—This letter presents the design of a magnetically iso-lated gate driver with high immunity to leakage inductance. Theproposed gate driver (PGD) is developed based on a bipolar totem-pole gate driver (noninverting) located on the secondary side of thecoupling transformer. It is able to drive a MOSFET/IGBT fromstandard CMOS to TTL output and down to LSTTL level. It alsoachieves large duty cycle ratio and small input to output delay andprovides reliable isolation. In this letter, the PGD is analyzed andverified experimentally. The design guidelines are also providedincluding design considerations.

Index Terms—Bipolar totem-pole, coupled inductor, isolatedgate driver, leakage inductance immunity, low-power Schottkytransistor–transistor logic (LSTTL).

I. INTRODUCTION

THE demand for an efficient and reliable gate driver forpower switches grows every year. It is concomitant with

the development of various characteristics and specificationsof power switching devices. Most in-chip IC drivers utilizeda direct connection between the PWM signal output and thegate which offers a lot of advantages such as high speed andhigh dV/dT immunity. However, when dealing with high-powerconverters and motor drive applications, isolation is usually re-quired for separation of low-voltage side from high-voltage side.Optical and magnetic isolations are common ways to provideisolation. Optical isolation devices such as optocoupler, how-ever, have limited range of operating temperature which is lessthan 100 ◦C for an average optocoupler [1]. Therefore, trans-former isolation is the preferred method when dealing withthe aforementioned applications. The various methods utilizingtransformer isolation have been proposed according to particularrequirements.

The magnetic isolation methods for the gate driver have ad-vantages such as dc isolation, impedance matching, ratio varia-tions, and level-shift abilities. The pulse transformer is amongstthe popular magnetic isolation methods to build a gate driver.However, transformers are only capable of working with ac in-put. The transformer cores need to be reset at every half-cycle

Manuscript received May 5, 2013; revised July 19, 2013; accepted August16, 2013. Date of current version October 15, 2013. This work was supportedin part by the Ministry of Higher Education, Malaysia, University TeknologiMARA, Malaysia, and The University of Sydney, Australia. Recommended forpublication by Associate Editor C. C. Mi.

The authors are with the School of Electrical and Information Engi-neering, University of Sydney, N.S.W. 2006, Australia (e-mail: khairul.muhammad@sydney.edu.au; dylan.lu@sydney.edu.au).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2013.2279548

Fig. 1. Proposed gate driver in [6].

and the average volt-second of the transformer must be zero toavoid core saturation. The conventional gate driver as in [1]–[4]provides a simple solution with large duty cycle ratio, how-ever, it requires a bipolar input signal. In [5], the authors solvedthe problem of using bipolar input but it is only applicable tolow-side gate drivers. A popular gate driver as proposed in [6](PGD6) is shown in Fig. 1. It is driven from a standard unipo-lar gate drive input level (12–15 V). The voltage across VL2 isreduced according to the voltage drop across CC 1 . Therefore,the gate drive level must be increased by adding a dc restorecircuit on the secondary side of the coupling transformer byadding a coupling capacitor, CC 2 and a diode, D1 . However,the gate driver needs a very good transformer coupling, wherea small value of leakage inductance will cause distortions andresonances to the output voltage. There is also a gate driverthat actually uses the leakage inductance as one of the elementsin the gate driver known as resonance gate driver (RGD). It isamong the popular gate drive techniques which started in the late1980s. The RGD normally is developed according to specificapplications and/or requirements [7] such as pulse driven [8], [9]or continuous driven [10]–[12]. However, the RGD is like otherdirect connection gate drivers which do not provide isolationbetween low-power side and high-power side.

In [13], the author suggested a topology which can be drivenusing a low input signal but the topology causes a delay be-tween the input and output stage due to the time taken by thebase charge carrier to leave the region and to forming the de-pletion layer. A reliable gate driver is proposed in [14] but thecomponent counts are high and it needs additional componentsfor the interface between the PWM signal and the gate driverinput. There is no transformer isolation gate driver that is able tocover the whole power switches requirements and it may comewith some tradeoff. Therefore, this letter introduces a new gatedriver which retains the advantages of previous gate drivers andalso addresses the aforementioned problems.

0885-8993 © 2013 IEEE

1568 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 4, APRIL 2014

Fig. 2. Proposed gate driver circuit.

II. PROPOSED GATE DRIVER CIRCUIT DESCRIPTION

AND OPERATION

Fig. 2 depicts the proposed gate driver (PGD) circuit. It con-sists of a damping resistor, RD , a dc blocking capacitor, CC , abase resistor, RB , a speed-up capacitor, CS , bipolar totem-poletransistors, Q1 and Q2 , a gate resistor, RG , a turn-off diode,Doff , and a gate-to-source resistor, RGS . When a unipolar sig-nal is applied to the primary side of the transformer, it passesthrough CC and differentiates the input signal. This causes apulse of current through the transformer primary side. It alsoprovides the reset voltage for the transformer to prevent coresaturation. CC must be placed in series with the input to avoidduty ratio dependents by blocking the dc voltage to appear acrossthe primary winding. The changes in the duty ratio will excitethe resonant tank between CC and L1 and cause resonance. Theresonance can be reduced by adding a damping resistor, RD inseries with the CC .

The current in L1 will induce L2 and turns ON Q1 (if thecurrent induced in L2 is positive w.r.t. Q1 emitter). The gen-erated voltage across L2 must be high enough to turn ON thetransistor. Without the speed-up capacitor, the gate driver in-troduces propagation delay between the input and output. Thepropagation delay is caused by the rise time, fall time, and thetime taken by the transistors to enter and leave the cutoff andsaturation regions. The switching time of the transistors can besped up by adding a capacitor in parallel with RB . When thevoltage across L2 , VL2 is high, the speed-up capacitor, CS canbe assumed as short-circuited across RB . Therefore, the baseof Q1 is coupled directly to the VL2 . The base of Q1 is appliedwith high voltage overshoot, hence producing a high initial basecurrent in Q1 . While CS is charging, the base current of Q1is decreased. Hence, the voltage across VGS is equal to VC C .When VL2 is low, CS is discharged. −VL2 will be applied tothe base of Q1 and will turn OFF Q1 quickly and turns ON Q2 .Therefore, the voltage across VGS will be zero.

The PGD does not need a dc restore circuit because the VGSlevel is depend on the VC C supplied by the isolated secondarypower supply. The isolated secondary power supply can be pro-duced by adding an extra coupled winding from the inductoror transformer of the converter [15], [16]. Alternatively, a low-power boost converter can be used. Nowadays, the low-powerboost converter comes in small package size [17]. The outputof the PGD is taken from emitter of Q1 and Q2 to the collector

TABLE IEXPERIMENTAL SETUP PARAMETERS

Fig. 3. PGD speed performance. (a) Turn-on. (b) Turn-off. VGS =4 V/div,Vin =2 V/div, 100 ns/div.

of Q2 . To increase the turn-off speed of the driver, a simpleturn-off diode is placed across the gate resistor. The diode isturned ON when the gate current is greater than the ratio of thediode forward voltage to the gate resistor.

III. DESIGN CONSIDERATIONS AND COMPONENT

SELECTION GUIDELINES

The design guidelines in choosing the components for thePGD are as follows:

A. Damping Resistor, RD

The value of the damping resistor RD can be determined bythe impedance of the resonant tank, L1 and CC as follows:

RD ≥ 2 ×√

L1

CC. (1)

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 4, APRIL 2014 1569

Fig. 4. Gate driver speed performances. (a) PGD6. (b) PGD.

Care should be taken in selecting the damping resistor. The highresistance value will limit the current flow through the couplingtransformer, hence limiting the gate current while lower resis-tance value will cause volt–second unbalance to the couplingtransformer.

B. Coupling Capacitor, CC

The ripple voltage across CC must be less than 0.7 V to avoidthe bipolar transistors from being turned ON. The relationshipof the ripple voltage and the total charge required can be usedto determine the coupling capacitor value. The elements thatinfluence the determination of the coupling capacitor are the gatecharge required by the MOSFET, and current flowing throughthe RGS . Hence, the value of CC can be determined by (2)

CC =QG

ΔVCC

+Vin × (1 − D) × D

ΔVCC× RGS

× fs(2)

where Vin is the input voltage of the gate driver, D is the dutycycle, ΔVCC

is the ripple voltage across CC , and fs is theswitching frequency. The maximum value of CC can be foundwhen D is equal to 0.5.

Fig. 5. Switching transitions for PGD. (a) Turn-on. (b) Turn-off.VD S =10 V/div, VGS =10 V/div, and ID =0.5 A/div, 200 ns/div.

C. Coupling Transformer, T

The coupling transformer is the key element in the PGDto achieve isolation. The transformer must not restore energybecause the stored energy will cause a delay in the drive path.A 1:1 ratio transformer (or so-called coupling transformer) isused to provide the galvanized isolation between L1 and L2 .In 1:1 ratio transformer, the stored energy is represented by theleakage inductance. Therefore, to reduce the amount of leakageinductance, a bifilar winding is used to provide better couplingin between the winding and consequently reduce the leakageinductance. A high permeability core can be used to maximizethe magnetizing inductance but it is not critical for the PGD sinceit only required 0.7 V to turn ON the bipolar transistors. Five toten turns are adequate to provide turn-on voltage for the bipolartransistors. The coupling coefficient, k can be determined by thefollowing equation [18]:

k =√

1 − LS

L1(3)

1570 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 4, APRIL 2014

Fig. 6. Practical switching waveform for PGD at different duty ratio.(a) ≈ 10% duty ratio. (b) ≈ 90% duty ratio. CH1:Vin , CH2:VD S , CH3:ID ,and CH4:VGS .

where LS is the primary inductance value when the secondaryside of the transformer is short-circuited and L1 is the primaryinductance value when the secondary side of the transformer isopen-circuited.

D. Speed-Up Capacitor, CS

The time constant formed by CS and RB must be very shortcompared to the pulsewidth of the input signal. With the speed-up capacitor, the turn-on speed is increased up to eight-foldcompared to the turn-on speed without the speed-up capacitoras long as the value of CS is selected according to (4)

CS <1

20 × RB × fmax(4)

fmax =0.35

100 × tr(5)

where RB is the base resistor and tr is the rising time fortransistor.

Fig. 7. Practical switching waveform for PGD6 at different k. (a) k =0.78.(b) k =0.99. CH1:Vin , CH2:VD S , CH3:ID , and CH4:VGS .

E. Transistor Q1 and Q2

BJT is used due to the low turn-on voltage (≈ 0.7V ). Anypair of n-p-n and p-n-p transistors with similar current ratingand high pulse current capability is suitable.

F. Gate Resistor, RG

The selection of the gate resistor requires the considerationof a tradeoff between losses and rise time speed. However, arange between 3.3 and 20Ω resistors is reported to be suitablefor most switching devices [19].

G. Turn-Off Diode, Doff

The turn-off diode, Doff is turned ON when the gate currentis higher than the ratio between the diode forward voltage andthe gate resistor. A standard signal diode can be used.

IV. EXPERIMENTAL RESULTS

In this section, the experimental results of the PGD are pre-sented. The PGD is compared with PGD6 in terms of the speed

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 4, APRIL 2014 1571

Fig. 8. Practical switching waveform for PGD at different k. (a) k =0.49.(b) k =0.99. CH1:Vin , CH2:VD S , CH3:ID and CH4:VGS .

performance and the ability of both gate drivers operated withdifferent transformer coupling coefficients and switching fre-quencies. The PGD and PGD6 are tested by connecting a simplebuck converter with parameters shown in Table I.

The measured gate to source capacitance value, CGS (withcomplete connection) of the buck converter MOSFET atVDD =0 V is 4.1 nF and the results show in Figs. 3 and 4are tested under this condition. Fig. 3 shows the rise and falltimes of the PGD at 50% duty ratio are less than 125 ns. Thedelay between input and output is approximately in the range of100 ns.

Overall, the PGD has better speed performance in all aspectsover PGD6 especially the rising time of the output voltage asshown in Fig. 4. However, the PGD6 has less effect to thechanges of duty ratio. The waveforms of the PGD during thetransition when the buck converter is fully operated are shown inFig. 5. During turn-on, the turn-on delay is less than 50 ns withapproximately 120 ns rising time. During turn-off, the PGD hasa fast fall time and turn-off delay which is less than 100 ns.

Fig. 9. Practical switching waveform for PGD6 at different switching fre-quency. (a) fs =50 kHz. (b) fs =1 MHz. CH1:Vin , CH2:VD S , CH3:ID , andCH4:VGS .

Fig. 6 validated that the PGD can be operated at a large dutyratio. Fig. 6(a) and (b) shows the practical switching waveformof the PGD at approximately 10% and 90% duty ratio, respec-tively. The VGS is remained in good shape. However, the risetime of the VGS is increased as the duty ratio is increased. Mean-while, the fall time is reduced as the duty ratio is decreased. Themaximal duty ratio, D, for both PGD and PGD6 are dependenton switching period, TS , rise time, tr , and fall time, tf , whichcan be obtained from (6) and (7)

Dmin(%) =tr + tf

TS× 100 (6)

Dmin(%) =TS − (tr + tf )

TS× 100. (7)

The range of the duty ratio is proportional to the switchingperiod. PGD has wider duty ratio range than PGD6 because ithas faster rise and fall times.

Figs. 7 and 8 show the experimental results of the practicalswitching waveforms with different coupling coefficient val-ues for the PGD6 and PGD, respectively. The same coupling

1572 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 4, APRIL 2014

Fig. 10. Practical switching waveform for PGD at different switching fre-quency. (a) fs =50 kHz. (b) fs =1 MHz. CH1:Vin , CH2:VD S , CH3:ID , andCH4:VGS .

transformer is used for both the gate drivers. At k =0.78 forPGD6, the VGS produced is distorted with high peak value atrise time which exceeds the nominal VGS value. A slightly betterVGS waveform is generated at high k =0.99. However, the VGSlevel is slowly decaying from approximately 20 to 10 V. Thisdecay can be overcome by increasing the inductance value of thecoupling transformer, which will increase the size of the cou-pling transformer. The input waveform of the PGD at k =0.49is distorted compared to the input waveform at k =0.99. Never-theless, this does not affect the generation of VGS . The resultsalso show that the generation of VGS is not really affected bycoupling coefficient variations and the PGD is immune to theleakage inductance.

Figs. 9 and 10 show the practical switching waveform forPGD6 at 50 kHz and 1 MHz switching frequencies. The testsare performed using the same k =0.99 coupling transformer. ForPGD6, at low frequency, the magnitude of the input voltage isreduced which also causes reduction on the magnitude of VGS .Again, this magnitude reduction can be overcome by using high-inductance coupling transformer. At higher frequency, the VGS

produced by PGD6 is distorted and the turn-on delay is alsoincreased. Fig. 10 shows that the PGD is capable of operatingat a wider range of the switching frequency. The VGS producedis better than PGD6 and there are no significant reductions anddecays of the magnitude.

V. CONCLUSION

The design of a magnetically isolated gate driver with highimmunity to leakage inductance has been presented. The gatedriver has fast rise and fall times, small turn-on and turn-offdelays, less duty ratio dependent, and the ability to operate at ahigh frequency more than 1 MHz. The PGD is able to operateat low value of coupling transformer inductance and couplingcoefficient/high leakage inductance. Hence, the PGD is immuneto the leakage inductance.

REFERENCES

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[2] I. Rectifier, “Transformer-isolated gate driver provides very large dutycycle ratios,” Appl. Note AN-950

[3] S. Sunter and J. Clare, “Development of a matrix converter inductionmotor drive,” in Proc. 7th Mediterr. Electrotech. Conf., Apr. 1994, vol. 2,pp. 833–836.

[4] V. Nguyen, J.-C. Crebier, and P. Jeannin, “Compact, isolated and simple toimplement gate driver using high frequency transformer,” in Proc. IEEE26th Annu. Appl. Power Electron. Conf. Expo., Mar. 2011, pp. 1092–1098.

[5] K. I. Hwu and Y. Yau, “Application-oriented low-side gate drivers,” IEEETrans. Ind. Appl., vol. 45, no. 5, pp. 1742–1753, Sep.–Oct. 2009.

[6] L. Balogh, “Design and application guide for high speed MOSFET gatedrive circuits,” in Power Supply Design Seminar, SEM-1400, Topic 2. NewDelhi, India/Dallas, TX, USA: Texas Instrument/Unitrode Corporation.

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[8] D. Maksimovic, “A MOS gate drive with resonant transitions,” in Proc.IEEE 22nd Annu. Power Electron. Spec. Conf., 1991, pp. 527–532.

[9] H. L. N. Wiegman, “A resonant pulse gate drive for high frequency ap-plications,” in Proc. 7th Annu. Appl. Power Electron. Conf. Expo., 1992,pp. 738–743.

[10] Y. Panov and M. Jovanovic, “Design considerations for 12-v/1.5-v, 50-avoltage regulator modules,” IEEE Trans. Power Electron., vol. 16, no. 6,pp. 776–783, Nov. 2001.

[11] Y. Panov and M. Jovanovic, “Correction to “design considerations for 12-v/1.5-v, 50-a voltage regulator modules”,” IEEE Trans. Power Electron.,vol. 17, no. 1, pp. 152–152, Jan. 2002.

[12] I. de Vries, “A resonant power MOSFET/IGBT gate driver,” in Proc. IEEE17th Annu. Appl. Power Electron. Conf. Expo., 2002, vol. 1, pp. 179–185.

[13] A. Ferencz. (2012). “Magnetically isolated digital coupling circuit,”[Online]. Available: http://www.how2power.com/article/2012/march/magnetically-isolated-digital-coupling-circuit-solves-gate -drive-and-communications-dilemmas.php

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[15] P. Grbovic, “High-voltage auxiliary power supply using series-connectedMOSFETs and floating self-driving technique,” IEEE Trans. Ind. Elec-tron., vol. 56, no. 5, pp. 1446–1455, May 2009.

[16] B. Andreycak, “Uc3854a and uc3854b advanced power factor correctioncontrol ICS (dn-44),” Application Report, SLUA177A. Texas Instruments,Apr. 1994–Revised Dec. 2005.

[17] I. International Power Sources, “Dc/dc converters, NME series 1watt,” (Jul. 8, 2013). [Online]. Available:http://pdf.datasheetcatalog.com/datasheets2/48/48656 1.pdf

[18] G. Barrere, “Measuring transformer coupling factor k.” (Apr.4, 2013). [Online]. Available:http://www.exality.com/files/Measuring%20Transformer%20Coupling%20Factor%20k.pdf

[19] Fairchild Semiconductor, “Suppressing MOSFET gate ringing in convert-ers: Selection of a gate resistor,” Appl. Bull. AB-9, 1998, Rev 1.0.2.

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