Generalized Switching Logic Interleaved

8/9/2019 Generalized Switching Logic Interleaved

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2004 35th Annual IEEE Power Electronics Specialists Conference Aachen, germ on^^, 2004

Generalized Switching Logic Schem e For CCM -PFC Interleaved Boost ConvertersM. A. P. Andrade, L. Schuch, J. R. Pinheiro

Power Electronics and Control Research Group - GEPOCFederal University of Santa Maria - UFSM97105-900 -Sa nta Maria, RS - BrazilEmail: [email protected], [email protected]: http://www.ufsm.br/gepoc Abstract - his paper presents an improvement in theoperation of the interleaved boost PFC achieved by a newswitching logic scheme. I n this technique, the choice of theoperation mode is defined by the value of the duty cycle of theconverter, which does not depend on the relationship betweeninput and output voltages. The new switching logic schemekeeps the input current ripple minimum through theappropriate phase shifting of the com mand signals. The conceptof the switching logic scheme is extended to n cells. Both theswitching logic algorithm and the impact of number of cellsunder input current ripple are discussed. Experimental resultsof a conventional boost and an interleaved boost converter withtwo cells are compared.

1. INTRODUCTIONWith more stringent and dem anding standards limiting theinput current harmonics [ I ] and the power factor [2] of theequipments connected to the AC utility grid, the passivemethods of power factor correction, using LC filters,become impracticable for medium power applications[3]-[4]. A ctive circuits for pow er factor correctio n usingbuck, boost, buck-boost, Sepic an d Cuk converters has been

proposed in the last years. Th e power factor correction basedon the boost cell i s the most popular technique [3], due to itsreduced number of components, easy control and highefficiency. Moreo ver, this topo logy has a step-up feature,which becomes it a strong candidate for universal inputvoltage applications (85 - 265 VWS).Boost cells operating with interleaving techniques areuseful for applications in which high values of current arerequired [5]-[7]. The interleaving technique permits toincrease the power density of the system, because thevolume of the boost inductors and volume of the EM1(Electromagnetic Interference) input filter are reduced [PI .Moreover, input current ripple frequency can be increased,without affect significantly the switching losses [9]. On theother way, the cost of the system is greater than theconventional boost, due to the extras components.Furthermore, the control and the circuits used to generate thecommand signals of the switches are more complex, becausethey should ensure the equalization of the currents throughthe boost cells.A switching logic scheme of the interleaved boostswitches, which minimizes the input current ripple andeliminates discontinuity in the input current, was proposed in[7]. This techniqu e presents tw o operation regions thatdepends on the relationship between the input and output

voltages of the converter. This dependence results in alimitation of the duty cycle applied to the switches,penalizing the dynamic response of the converter and, at lowpower range, leading the system to the instability.In this paper an improvement in the operation of theinterleaved boost PFC (Power Factor Corrector) is achievedby a new switching logic scheme. Now, the choice of theoperation region is defined by value of its duty cycle, whichdoes not depend on the relative amplitude of the input andoutput voltages. The problems previously mentioned wereeliminated, keeping still the minimization of input currentripple by appropriate phase shiRing o f the command signals,even in low pow er range.The addition in the number of cells leads to reduction ofinput current ripple. In this way, the concept o f the switchinglogic scheme is extended to n cells in parallel (Fig. I) . Th edecision of logic scheme, to control the n switches, is alsobased on the duty cycle. Algorithms to implement theswitching logic scheme for n cells converter and the effect ofthis under the input current ripple are explained. In the finalsections of this paper, simulation and experimental resultsare presented to verify the performance, pros and cons of thenew switching technique.

11. SWlTCHMGLOGIC SCHEMEFig. 2 shows the single phase two cells interleaved boostconverter, composed of a diode bridge, two witches (SI andS2),two diodes (D l and D2),wo boost inductors (L l and L 2 )

Fig. I . Interleavedboost converterwith two cells.

Fig. 2. Interleavedbws t converter with two cells.

0-7803-8399-0/04/$20.0002004 IEEE. 2353
mailto:[email protected]://www.ufsm.br/gepochttp://www.ufsm.br/gepocmailto:[email protected]


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2004 35thAnnual IEEE Power Electronics Specialisls Conference Aachen, Germany,2004

TABLE ISWITCHING LOGIC SCHEME PRESENTED IN [71.

Region 0 V , & ( @ < V d 2Control Signal (Dc) Gate signal (LIS,e 0.d

High SI an d S, onLow S, or S, on

Region I : V,,&(@>Vd2Control Signal (9) Gate signal (4, DA2)

HighLow

S , or S1 onS , an d S l off

and one output capacitor (c) . In this section the technique o fgeneration of the command signals proposed in [7] nd thenew technique will be presented.A.

The objective of this switching logic scheme is tominimize the input current ripple. To analyze this techniqueis assumed that the duty cyc le in both switches are the same,and that the variations of the input voltage during oneswitching period ar e negligible.The operation regions of this technique depend on th erelative amplitude of the input and output voltages, aspresented in TABLE I and their command signals are shownin Fig. 3 an d Fig. 4. The problem of this technique is that thedefinition of operation region is associated to input-output

Original switching logic scheme, propose d in [ 7 ]

Fig. ).Gate signals DSIand D.52, an d control signal DCat Region 0 ,OS,

0,

D C_ 1- - - _ - b- -+C TC rc 7-rTs liRegion IL 1

Fig. 4. Gate signals D.5, an d 0.51, and control signalDCatRegion I

Minimum Power (VA)Fig. 5 . Minimum power of !he interleavedb m t convener operating atRegion 0.

voltage relationship. As there is a limit value for the dutycycle for each region, it will cause penalties on converterperformance, instabili9, and input current distortion as well.The minimum duty cycle applied to the switches (Os] an dDs2)at Region 0 is 0.5 , when the width of Dc is zero. On theother side, at Region I the maximum duty cycle applied tothe switches is 0.5, when the width ofDC is 1.So, a converter operating into the Region 0 (Y,. 0,5Control Signal (Dc) Gate Signal(4,n d D,-)High SIan d Sl nLow S, or Sl on

Region I : Ds < 0.5Control Signal (DC) Gate Signal (Dsl an d 0,)

High SI or Sl nLow S, and Sl off

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2004 35th Annual IEEE Power Electronics Specialists Conference Aarhen, Germany, 2004

Fig. 6 . Amplitudeof the input current ripple in a utility g i d half-cycle forhvo cells.

TABLE IVREGIONSF THE SWITCHHG LOGIC SCHEME FOR AN INTERLEAVED BOOSTCONVERTERWITH n CELLS

Region Duty Cycle (DS)0 ( n - l ) / n < D , < II (n -2 ) /n< Ds < ( n - l ) / n2 ( n - 3 ) / n < D s < ( n - Z ) / n

n- 2n- l O < D s < l / n... ...I ln


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2004 35th Annual IEEE Pow er Electronics S pecialists Conference

Fig. 8. Behavior ofthe input ripple for V J V , = 0.915, for differ ent numberof cells.

Fig. I O . Maximum amplitude of th e input current ripple in function of thenumber afcells.

not track the reference. During the transition of regions, theinput curre nt ripple will b e null.TABLE 111 shows how many switches are on in eachregion. It is introduced a control logic to guarantee thecurrent equalization through the cells: When the PWMsignal is high, the switch with sm aller current must be turnedon; And when the PWM signal is low, the switch with highercurrent must be turned off.The input current ripple in each region, for n cells, isgiven by:

A / i n ( n , R ) = ( n - R)( D.,(S)- n

where:n - umber o f cells in parallel,R - egion o f modulation (0 lo n - I ) ,D,$(@ witch duty cycle,

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Aachen, Germany, 2004

0.W 0.01 0.M 0.MTime (s)

Fig. I I . Input current using the technique proposed.

tl

-sE 32

0.00 0.02 0.0. 0 . 0Time (s)

Fig.9 Input current using the techn ique presen ted in 171.1 .- ell inductance,Ts witching period.

Fig. 8 shows the behavior of the input current ripple forone input voltage hall-cycle using the proposed switchinglogic scheme. As n illcreases the amplitude of maximuminput current ripple decreases, a s shown in Fig. 10.

IV. SIMULATION RESULTSIn this section simulation results are presented todemonstrate the behavior of the technique proposed.Moreover, the simulation results will be used for acomparison between the new technique and the originaltechnique presented in [7].The parameters adopted for thesimulations are: L , and L2 3mH,j;=25kHz, V,,=3I 1V and

V, = 400V.Fig. 1 I and Fig. $ 1 show the input current when theconverter is subjected to a large variation into the inputcurrent reference. Fig. I 1 shows the input current when theproposed technique is used. In this case, there is nolimitations of values ,of duty cycle, which allows a goodperformance of the converter, even in low power range.Fig. 9 shows the distortion of the input current due tolimitations of the technique presented in [7].When theconverter is operating at Region 0, the minimum duty cycleapplied to the switches is 0.5, which causes distortions.


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2004 35th A n n u l IEEE Power Electronics Specialists Conference Aachen, Germany, 2W 4

"h 'LqT:+p@'Fig. 12. Conventional boost convener implemented.","

Fig. 13. Two cells Interleaved boost wnverter implemented

v. EXPERIMENTALESULTSAn experimental protoype was implemented todemonstrate the reduction in the input current ripple, whenanother cell is added to the system. Fig. 12and Fig. 13showthe circuitry of the prototypes implemented in the laboratory.In the first case a conventional PFC boost converter wastested. The parameters adopted were Po = 500W. L = 3mH,L = 251dIz, V,, = 110/220V and

V , = 400V. The semicondutors S and D are IRFP460 andSETH06 respectively. DSP TMS320F243, from Texasinstruments, implemented the digital controllers of thesystem (input current controller and output voltageregulator).Fig. 14and Fig. 15 show the input current and the inputvoltage of the conventional PFC boost converter operating at1 IO Vm s and 220Vms input voltage, respectively.After this, the PFC interleaved boost converter with twocells in parallel was implemented. The parameters adoptedinto the scheme presented in Fig. 13were the same of thoseadopted into the conventional PFC boost con verter.DSP controller also implemented the switching logicscheme and the controllers ofthe system. Fig. 16 and Fig. 17show the input current and the input voltage of theinterleaved PFC boost converter operating at 1 IO VRMs nd220Vws input voltage, respectively.DSP controller also implemented the switching logicscheme and the controllers of the system. Fig. 16 and Fig. 17show the input current and the input voltage of theinterleaved PFC boost converter operating at 1 IO VW S and220Vms input voltage, respectively.

Fig. 14. Input current and input voltage of the convention al boost wnverterat I OVRMS.(V,~OVIdiv and L SAldiv).1 lW / 3 lWV/ c 0.00s LoonJ StW t L

I IFig. 15. Input current and input voltage o fth e conventional boost converterat 22OVms (V," IOOVldiv, and I,. 2Aldiv).1 low c 0.00s 5JmY stow t L

.. . . . .. ." ..............

at I I VRMSV," JOVIdiv, an d I, 5Aldiv).

Fig. 17. Input current and input voltage of the interleaved boost convenerat 22OVn~ sV," IOOVldiv, and lJnAldiv).

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2004 35th A n n u a l IEEE Power Electronics Specialisls Cbnference Anchen, Cermony. 2004

A detail of the input current in both converten operatingat l lOVms is presented in Fig. 18 and Fig. 19. It can beobserved the reduction in the input current ripple of theinterleaved converter. Moreover, the high frequencycomponent for this topology is two times greater than thatappear in the conventional boost.In the same way, in Fig. 20 and Fig. 21 can be observed areduction of the maximum amplitude of the interleavedconverter input current ripple, when the converter areoperating at 220VRMs tility grid.

2 to?/ c 4.44 20.W Stop \ L

Fig. 18. Detail of conventional boost converter maximum input ripple, atI IOVRMS(I,~Ndiv) .

Fig. 19. Detail of interleaved bw st converter maximum input ripple andinductor ripple at I IOVmS(l,n(lop) and I,.,(bonom) 2Ndiv).

Fig. 20 . Detail of conventional bw st converter maximum input ripple at2 2 0 V ~ ~ sI, , and I,,, 2Ndiv) .

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1 to?/ c -5.mm w stop t L

i--, .......... ............... ...........

.. ..... .. . . .. .. . . . .. .. ^ < ji i i i ? j IFig. 21. Detail of interlea, ed b ws t converter maximum input ripple andinductor ripple at 220V-s (1,dlop) and Id bo lt om ) 2N div ).

VI . CONCLUSIONSThis paper presents m improvement in the switching logicscheme of the interleaved boost converter. In this newtechnique the choice olthe operation region is based on the

duty cycle of the converter, Therefore, the choice of theoperation region is rel;ited straight with the dynamic of theconverter, The minimiintion of the input current ripple wasobtained through the appropriate shifting of commandsignals applied to the switches. The concept of the switchinglogic technique was ertended to n cells, and algorithms toimplement the switching logic scheme were presented.The simulation results of the interleaved boost converter,used for PFC, proved I he advantages of the proposed logicscheme. This techniquc and the control system can be easilyimplemented by a low t.ostDSP.The experimental results show the reduction of theinterleaved boo st convc:rter input ripple, when anoth er cell isadded to the system. Since the amplitude of harmoniccomponents, which now are related to high frequencies, aresmaller than those oktained with the conventional boostconverter, conseq uently the EM1 input filter can be reduced.In this way, the intsrleaved boost converter is a strongcandidate for applicatims where a low input current rippleand low EM1 emission are required, as telecommunicationspower supplies.REFERENCES

[ I ] International Eleclrorechnical Commission, IEC 61000-3-2:Electromagnetic Compatibility (EMC) - Part 3 Limits -Section 2Limits forHarmonic Current Emissions, 2000.2 edition.121 Telebras Recommendation SDT 240-5 10-722 - E s p e c i f i c a W. gerais de sislemas naificadores chaveados em alta frequencia,Brazil, Dec 1997.James P. Nwn, Designing High-Power Factor Power Supplies,2002 Power Supply &sign Seminar, SE M 1500,Texas Instruments,

1312002.Po-Wa Lee, Yim-Shu Lee, David K. W. Cheng, Chiu Cheng Liu,Steady-Satate analysis of an Interleaved Boost Converter withCoupled Inductors Ii,dustnOl Electronics, IEEE Transactions on,Volume: 47 Issue: 4, Aug 2000.X. Huang, X. Wang, F. J. Nergaard, T. J. h i , X. Xu, L. Zhu,Parasitic ringing and design issues of high power interleaved boostc~nveners n IEEE Power Electronics Speclolists Conference, 002,pp. 30-35.1 Cadirci, A. Yafavi, lul. Ermis, Unity power factor bwst converterwith phase shifted pra i le l IGBT operation for medium power

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[SI

[6 ]


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2004 35rh Annual l EEE Pow er Electronics Specialists Conference Aarhen, Germany, 2004

applications in IEE E le mi c Power Applications, V. 149, no. 3,May, 2002, pp. 237 -244.I. R. Pinheiro, H. A. Grundling, D. R. Vidor, J. E. Baggio, ControlStrategy ofan interleaved boost power factor correction converter, inIEEE Power ElectronicsSpeciolisrsConf~rence,999, pp. 137-142.[8] L. Balogh, R. Redl, Power-Factor Correction with Interleaved BoostConverters in Continuous Inductor Current Mode in IEEE AppliedPower ElectronicsConfe rence, 1993, pp. 168-1 74.

[91 B. A. Miwa, D. M. Otten, M. F. Schlecht, High Efficiency PowerFactor Correction Using Interleaving Techniques, in Applied PowerElectronicsConference and EqosItion, 1992. APEC92. ConferenceProceedings 1992,23-27 FEE 1992, pp. 557-568.[IO] J. E. Baggia, H. A. Gnmdling, H. L. Hey, H. Pinheiro, J. R. Pinheiro.Discrete Control for Three-Level Boost PFC Converter, in IEEEInternotional Telecomrnunicotiom Energy Conference, 2002, pp.627-633.

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Generalized Switching Logic Interleaved