Greetings from IPC and Georgia Tech - UnivAQing.univaq.it/emc-chap-it/download/swaminathan_laquila_emc.pdf · School of Electrical and Computer Engg. ... ( 4u)/ h ∇ T i j = i j−

Greetings from

Managing Power IntegrityStatus, Challenges and Opportunities

Managing Power IntegrityStatus, Challenges and Opportunities

IPC and Georgia TechIPC and Georgia Tech

Madhavan Swaminathan

Joseph M. Pettit Professor in Electronics

School of Electrical and Computer Engg.

Director, Interconnect and Packaging Research Center

Georgia Institute of Technology May 2011

OutlineOutline

� Motivation

� Overview of the past (Boring)

� Challenges and Opportunities for the Future (most Interesting)


Power DistributionMore than a Decade of Innovation with Many More to Come

Power DistributionMore than a Decade of Innovation with Many More to Come

96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17

Gig

abit

and

Terab

it Era

� I/O Power Distribution� Return Path Discontinuities� Will the Low Target

Impedance concept stillwork ?

Year

Inte

gra

tion

+C

om

ple

xity

+C

ost

Target Impedance

Concept

Megabit and Gigabit Era

� Core Power Distribution� Low Target Impedance� SMT Capacitors� Power Distribution Tools


Signal Wires

PCB or Module

Active Device (IC)

Package

Core Circuits

(Communication within IC)I/O Circuits

(Communication outside IC)

Current

Vdd

Gnd

SSN

SSN in High-Speed / High-I/O Packages and High-Speed Boards

SSN in High-Speed / High-I/O Packages and High-Speed Boards


Power Distribution Affects Operating FrequencyPower Distribution Affects Operating Frequency

Reliability Wall

50MHz

Increase

In FMAX

+/- 100mV

+/- 50mV

1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80

825

785

745

705

665

625

FMAX (MHz)

VCC (V)


SSN causes JitterSSN causes Jitter

Uncertainty in Delay due to SSN causing Jitter

Varying Voltage Droop

on Power Supply dueto SSN

time

Output driver waveform

Vdd

Courtesy: Sony


MHz GHzFrequency

Pow

er/G

rou

nd

Net

wo

rk I

mp

eda

nce

Inductance by

VRM or

ESL of Bulk Capacitor

Capacitance given by

Discrete Decoupling Capacitors

Inductance given by

• ESL of Discrete Capacitor

• Mount Pad

• Power/Ground Traces

• Power/Ground Via

Capacitance by

Power/Ground Plane

Inductance by

Power/Ground Plane

& Pkg Via

KHz

Chip Decoupling

Capacitor

VRM

Power

Ground

Courtesy: Prof. J. Kim, KAIST, S. Korea and Ansoft Corporation

Impedance Vs Frequency and the role of various componentsImpedance Vs Frequency and the role of various components

in the Power Delivery Networkin the Power Delivery Network

Resonance

Anti-resonance

On-chip

CapacitanceTarget Impedance


DC Modelingof PDN

CAD Layoutof Packageand PCB

Acceptable Output Eye

Diagram

AC Modeling ofSignal and

Power Distribution

Macro-modeling

TransientSimulation

Evaluate Layout- Signal RL and IL- Substrate Coupling- PDN Impedance

- SSNEvaluate DC Drops- Voltage distribution

Create� Spice Sub-circuitof frequency response

Evaluate Drv/Rcv Path- Driver Non-linearity- Eye Diagrams

- Timing Margin

- Voltage Margin

Fix DC Drop

Fix Frequency

Response

FixVoltage &TimingMargin

Signal and Power

Integrity Modeling

Signal and Power

Integrity Modeling

Frequency Domain

Frequency to

Time Conversion

Time Domain

Courtesy: E-System Design

(www.e-systemdesign.com)


Multi-layered Finite Difference Method (M-FDM) High Frequency Signal and Power Integrity Analysis

Multi-layered Finite Difference Method (M-FDM) High Frequency Signal and Power Integrity Analysis

zT dJjuk ωµ−=+∇ )( 22

2

,,1,11,1,,

2 /)4( huuuuuu jijijijijijiT −+++=∇ +−+−

h

h

ui,j ui-1,j

ui,j+1

ui,j-1

ui+1,j

� Helmholtz Equation (Differential Form)

� Five point Finite Difference Approximation

R2

C2

L2

G2

R1

C1

L1+L2

G1L1+L2

R2

L2

R1

L1+L2

R2

L2

R1L1+L2

R2L2

L2

L2

L2

L2

Plane 1

Plane 2

Plane 3

L1

L2

Loop Inductance 1

Loop Inductance 2

United States Patent 7,895,540, 2/22/11


Coupling to Signal linesCoupling to Signal lines� Proprietary Signal Referencing Method

� Preserves sparse matrix

� Model return currents and coupling

Signal

Power

Ground

ε1

ε2

ε1

ε2

Signal

Ground

Power

ε1

ε2

Power

Signal

Ground

h2

h1

Courtesy: E-System Design (www.e-systemdesign.com)


64 bit32 bit

32mm 6 lyrFC Pkg

44mm 10 lyr

FC Pkg

Scalability, Memory and Timing

Note: Time per frequency point Sphinx for Signoff: www.e-systemdesign.com


Nets Measured

IBM 8 Layer Flip Chip PackageIBM 8 Layer Flip Chip Package

� Objectives

� Correlate Risetime, Delay

NEXT and FEXT for the IBM

Package

� All measurements done by IBM

using TDR with top and bottom

side probing

Courtesy: Alina Deutsch and Jason Morsey

IBM Yorktown Heights


Measurement Set-upMeasurement Set-up

� TDR/TDT Set-up with 40ps pulse transition

� High Frequency probes and cables usedCourtesy: Alina Deutsch and Jason Morsey

IBM Yorktown Heights


FEN

-4.0E-03

-2.0E-03

0.0E+00

2.0E-03

4.0E-03

6.0E-03

8.0E-03

1.0E-02

1.2E-02

1.4E-02

1.6E-02

0.E+00 5.E-10 1.E-09 2.E-09 2.E-09 3.E-09 3.E-09 4.E-09 4.E-09 5.E-09 5.E-09

Time (s)

Vo

lta

ge

(V

)

Measured

Simulated

Reflection

FEXT

12.1mV13.3mVFEXT Amplitude

SphinxMeasurementParameter

Far End Cross Talk (FEXT)Model to Hardware Correlation

Far End Cross Talk (FEXT)Model to Hardware Correlation


2007 2009 2013-2015 2015-2018 >2018

3D

Inte

rco

nnec

t C

om

ple

xit

y

Consumer

(Camera..)

CMOS ImageSensor

Digital Processor Consumer

(Mobile Phones..)

3D SRAM and

DRAM

Sensor on Logic

Low Power/Low Density

Multi-core CPU

Stacked Cache Memory

Multi-core CPU With Stacked

Memory

Consumer/ComputingMobile Phones

Networking

GPU

Multi-core/Server

Low/High Power/High Density/Multi-Functional

3D Integration

Multi-Level

System Integration

3D Multi-functional

Vertical Integration

Consumer/Computing/Bio/Sensing/RF

Interconnect and Packaging Center: Vision and Roadmapto Achieving Integration using 3D IC and Packaging Technologies

Major Driver


Mechanical Stresses

Joule Heating/Electro-migration

Thermal ManagementPower Delivery/DC/AC

Signal Integrity

Place & Route

Multi-physics and

Multi-scale

Environment

For the DesignOf Heterogeneous

Systems

ECE ME ME ECE

Coupling of Electrical, Thermal Coupling of Electrical, Thermal

and Mechanical Effectsand Mechanical Effects

A MultiA Multi--Physics and MultiPhysics and Multi--scale scale

ChallengeChallenge


Conductor (10um dia) Thin oxide layer (<1um)

Lossy silicon

substrate

100um

10-30um

Commercial Tools will choke due to the multi-scale geometries of these structures

Electromagnetic Modeling of Electromagnetic Modeling of TSVsTSVs

MultiMulti--scale Challengescale Challenge


� Uses Cylindrical

Basis Functions – CMBF, AMBF,PMBF

� Solves Electric Field Integral Equation

� Uses Acceleration Methods

� Computes frequency dependent RLGC parameters

� Computes accurate coupling and loss occurring due to

proximity effect

� Computes hot spots (current distribution)

� TSV position can be arbitrary

Modeling of Modeling of TSVsTSVs using an Integral Equation Based using an Integral Equation Based MeshlessMeshless ApproachApproach


Using Modal Basis Functions to Extract Electromagnetic Using Modal Basis Functions to Extract Electromagnetic

Properties of Properties of TSVsTSVs

×1

×5.0

×5.0

SE mode

PE-d mode

PE-q mode

Resultant current

density distribution

×1

×5.0

×5.0

SE mode

PE-d mode

PE-q mode

Resultant current

density distribution

-1.5 -1 -0.5 0 0.5 1 1.5

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5 -1 -0.5 0 0.5 1 1.5

-1.5

-1

-0.5

0

0.5

1

1.5

Skin and Proximity Effect Modes

Polarization Effect Modes

Fundamental

1st Mode 2nd Mode

Ref: K. J. Han and M. Swaminathan, “Inductance and Resistance

Calculations in Three-Dimensional Packaging using

Cylindrical Conduction Mode Basis Functions”, IEEE Trans. on

Computer Aided Design of Integrated Circuits & Systems, ‘09


conductor series

resistance Conductor self

and mutual

inductances

TSV RLGC Parameter Extraction

Problem due to

increased conductance

(leakage)

Conductance

CapacitanceTSV Structure

L=100um

D=30um

P=60umGrounded Substrate

K. J. Han, M. Swaminathan and T. Bandhyopadyay, “Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections using Cylindrical Modal Basis Functions”, IEEE Trans. on Advanced Packaging, 2010


1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

diameter=20um pitch=50umheight=200um

S12

S13

S15

S1_25

1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

diameter=20um pitch=50umheight=200um

S12

S13

S15

S1_25

�TSV array Coupling- 5x5 TSV array

- Length: 200um

- Diameter:20um

- Pitch: 50um

- Oxide thickness: 0.1um

� Mutual Coupling between TSVs

- Mutual coupling reduced with increasing distance- But doesn’t Vanish

Coupling between TSVs – The Variability Problem


� Coupling waveform at different TSVs (10S/m)- the amplitude of the coupling waveform decrease with distance

- the time constant of the waveform increase with distance� Configuration

- A voltage pulse is applied at TSV-1

- Pulse Rise and Fall time : 100ps

- Substrate conductivity: 10 S/m or 0.01 S/m

0 0 .1 0 . 2 0 .3 0 . 4 0 .5 0 . 6 0 .7 0 . 8 0 .9 1

x 1 0- 8

-0 . 0 2

0

0 . 0 2

0 . 0 4

0 . 0 6

0 . 0 8

0 .1

Vo

ltag

e (

V)

T I M E

T S V - 2T S V - 2T S V - 2T S V - 2

T S V - 7T S V - 7T S V - 7T S V - 7T S V - 2 5T S V - 2 5T S V - 2 5T S V - 2 5

1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

50 Ohm

50 Ohm

Voltage: 2V

1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

50 Ohm

50 Ohm

Voltage: 2V

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

x 10-9

-0.005

0

0.005

0.01

0.015

0.02

0.025

Vo

lta

ge

(V

)

T IME

TSV-2TSV-2TSV-2TSV-2TSV-7TSV-7TSV-7TSV-7

TSV-25TSV-25TSV-25TSV-25

� Coupling waveform at different TSVs (0.01S/m)- the amplitude of the coupling waveform decrease with distance

- the waveforms decay much faster in high resistivity substrate

Crosstalk Waveforms – Low Vs High Resistivity Si

The Long Tail Problem �


50 Ohm

Random bit 101001….

50 Ohm

50 Ohm


50 Ohm

50 Ohm


50 Ohm


50 Ohm


50 Ohm

1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

1 2 3 4 5

6 7 8 9 10

11 12 13 14 15

16 17 18 19 20

21 22 23 24 25

0 0.5 1 1.5 2 2.5 3 3.5 4

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

Time (seconds)

Voltage (

V)

Eye Diagram of TSV-1

Eye height 2.01V

Jitter: 6.86ps

0 0.5 1 1.5 2 2.5 3 3.5 4

x 10-10

-0.5

0

0.5

1

1.5

2

2.5

3

Time (seconds)

Vo

lta

ge

(V

)

Eye Diagram of TSV-13Eye Diagram of TSV-13Eye Diagram of TSV-13Eye Diagram of TSV-13

Eye height: 1.8VJitter: 8.19ps

� Configuration- Each TSV is connected with a Random bit generator

- Bit sequences applied are different for each TSV- Bit rate: 5Gbps- Substrate conductivity: 10 S/m

Variability in TSV Performance

All TSVs switching with a PRBS


Design of PDNsDesign of PDNs

PCB power delivery network

Currently Practiced design

approach

Achieve a low-impedance path from the power supply to the die

ZPDN < Ztarget noise voltage < Vripple

avgI

rippleV

targetZ =

DDV

avgP

avgI =


Two Sides of a Power PlaneTwo Sides of a Power Plane

• Forms a cavity resonator

• Induces return path discontinuity

• Requires decoupling capacitors

• Needs computationally expensive

design procedures

• Provides low-impedance paths

Pros Cons

A new approach for PDN design is needed!


Vdd

Zo

Zo

TxPwr

Package

RxPwr

+

-

Package

Package

Package

Transmitter

Receiver

Ground Plane

Power Plane

Signal transmission line

Conventional Power Delivery NetworkConventional Power Delivery Network

� Return path discontinuity (RPD)

Return current

Return path

discontinuity

Cavity modesCavity modes

Signal current


� Transmission lines replace the power plane to convey power

� reduce the layer count

� remove the effect of cavity mode resonance

� Both the power and signal transmission lines are referenced to the same

ground plane

� prevent the RPD (THIS IS A HIGH IMPEDANCE PDN)

Power Transmission Line (1)Power Transmission Line (1)

*PTL : Power Transmission

Line

*

*

A. E. Engin and M. Swaminathan, “Power Transmission Lines: A New Interconnect Design to Eliminate Simultaneous

Switching Noise,” in Proc. ECTC, pp. 1139-1143, 2008


Power Transmission Line (2)Power Transmission Line (2)

Signal Current

Return

Current

Closed current loop


Limitation of Power Transmission Line(1)Limitation of Power Transmission Line(1)

� DC drop on PDN due to DC resistance

¾Vdd

½Vdd

IR drop data_in=0 data_in=1

Vdd

No current

Yikes

Power Supply Noise

Still exists


Limitation of Power Transmission Line(2)Limitation of Power Transmission Line(2)

� Impedance mismatch in PTL

� Line congestion issue

�� I/O driver per PTL will double the # of lines on PCB


Limitation of Power Transmission Line (3)Limitation of Power Transmission Line (3)

� Varying DC Level on PDN when extended to multi-bit I/Os

Cas

e

Data Pattern Eye Height

data1_tx data2_tx data1_tx data2_tx

1 High High 1V 1V

2High Low 1.25V 0

Low High 0 1.25V

3 Low Low 0 0

IPTL

IR drop

Eye height varies


Constant Current PTL (1)Constant Current PTL (1)

data_in=1

IR drop

data_in=0

Induces the same

amount of current

when data_in=1

Dummy path

IR drop


Constant Current PTL (2)Constant Current PTL (2)

� Constant current power transmission line (CC-PTL)

Constant current

through PTL

Constant IR drop

over PTL

Constant voltage

at TxPwr node

Continuously

charged PTL

No mismatch

effect

No Power supply Noise


Test VehiclesTest Vehicles

Via to power plane

Via to ground plane

2.6”-long

Dummy path

Driver

Via to ground plane

2.6”-long

Dummy path

Power transmission line

Driver

PTL-based test vehicle

Power-plane-based test

vehicle


Modeling and SimulationModeling and Simulation

Modeling in frequency domain Converted to Macromodel

Power-plane-based

TV

PTL-based TV

SPICE simulation setup

1st resonant frequency =

750MHz

1.5Gbps

Eye height improves by 19.6%

Jitter improves by 58%


Measurement SetupMeasurement Setup

Measurement setup

Dummy path

1.5Gbps

� The dummy path is implemented outside the chip due to the limitation of using an

off-the-shelf chip

� AC coupling capacitor is used

• to suppress the DC current flow

• to provide bias for the oscilloscope


With Source TerminationWith Source Termination

Plane-based TV CCPTL-based TV

Signal generator output

Eye height P-P jitter

Power plane 430mV 39.1ps

CCPTL 495mV 24.9ps

Improvement 15.1% 36.3%

• The supply voltage of 2.5V is used for the plane-based TV, while 3.47V is used for the

PTL-based TV.


Without Source TerminationWithout Source Termination

Plane-based TV CCPTL-based TV

Signal generator output

Eye height P-P jitter

Power plane 463mV 36ps

CCPTL 546mV 27ps

Improvement 17.9% 25%

• The same supply voltage of 2.5V is used for both test vehicles.

• Mismatch between the signal line and load termination is negligible so that the

source termination could be omitted.


RMS and P-P Jitter ComparisonRMS and P-P Jitter Comparison

� PTL: Both RMS and P-P Jitters have relatively monotonic behavior.

� Power plane: Both RMS and P-P Jitters have non-monotonic behavior,

having local peak values at the frequencies of power/ground plane

resonances.


Summary for Power Transmission LineSummary for Power Transmission Line

� The first demonstration of the CCPTL scheme has been presented –

A High Impedance PDN based concept

� Reduces decoupling capacitors required (not shown)

� Simulations are done to model the test vehicle in both frequency and

time domains.

� Based on measurements, using the CCPTL scheme

o improves the eye height by 15.1% and p-p jitter by 36.3% with source termination

o improves the eye height by 17.9% and p-p jitter by 25% with source termination

• The power consumption issue needs to be addressed

• This is being addressed through Constant Voltage Power Transmission

Line concept – ongoing work

Georgia Institute of Technology Mar 2011

epsilonlab.ece.gatech.edu

Mixed Signal Design Group @ GT

Documents

Greetings from IPC and Georgia Tech - UnivAQing.univaq.it/emc-chap-it/download/swaminathan_laquila_emc.pdf · School of Electrical and Computer Engg. ... ( 4u)/ h ∇ T i j = i j−