Group 1Group 1chapter 3chapter 3

Alex FranciscoAlex FranciscoMario PalominoMario Palomino

Mohammed Ur-RehmanMohammed Ur-RehmanMaria LopezMaria Lopez

Table of ContextTable of Context

What’s a Program?What’s a Program? Components of 68HC711Components of 68HC711 Fetch cycle & Execute cycleFetch cycle & Execute cycle Interrupts & Multiple InterruptsInterrupts & Multiple Interrupts ConnectionsConnections Bus LinesBus Lines

What is a program?What is a program?

A sequence of stepsA sequence of steps For each step, an arithmetic or logical For each step, an arithmetic or logical

operation is doneoperation is done For each operation, a different set of control For each operation, a different set of control

signals is neededsignals is needed

Components of the 68HC711Components of the 68HC711

Central Processing Unit is made up by the Central Processing Unit is made up by the Control Unit and the Arithmetic and Logic UnitControl Unit and the Arithmetic and Logic Unit

Data and instructions need to get into the Data and instructions need to get into the system and results outsystem and results out– Input/outputInput/output

Temporary storage of code and results is Temporary storage of code and results is neededneeded– Main memoryMain memory

Function of Control UnitFunction of Control Unit

The control unit is the circuitry that controls The control unit is the circuitry that controls the flow of data through the processor, and the flow of data through the processor, and coordinates the activities of the other units coordinates the activities of the other units within it. within it.

In a way, it is the "brain within the brain", as In a way, it is the "brain within the brain", as it controls what happens inside the it controls what happens inside the processorprocessor

Computer Components:Computer Components:Top Level ViewTop Level View

Instruction CycleInstruction Cycle

Sequence of actions that the central Sequence of actions that the central processing unit (CPU) performs to execute processing unit (CPU) performs to execute each machine code instruction in a program. each machine code instruction in a program.

Two steps:Two steps:– Fetch & ExecuteFetch & Execute

Fetch CycleFetch Cycle Program Counter (PC) holds address of next Program Counter (PC) holds address of next

instruction to fetchinstruction to fetch Processor fetches instruction from memory Processor fetches instruction from memory

location pointed to by PClocation pointed to by PC Increment PCIncrement PC

– Unless told otherwiseUnless told otherwise Instruction loaded into Instruction Register (IR)Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs Processor interprets instruction and performs

required actionsrequired actions

Fetch Cycle CommandFetch Cycle Command

Mov PC, MARMov PC, MAR

Increment PCIncrement PC

Mov RAM, MDRMov RAM, MDR

MOV MDR, IRMOV MDR, IR

Execute CycleExecute Cycle Processor-memoryProcessor-memory

– data transfer between CPU and main memorydata transfer between CPU and main memory Processor I/OProcessor I/O

– Data transfer between CPU and I/O moduleData transfer between CPU and I/O module Data processingData processing

– Some arithmetic or logical operation on dataSome arithmetic or logical operation on data ControlControl

– Alteration of sequence of operationsAlteration of sequence of operations– e.g. jumpe.g. jump

Combination of aboveCombination of above

Instruction Cycle State DiagramInstruction Cycle State Diagram

Interrupt CycleInterrupt Cycle Added to instruction cycleAdded to instruction cycle Processor checks for interruptProcessor checks for interrupt

– Indicated by an interrupt signalIndicated by an interrupt signal If no interrupt, fetch next instructionIf no interrupt, fetch next instruction If interrupt pending:If interrupt pending:

– Suspend execution of current program Suspend execution of current program – Save contextSave context– Set PC to start address of interrupt handler routineSet PC to start address of interrupt handler routine– Process interruptProcess interrupt– Restore context and continue interrupted programRestore context and continue interrupted program

Transfer of Control via InterruptsTransfer of Control via Interrupts

Instruction Cycle with InterruptsInstruction Cycle with Interrupts

Instruction Cycle (with Interrupts) Instruction Cycle (with Interrupts) - State Diagram- State Diagram

Multiple InterruptsMultiple Interrupts Disable interruptsDisable interrupts

– Processor will ignore further interrupts whilst processing Processor will ignore further interrupts whilst processing one interruptone interrupt

– Interrupts remain pending and are checked after first Interrupts remain pending and are checked after first interrupt has been processedinterrupt has been processed

– Interrupts handled in sequence as they occurInterrupts handled in sequence as they occur Define prioritiesDefine priorities

– Low priority interrupts can be interrupted by higher priority Low priority interrupts can be interrupted by higher priority interruptsinterrupts

– When higher priority interrupt has been processed, When higher priority interrupt has been processed, processor returns to previous interruptprocessor returns to previous interrupt

Memory ConnectionMemory Connection

Receives and sends dataReceives and sends data Receives addresses (of locations)Receives addresses (of locations) Receives control signals Receives control signals

– ReadRead– WriteWrite– TimingTiming

Input/Output Connection(1)Input/Output Connection(1)

Similar to memory from computer’s Similar to memory from computer’s viewpointviewpoint

OutputOutput– Receive data from computerReceive data from computer– Send data to peripheralSend data to peripheral

InputInput– Receive data from peripheralReceive data from peripheral– Send data to computerSend data to computer

Input/Output Connection(2)Input/Output Connection(2)

Receive control signals from computerReceive control signals from computer Send control signals to peripheralsSend control signals to peripherals

– e.g. spin diske.g. spin disk Receive addresses from computerReceive addresses from computer

– e.g. port number to identify peripherale.g. port number to identify peripheral Send interrupt signals (control)Send interrupt signals (control)

CPU ConnectionCPU Connection

Reads instruction and dataReads instruction and data Writes out data (after processing)Writes out data (after processing) Sends control signals to other unitsSends control signals to other units Receives (& acts on) interruptsReceives (& acts on) interrupts

BusesBuses

A Bus is a communication pathway A Bus is a communication pathway connecting two or more devices.connecting two or more devices.

SYSTEM BUSSYSTEM BUS

A system bus connects major computer A system bus connects major computer components such as processor, memory, components such as processor, memory, I/O. I/O.

The most common computer The most common computer interconnection structures are based on the interconnection structures are based on the use of one or more system buses.use of one or more system buses.

SINGLE BUS STRUCTURESINGLE BUS STRUCTURE Data BusData Bus – – Carries dataCarries data _ _ Remember that there is no difference between “data” andRemember that there is no difference between “data” and “ “instruction” at this levelinstruction” at this level – – Width is a key determinant of performanceWidth is a key determinant of performance 8, 16, 32, 64 bit8, 16, 32, 64 bit Address BusAddress Bus – – Identify the source or destination of dataIdentify the source or destination of data – – e.g. CPU needs to read an instruction (data) from a givene.g. CPU needs to read an instruction (data) from a given location in memorylocation in memory – – Bus width determines maximum memory capacity of systemBus width determines maximum memory capacity of system e.g. 8080 has 16 bit address bus giving 64k address spacee.g. 8080 has 16 bit address bus giving 64k address space Control BusControl Bus – – Control and timing informationControl and timing information Memory read/write signalMemory read/write signal Interrupt requestInterrupt request Clock signalsClock signals

BUS INTERCONNECTIONBUS INTERCONNECTION

The bus extends across all of the The bus extends across all of the system components, each which taps system components, each which taps into some or all of the bus lines. The into some or all of the bus lines. The bus uses a number of electrical bus uses a number of electrical conductors or metal lines etched in a conductors or metal lines etched in a card or board.card or board.

SINGLE BUS PROBLEMSSINGLE BUS PROBLEMS

WHEN A NUMBER OF DEVICES WHEN A NUMBER OF DEVICES ARE CONNECTED TO THE BUS, ARE CONNECTED TO THE BUS, PERFORMANCE IS AFFECTED:PERFORMANCE IS AFFECTED:

Propagation delay: the greater the bus Propagation delay: the greater the bus length the greater the propagation delay.length the greater the propagation delay.

It can be overcome by using multiple bus or It can be overcome by using multiple bus or use wider bus ( e.g., increasing the data bus use wider bus ( e.g., increasing the data bus form 32 bits to 64 bits )form 32 bits to 64 bits )

HIGH SPEED BUSESHIGH SPEED BUSES

The traditional bus architecture is The traditional bus architecture is reasonably efficient but begins to reasonably efficient but begins to breakdown as higher and higher breakdown as higher and higher performance is seen in the I/O devices.performance is seen in the I/O devices.

In response to these growing demands In response to these growing demands high speed buses were build requiring high speed buses were build requiring only a bridge between the processor only a bridge between the processor bus and the high-speed bus.bus and the high-speed bus.

HIGH SPEED BUS HIGH SPEED BUS

BUS TYPESBUS TYPES DedicatedDedicated

– Separate data & address linesSeparate data & address lines MultiplexedMultiplexed

– Shared linesShared lines– Address valid or data valid control lineAddress valid or data valid control line– Advantage - fewer linesAdvantage - fewer lines– DisadvantagesDisadvantages

More complex controlMore complex control Ultimate performanceUltimate performance

Review QuestionsReview Questions1)1) Define what a program is?Define what a program is?2) The Control Unit and the Arithmetic and Logic Unit are 2) The Control Unit and the Arithmetic and Logic Unit are

part of________part of________3) What is the first step of the Fetch sequence?3) What is the first step of the Fetch sequence?4) What is the second step of the Fetch sequence?4) What is the second step of the Fetch sequence?5) What is the third step of the Fetch sequence?5) What is the third step of the Fetch sequence?6)6) What is the final step of the Fetch sequence?What is the final step of the Fetch sequence?7)7) What is an Interrupt?What is an Interrupt?8)8) How many Bus lines does a 68HC711 have?How many Bus lines does a 68HC711 have?9)9) How many bits does a 8 bus lines have?How many bits does a 8 bus lines have?10)10) What is a bus?What is a bus?