Hardware Acceleration

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Hardware AccelerationHardware Acceleration

February 2006February 2006

Proprietary and Confidential Inform

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The ProblemThe Problem

1. Verification tools have not kept pace with the incredible rate at which design sizes are growing.2. Each verification stage has its own methodology, tools, models and user inteface.3. Embedded Software debug/integration is started late after first silicon/prototype.

System-on-a-chip verification, 2001 – P.RashinkarDesign complexity


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Simulation

HardwareAcceleratedSimulation

Emulation

FormalVerification

Semi-formalVerification

Prototyping

Faster speed, closer to final product

Bigger coverage

Basicverificationtool

MethodologiesMethodologies


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Hardware-Accelerated SimulationHardware-Accelerated Simulation

• Simulation performance is improved by moving the time-consuming part of the design to hardware.

• Usually, the software simulation communicates with FPGA-based hardware accelerator.

Simulation environment

Testbench

Module 0

Module 1

Module 2

Hardware Accelerator

Module 2 is synthesized &compiled into

FPGAs


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Pros Fast (100K cycles/sec) Cheaper than hardware emulation Debugging is easier as the circuit structure is unchanged. Not an Overhead : Deployed as a step stone in the gradual refinement

Cons (Obstacles to overcome) Set-up time overhead to map RTL design into the hardware can be

substantial. SW-HW communication speed can degrade the performance. Debugging of signals within the hardware can be difficult.

Hardware-Accelerated SimulationHardware-Accelerated Simulation


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EmulationEmulation

Imitating the function of another system to achieve the same results as the imitated system.

Usually, the emulation hardware comprises an array of FPGA’s (or special-type processors) and interconnection scheme among them.

About 1000 times faster than simulation.

Simulation

HardwareAcceleratedSimulation

Emulation

Prototyping


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EmulationEmulation

User logic design is mapped to emulation board with multiple FPGA’s or special processors.

The emulation board has external interconnection hardware that emulates the pins of final chip.

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&

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Logic design Emulation hardware with multiple FPGAs

Design mapping

External pins


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EmulationEmulation

Pros Fast (500K cycles/sec) Verification on real target system.

Cons Setup time overhead to map RTL design into hardware is very

high. Many FPGA’s + resources for debugging

high cost Circuit partitioning algorithm and interconnection architecture

limit the usable gate count.


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PrototypingPrototyping

Pros Higher (than emulation) clock rate (over 1M cycles/sec) due to

specific design of prototyping board. Components as well as the wiring can be customized for the

corresponding application. Can be carried along. (Hardware Emulation? Forget it!)

Cons Not flexible for design change (Every new prototype requires a new board architecture. / Even

a small change requires a new PCB.)

Special (more dedicated and customized) hardware architecture made to fit a specific application.


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SurveySurvey

HW emulators/accelerators

2004 2005

don't use 52% 62%homebrew with FPGAs

20% 14%

Cadence Palladium 11% 14%Verisity Axis 7% 5%Mentor IKOS/Celaro/Vsta

5% 8%

Other 5% 5%

Does your company use HW emulators/accelerators like Cadence Quickturn Palladium, Mentor IKOS/Meta Systems, Verisity Axis, Tharas, Pittsburgh Simulations, EVE, or Aptix? (10/25/05 )

Resource : http://www.deepchip.com/items/dvcon05-15.html


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ProductsProducts

Simulation acceleration and in-circuit emulation in one system natively supports Verilog, VHDL, System Verilog, SystemC, SystemC

Verification Library, OVL, and PSL/Sugar assertions. Dynamic probes/events allow interactive debug during run-time Comprehensive verification with "live" data Support for assertions in hardware with no performance degradation High Capacity -

Provides up to 100x-10,000x RTL performance ( run four days of simulations over lunch at 100x).

Compiles up to 30 million gates per hour on a single workstation Maximum capacity of 256 million gates Supports up to 32 users in local or remote access Highest throughput for HW/SW co-verification

Cadence - PALLADIUM


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ProductsProducts

Mentor - VStationTBX

Single verification environment for simulation and verification High-performance verification accelerator for designs and testbenches Built on standard languages: SystemC, SystemVerilog, C/C++ Behavioral Verilog testbench and memory compiler VHDL and Verilog RTL debug HDL acceleration 10x-100x faster than co-simulation Accelerates the entire design process with advanced techniques, such as

assertions and transactions


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ProductsProducts

Support SpeXtreme - direct compilation of e testbenches Multi-Purpose –

Seamlessly integrates emulation, acceleration, and simulation into a single verification environment

Provides a configurable platform for early system-level integration Emulates behavioral objects with reconfigurable behavioral processors

High Capacity - Supports designs of up to 50M ASIC gates Provides memory of up to 12 GB Supports up to 4,656 IOs Allows up to 12 simultaneous users

Easy-to-Use - Preserves native simulation debugging environment by supporting all HDL constructs, PLI calls, and testbenches

Verisity - Xtreme Server


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ProductsProducts

Verisity - SpeXtreme


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Other solutionOther solution

Homebrew with FPGAs – Partition design to number of FPGAs. Use FPGA on-chip processors or configurable processors to drive

testbench.

Pros Low cost solution. fast

Cons Most embedded processor compilers supports C/C++ languages. Requires two verification environments. Need to establish debug connection between WS and FPGAs


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ConclusionsConclusions

Hardware Acceleration/Emulation

Simulation Acceleration

Verification Acceleration

Project Acceleration


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Thank youThank you

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Hardware Acceleration