High Speed Electronic Circuits

High Speed DAC

Presented by

Ahmed Elsiginy 28-6282

Mostafa Elswefy 28-4174

Mohamed Elhadad 28-4067

1

Few definitions Nyquist Criteria Minimum sampling rate=2*signal frequency Sampling rate=number of samples/sec DAC settling time: The time it takes for the DAC to settle to within some specified amount of the final value (the time it takes to convert from digital to analogue) So high speed DACs require high sampling rates and slow settling time

The basic concept

Binary Stream bn…………..b0

01

11

00

10

……

……

……

.

DAC

Vout=2^n*bn……… +2^2 *b2+2^1*b1+2^0*b0

The basic concept …. cont

Binary Stream bn…………..b0

01

11

00

10

……

……

……

.

Adder

Vout=2^n*bn……… +2^2 *b2+2^1*b1+2^0*b0

2^n--------2^0

Switches

First Design[Hamade,1978] Input Nodes with different voltages drops Are selected to form all possible combinations 8(2^3) in this case as we use a 3 bit binary input word (only one path will be connected to the buffer)

Disadvantages of the Design

The main disadvantage of the design is number of selection transistors increases drastically with increasing the number of bits, thus adding more delay and power To realize the delay of such design. Elmore delay calculations is used There also many other disadvantages like the very large switching power loss due to the large number of transistors used.

Delay calculations

Delay calculations….cont

Let’s assume very small design parameters: C=1pF , R=100Ω and only 16 bits used, by calculating the t=7τ, we get a value of around 90ns. Is such delay suitable for High-speed applications in ranges of GHZ ? The answer is no! Remember that the sampling rate must be at least twice the frequency, so sampling of GHz ranges is not achievable by such delays So we are going to look for other designs

Binary weighted resistors DAC

Instead of scaling voltages as in the previous design, we scale the resistors But what are the advantages and the disadvantages of such design ?

Inverting amplifier

Vout=(−𝑅𝑓

𝑅𝑖𝑛)*Vin Rin

Binary weighted resistors DAC

Advantages: Only n switches used not 2^n switches, which in turns reduce the delay time and the power losses.(more suitable for High-speed designs) Disadvantages: Large current ratios require the switches(transistors) To be scaled too (more complex design), in addition to the problem of glitches in high-speed operations I1 and I2 here represent the switching current Flowing through the resisters, as the resistors are scaled with different Values, there will be a delay from the switching the MSB compared to the LSB, making a gap of no current which is called a glitch.

Binary weighted resistors DAC To avoid scaling resistors with large different values a small enhancement is proposed

Where a series resistances are added to scale the voltage too and get the same ratios as Before. Note that, by repeating this procedure recursively, one arrives at a structure commonly referred to as R-2R ladder, described next

R-2R ladder DAC

Still the currents are different in each branch so we still have to scale the switches (transistors).

Binary-array charge-redistribution DAC

One could also think of using capacitors instead of resistors to make the same scaling ratios, but the design of the switching signals must be design carefully

Problem Solving

Problem(1) description

• For a computer or other digital device to interface with external analog circuits and devices, a digital-to-analog converter (DAC) is required. The most common DAC is a R-2R resistor ladder network, which requires only two precision resistor values R and 2R.

• A 4-bit R-2R resistor ladder network is shown below:

Problem(2) Description Cont’d

• The digital input to the DAC is a 4-bit binary number represented by bits b0, b1, b2 and b3, where b0 is the least significant bit (LSB) and b3 is the most significant bit (MSB).

• Each bit in the circuit controls a switch between ground and the inverting input op amp.

• When a bit is 1, the corresponding switch is connected to the op-amp; when a bit is zero, the corresponding switch is connected to ground.

a) determine the voltage levels at V0, V1, V2 and V3 in terms of the source voltage, Vs.

• we assume this is an ideal op-amp, we can analyze the voltage levels in the circuit by removing the op amp.

• Below is a picture of the circuit when all bits are zero:

Part(a) Sol.

b) If we assume that closing switches has negligible effect on the voltage levels we found in part a), what will be the output of the DAC circuit, Vout (in terms of Vs), when the input (b3 b2 b1 b0) is:

• 0001:

• 0010:

• 0100:

• 1111:

Part(b) sol.

• 𝑉𝑜𝑢𝑡 = − 𝑅𝑓

𝑅𝑖𝑛𝑉𝑖𝑛 = −

𝑅

2𝑅𝑉𝑖

• 0001: Vout = -(R/2R)V0 = (-1/2)(Vs/8) Vout = -(1/16)Vs

• 0010: Vout = -(1/8)Vs

• 0100: Vout = -(1/4)Vs

• 1111: Vout = -(1/16)Vs + -(1/8)Vs + -(1/4)Vs + -(1/2) Vs Vout = -(15/16)Vs. (Superposition Technique!)

• c) In terms of Vs, what is the range of the analog output for a 4 bit binary input? (ie. If the input ranges from 0000 to 1111, what is the output range?)

Problem(2)

Solution

Problem (3)

• The configuration of op-amps and resistors shown below can produce an analog output voltage (across the last 100kΩ resistor on the right) equal to the binary word ABCD input at the left. Assume that you are working with TTL devices, so the voltage levels for ones and zeros are TTL levels (0V and 5V). Select values for R1, R2, R3, and R4 so that the output voltage will be the decimal equivalent of ABCD, for any choice of ABCD.

R1 = ?? R2 = ?? R3 = ?? R4 =??

• Your choices of resistors should work for any number, but specifically show that your values work for the two binary numbers ABCD =0110 and ABCD = 1001.

Current mode converters

• Same as resistor-based converters but intended for high-speed applications. • The current is switched to output or to the ground. • 𝑅𝑓 converts the current into voltage.

Disadvantages of current mode converters

1. The matching requirements for achieving good accuracy are very high.

Cont. Disadvantages of current mode converters

2. Glitches: • consider the transition from 011111 to 100000, the MSB current

source turns on and all the remaining bits turn off. If the MSB source turns on a bit earlier(or slower) than the remaining sources turn off, then for a time interval the code 111111(or 000000) will appear before the 100000

Thermometer code converters

• Thermometer code is an equivalent to the binary code.

• It uses 2𝑁 − 1 bits to represent 2𝑁 numbers

Thermometer code converters

• Current in all branches is the same.

• This relaxes the matching requirements substantially.

• Disadv.: As the resolution scales up, the number of elements increases dramatically (e.g. 4095 switched current cells for a 12 bits DAC), not practical for more than 8-bits.

Segmented converters

• Uses thermometer code for the MSB and binary code for the LSB.

High speed segmented converters

• It consists of

1. a digital decoder responsible for

encoding operations for the binary

input data.

2. a delay equalizer that matches coarsely

the delays of binary and thermometer data.

3. circuits that synchronize data with the clock before driving the switches.

4. the current switching network that is driven by the clocked elements.

5. the current source network where the currents are generated.

Current switching and current source

• A cascoded current source configuration and a differential current switch is used

• Dependent on the input bit values the current is driven to one or the other side of the cell

• Adv.: Switching is very fast because the large capacitances associated with the current source terminals stay charged for most of the time.

Clock-data synchronization circuit

• The data signals generated at the output of the decoder are subject to the effects of different logic depths, device process mismatch, interconnect length differences, cross-coupling. These effects cause large waveform shape variations and delays, the clock-data synchronization circuitry generate clear, identical and very accurately synchronized ones.

Clock-data synchronization circuit

Importance of clock-data synchronization circuit: • Allow pipelining (increasing the maximum conversion rate). • Eliminates the unwanted variability of the decoded data waveforms.

(read only)

• You can also check the latest publications on High speed DAC. Some could reach 100GHs like

• Chen, Xi, et al. "All-Electronic 100-GHz Bandwidth Digital-to-Analog Converter Generating PAM Signals up to 190 GBaud." Journal of Lightwave Technology 35.3 (2017): 411-417.

References

• Johns, David A., and Ken Martin. Analog integrated circuit design. John Wiley & Sons, 2008. Chapters 11 and 12

• Doris, Konstantinos, and Arthur van Roermund. "High-Speed Digital to Analog Converters." Analog Circuit Design. Springer Netherlands, 2006. 91-109.

• K. Doris, "High-speed D/A Converters: from Analysis and Synthesis Concepts to IC Implementation", Ph.D. Thesis, Technical University Eindhoven, Sept. 2004.