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© Copyright 2019 Xilinx How FPGAs Have Evolved to Address Compute Acceleration and Interconnects Ken Chang Xilinx at OFC Booth #1811

How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

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Page 1: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

How FPGAs Have Evolved to

Address Compute Acceleration

and Interconnects

Ken Chang

Xilinx at OFC Booth #1811

Page 2: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

Agenda

˃Why FPGA, Adaptable Compute?

˃FPGA to Adaptable Compute Evolution

˃FPGA Transceiver Evolution

˃Summary

>> 2

Page 3: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx>> 3

Compute and Bandwidth Needs Across All Industries

>> 3

CLOUD EDGENETWORK

AI ADOPTION ACROSS MARKETS

EXPONENTIAL DATA BANDWIDTH GROWTH

Page 4: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

The Slowdown of Moore’s Law and Technology Scaling

Processing Architectures are Not Scaling

>> 4

10

100

1000

10,000

100,000 ?

2X / 3.5 Years

2X / 1.5 Years

2X / 6 Years

2X / 3.5 Years

1980 1985 1990 1995 2000 2005 2010 2015

Performancevs. VAX11-780

CISC

RISC

End of DennardScaling

AmdahlsLaw

40 YEARS OF PROCESSOR PERFORMANCE

Source: John Hennessy and David Patterson, Computer Architecture: A Quantitative Approach, 6/e 2018

Page 5: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

FPGA Evolution: From FPGA to SoC to ACAP

>> 5

First FPGA Introduced

First VirtexFPGA

Virtex-2 Pro

First 3D FPGA &

HW/SW

Programmable SoC

First MPSoC& RFSoC

ACAP

1985

2019

1998

2001

2011

2016

Moore’s Law Era SoC Era

Page 6: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx>> 6

˃ Based on 7nm FinFET

˃ Platform Solution for Compute /

Storage / Network Acceleration

˃ IP Subsystems and a Network-on-Chip

˃ Programmable AI Engine

>> 6

Programmable Logic

GPIO & Mem I/F

SerDes HBMRFDAC/

ADC

Application Processors

Real-Time Processors

AI Engine

Next Generation Programmable

Logic

Adaptive Compute Acceleration Platform

Page 7: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

MLInference

5GWireless

Power

7nm ACAP 16nm FPGA

AI Engine

˃ Target Applications

ML Inference for Cloud DC

5G wireless: Radio, Baseband

ADAS/AD Embedded Vision

˃ Each Tile:

ISA-based Vector Processor

(SW programmable, C++, e.g.)

Local Memory

Adaptable, Non-blocking

Interconnect

>> 7

Core

Me

mo

ry

Core

Me

mo

ry

Core

Me

mo

ry

Core

Me

mo

ry

Core

Me

mo

ry

Core

Me

mo

ry

Core

Me

mo

ry

Core

Me

mo

ry

Core

Me

mo

ry

Array Architecture

Source: Juanjo Noguera, “HW/SW Programmable Engine: Increased Compute Density Architecture for Project Everest”, Hot Chips 2018

10x

40%Less

Power

5x

Page 8: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

Industry’s First ACAP: Versal Architecture Overview

>> 8

Network On Chip

Versal

Adaptable

Hardware

Scalar Engines Adaptable Engines Intelligent Engines

Arm Dual-CoreCortex-R5Real-TimeProcessor

Arm Dual-CoreCortex-A72ApplicationProcessor

AI

Engines

DSP

Engines

28G

58G

112GPCIe &

CCIX

(w/DMA)

DDR HBMMultirate

Ethernet

600G

Cores

Direct

RF

MIPI

LVDS

GPIO

Block RAM

UltraRAM

Accelerator RAM

PlatformManagement

Controller

Processing System

7nm FinFET

Page 9: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

ACAP Meets Compute Demands for Cloud, Network, and Edge

>> 9

CLOUD EDGENETWORK

16nmFPGA

7nmACAP

Go

og

leN

et

V1

Im

g/S

ec

(<2m

s)

10X

16nmRFSoC

7nmACAP

Int

16

x1

6 D

SP

Co

mp

ute

(Tera

MA

C/

sec)

5X

16nmFPGA

7nmACAP

Sin

gle

-Chip

Encry

pte

d

Tra

ffic

(G

b/s

)

4X

16nmMPSoC

7nmACAP

ResN

et5

0 im

g/s

ec

(ba

tch

=1

)

15X

Page 10: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

FPGA Transceiver Evolution

Page 11: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

1

10

100

0102030405060708090100110120

Dat

a Ra

te [G

bps]

Process Node [nm]

2006

2007

2008

2009

2010

2011

2012

2013

2014

2015

2016

2017

2018

2019

Backplane Transceiver Trend from Industry

>> 11Data source: ISSCC, VLSI Circuit Symposium

Xilinx

Backplane channel loss: > 25dB

Page 12: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx>> 12

Backplane Transceiver Trend: Date Rate vs Year

>> 12

1

10

100

2006 2008 2010 2012 2014 2016 2018 2020

Data

Rate

[G

bp

s]

Year

56G PAM4

RX

100G FEC

56G PAM4

RX

First 28G LR paper (IBM)ADC based

Page 13: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx>> 13

Backplane Roadmap (From 2012)

˃ Courtesy of E. Wu, “FPGA Optical Connectivity,” OFC Workshop 2012

Page 14: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx>> 14

Backplane Transceiver Trend: Date Rate vs Year

>> 14

1

10

100

2006 2008 2010 2012 2014 2016 2018 2020

Dat

a R

ate

(Gb

/s)

Year

DR [Gb/s]

Roadmap

Page 15: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx>> 15

Electrical vs Optical

>> 15

Ashok Krishnamoorthy, “Optical interconnects in computing and

switching systems: the anatomy of a 20Tbps switch card”, ISSCC 2018

Optical for 200G?

Page 16: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

On-Board Optics Solution

˃ Capable of error free (BER < 10-12) for compute application

˃ Electrical portion (16nm FinFET) based on CEI-56G-NRZ Published in ISSCC 2018

˃ Optical portion based on EAM silicon photonics with Driver/TIA in 16nm FinFET

Submitted to VLSI 2019

>> 16

XSR Example: 50mm, 8dB

Optical EngineASIC / FPGA Fiber1.5dB

PCB

Total Power

per Channel

mW pJ/bit

126 2.25

Page 17: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx>> 17

Optical …

>> 17

1.00E-12

1.00E-11

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

4 6 8 10 12 14 16 18 20 22 24 26

BER

PI Code

Error free at 50Gb/s!

Measured Bathtub 50Gbps

Tx7 Rx4 No EDFA Ext Loop

Xilinx OFC Booth #1811

Page 18: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx>> 18

Transceiver Evolution: the “On Package” Stage

˃ Front Panel Pluggable

˃Mid-Board Optics

˃On Package, Electrically Pluggable

˃On Package, Optically Pluggable

Slide courtesy of

Page 19: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx>> 19

Summary

>> 19

Evolution of Compute BandwidthSurpassed Moore’s Law with New

Architecture

Time

Limits of Moore’s Law

Evolution of Serial I/O BandwidthSurpass Electrical Limits with New

Architecture?

Limits of Electrical Signaling

Compute

(TOPS)

Time

I/O

BW/Package

FPGA ACAP re-architecture

To meet expectations of growth

Optics?

Lo

g s

ca

le

Lo

g s

ca

le

Page 20: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

Acknowledgments

˃ The speaker would like to thank the following people for their valuable

contributions and discussions for the presentationAnthony Torza, Ehab Mohsen, Kees Vissers, Vamsi Boppana, Gaurav Singh, Yohan Frans, Geoff Zhang, Ephrem Wu, Liam Madden

>> 20

Page 21: How FPGAs Have Evolved to Address Compute Acceleration and ... · FPGA Evolution: From FPGA to SoC to ACAP >> 5 First FPGA Introduced First Virtex FPGA Virtex-2 Pro First 3D FPGA

© Copyright 2019 Xilinx

Adaptable.

Intelligent.


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