Virtex-6 Clocking ResourcesBasic FPGA Architecture

Xilinx Training

Objectives

After completing this module, you will be able to:

Detail the clocking resources available in the Virtex-6 FPGA

Specify the resources available in the Clock Management Tile (CMT)

Describe the basics of the PLL capabilities

Clo

ck

Bu

ffe

rsMMCM

MMCM

Clock Wizard Automatic HDL code

Virtex-6 Clock Management

Global clock buffers– High fanout clock distribution buffer

Regional clock distribution (low-skew)

I/O clock routing

Clock regions– Each clock region is 40 CLBs high and

spans half the device

Clock management tile (CMT)– Two PLL-based Mixed-Mode Clock

Managers (MMCMs) in each Clock Management Tile (CMT)

– Up to nine CMTs per device– Performs frequency synthesis, clock

de-skew, and jitter-filtering– High input frequency range (10-800 MHz)

Simple design creation through the Clocking Wizard

MMCM Features

8 independently programmable clock outputs (O0-O6 and CLKFBOUT)

– O0 to O3 and CLKFBOUT offer complementary outputs

Additional MMCM_ADV features– Clock input switching– Phase shift port – Dynamic Reconfiguration Port (DRP)– LOCK circuit enhanced to eliminate

possibility of false LOCK

Both are easily customized with the

Architecture Wizard

MMCM able to implement both DCM and PLL functionality

MMCM able to implement both DCM and PLL functionality

Each MMCM can be invoked with either the MMCM_BASE or MMCM_ADV primitive. SW takes care of unused ports on MMCM_BASE.

CLKIN1CLKFBINCLKIN1CLKFBIN

CLKOUT<6:0>CLKFBOUT

CLKOUT<6:0>CLKFBOUT

MMCM_ADVMMCM_ADV

CLKIN2CLKINSELDRPPhase Shift

CLKIN2CLKINSELDRPPhase Shift

RSTRST LOCKEDLOCKED

CLKIN1CLKFBINCLKIN1CLKFBIN

CLKOUT<6:0>CLKFBOUT

CLKOUT<6:0>CLKFBOUT

MMCM_BASEMMCM_BASE

RSTRST LOCKEDLOCKED

Die View

Clock RegionsClock

Regions

IO Columns

IO Columns

Clock Spine and Column

Clock Spine and Column

MMCM Tiles

MMCM Tiles

HROWsHROWs

BUFIO (Single or

Multi Region)

BUFIO (Single or

Multi Region)

BUFG in Center of

Device

BUFG in Center of

Device

BUFRBUFR

BUFHBUFH

Clocks in “Leaf” Region

Clocks in “Leaf” Region

BUFH Mux Areas

BUFH Mux Areas

Virtex-6 FPGA Clock Distribution

Larger clock region– 40 CLBs high, 40 I/Os high– Same size as I/O bank– Half width of device– 6-18 regions per device

Resources per clock region– 12 global clock networks

• Driven by BUFH

– 6 regional clock networks• Driven by BUFR

– 8 I/O clock networks per I/O column

CLB20

MMCM

CLB20

IOB20

IOB20

MMCM

CLB20

IOB20

CLB20

IOB20

Global Clocking

32 BUFGs reside in the center of the deviceDriven by 8 global clock pins– There are also four clock-capable I/O pins per

I/O bank• Four differential or single-ended• Global clock pins are not the only clock input

resource

BUFGs can be driven by– Global clock inputs– Clock-capable inputs (inner I/O columns only)– MMCM outputs– Other BUFG– Interconnect– BUFR– GTX (recovered clock from GTX)

BUFG outputs can drive the vertical global clock spineBUFGCTRL component implements– Glitch-free clock switching between two sources– Clock enable for disabling clocks

BUFGCTRL

O

S1

S0

IGNORE0

IGNORE1

CE0

CE1

I1

I0

Horizontal Clocking

12 BUFHs per clock region– You should not have to instantiate this

BUFH drives logic via horizontal global clock lines– BUFHs on left and right of vertical spine can

be driven by the same CCIO or MMCM output

Driven by…– MMCM in the same region– BUFG via vertical clock spine– Clock-capable inputs in same horizontal row– Interconnect

Provides control of clocks routed into regions– Power saving by turning off or gating clocks to

specific regions– Isolating logic into regions may require an Area

Constraint

BUFHCE

I

CE

O

BUFH

I O

Regional Clocking

Up to 4 BUFRs per clock region (varies by density)– 2 per I/O bank

Driven by…– Clock-capable inputs– Interconnect– GTX– MMCM high-performance clocks

Can drive…– Logic– IO logic– MMCM– BUFG

For medium- and high-performance clocks driving 1-3 regions (one above, self, and one below)BUFR frequency can be divided by 1…8

BUFR

÷

CLR

I O

CE

I/O Clocking

2 single-region BUFIOs and 2 multi-region BUFIOs in each I/O bank

Driven by…– Clock-capable inputs in the same I/O bank– MMCM outputs via high-performance paths

Can drive…– I/O logic in the same and adjacent I/O

banks– BUFIO can drive logic resources only in the

same I/O column

Intended for clocking high-speed I/O logic

BUFIO

I O

Source-Synchronous Interfaces

I/O and regional clock networks combined with ISERDES/OSERDES provide powerful tools for creating source synchronous interfaces

BUFR is set to ÷N if interface is SDR, or ÷(N/2) if DDR– N can be 2 to 8 in SDR, and 2 to 10 in DDR

Clock-Capable I/O (CCIO)

I/O Clock Buffer (BUFIO)

Conventional I/O (IO)

Regional Clock Buffer (BUFR)

NISERDESISERDES

CLK CLKDIVFPGA FabricFPGA Fabric

CLK

Data

IO

CCIOBUFIO

BUFR

Performance Path Routing

4 performance paths driving each inner/outer left/right IO column

Driven by…– MMCM outputs O0-O3

Can drive…– BUFIO– BUFR– GTX

Powered by a regulated supply within each MMCM– This isolates the clocks from noise on

Vccint– Cleanest path from MMCM to I/O

columns– Lower jitter than any other routing

Software automatically places critical signals onto performance path routing, so don’t worry about controlling this route

MMCM

MMCM

GTXIOIOIOIO

Global Clocking Features

Global Clock Inputs(IBUFG or IBUFGDS)

Global Clock Multiplexers (BUFGCTRL)

Flexibility 8 total – 8 differential (16 pins) or– 8 single-ended (8 pins)

32 total Drive the global clock

networks Optional clock enable Guaranteed glitchless clock

switching

Performance Up to 800 MHz Differential for maximum performance High fanout (access to all clock loads in the FPGA) Low skew Short clock insertion delay

I/O and Regional Clocking

Clock-Capable I/Os I/O Clocks Regional Clocks

Flexibility Exist in all I/O columns 4 CCIOs per I/O bank

– 4 differential (8 pins) or– 4 single-ended (4 pins)

Adjacent to HCLK row– 2 CCIOs above and

below

Exist in all I/O columns

4 BUFIOs per I/O bank

Up to 8 I/O clock networks per I/O bank

Some clocks are local only; some can drive neighboring banks

Exist in all I/O columns

2 BUFRs per I/O bank

6 regional clock networks per region

Span up to three regions (one above and below)

Clock divider range from 1 to 8

Performance 800-MHz differential 800-MHz differential

500 MHz

Virtex-6 Clock Network Summary

Clock regions are 40 CLBs tall

Clock regionsmatch I/O banks

40 I/Os per bank

12 GCLKs (via BUFH) per region

2 BUFRs per I/O bank

2 single region BUFIOs2 multi-region BUFIOs

Clock regionsspan one half the die

Four differential or single-ended clock capable inputs

MMCM Features

Up to 9 CMTs per device– 2 MMCMs per CMT

Two software primitives– MMCM_BASE has only the basic

ports– MMCM_ADV provides access to all

ports

8 independently programmable clock outputs– O0 to O6 plus CLKFBOUT– O0 to O3 and CLKFBOUT true and

complement outputs

Additional MMCM_ADV features– Clock input switching– Phase shift port

CLKIN1CLKFBINCLKIN1CLKFBIN

CLKOUT<6:0>CLKFBOUT

CLKOUT<6:0>CLKFBOUT

MMCM_BASE

RSTRST LOCKEDLOCKED

CLKIN1CLKFBINCLKIN1CLKFBIN

CLKOUT<6:0>CLKFBOUT

CLKOUT<6:0>CLKFBOUT

MMCM_ADV

CLKIN2CLKINSEL

DRPPhase Shift

CLKIN2CLKINSEL

DRPPhase Shift

RSTRST LOCKEDLOCKED

MMCM Internals

Phase / frequency detector compares CLKIN with CLKFB– Accepts up to 650-MHz inputs– Adjusts the charge pump output

voltage higher or lower– Charge pump controls the VCO

frequency

Many different output frequencies can be generated– Fout = Fin * M / (D*O)– One M and one D value per MMCM– Each MMCM output can have its

own O value– M: 1…64; D: 1…80; O: 1…128

VCOLFCPPFD O0

CLKFB

CLKIN1CLKIN2

Routing ClockSwitch

D

CLKINSTOPPED

Lock

CLKFBSTOPPED

StopDetect

LockDetect

9

O1

O2

O3

O4

O5

O6

MCLKFBOUT

HOLD

Extra MMCM Features

Fractional counters– Ability to configure O0 and CLKFBOUT

as counters with 1/8th granularity (e.g. 2.125, 2.250, 2.375, etc.)

– O5 output is disabled when using this feature

– Enables many more frequencies to be synthesized

Two methods of shifting phase– Static phase shift using time-shifted

VCO outputs– Dynamic phase shift using the PS port

to change the phase on the fly in increments of 1/56 of VCO period

0

45

90

135

180

225

270

315

VCOOutputs

O0

O1

O2

O3

O4

O5

O6

CLKFBOUT

Additional MMCM Signals

Complement outputs– O0-O3 of every MMCM have

both true and complement outputs

– Provide 180 degree phase shift

LOCKED– Signal showing that the MMCM has

locked on to the input frequency

CLKINSTOPPED/FBSTOPPED– Status signals indicating that the input or feedback clocks have stopped

running

PWRDWN (not shown)– Disable / Enable signal to the regulated supply of each MMCM

• Unused MMCMs draw power

VCOLFCPPFD O0

CLKFB

CLKIN1CLKIN2

Routing ClockSwitch

D

CLKINSTOPPED

Lock

CLKFBSTOPPED

StopDetect

LockDetect

9

O1

O2

O3

O4

O5

O6

MCLKFBOUT

HOLD

MMCM Connectivity

Many possible inputs to each MMCM – CCIO from inner I/O

columns– Global clock inputs– BUFG– GTX clocks

MMCM outputs drive– BUFG– BUFH in same region– Performance paths to

BUFIO and BUFR (not shown)

MMCM

Clock capable IO(Inner I/O Columns)

GTX clocks

Clock capable IO(Inner I/O Columns)

HROW clock HROW clock

Glo

ba

l C

loc

k in

pu

ts

To B

UF

G

To B

UF

G

To B

UF

G

Fro

m B

UF

G

To B

UF

G

CLKIN1CLKIN2

CLKFBIN

Clock Deskew

Use a BUFG on CLKFBOUT if a precise phase relationship between input clock and output clock is required– Most flexible solution but requires two

global clock buffers

Remove the BUFG on CLKFBOUT if there is no need for a precise phase relationship– Frequency synthesis or jitter filtering

only

IBUFG BUFG

BUFG

CLKIN

CLKFBIN

CLKOUT0

CLKFBOUT

MMCM-to-MMCM Connection

IBUFG

BUFGCLKIN

CLKFBIN

CLKOUT0

CLKFBOUT

BUFG

CLKIN

CLKFBIN

CLKOUT0

CLKFBOUT

CLKOUT1 To Logic

To Logic

MMCMs in the same CMT can be connected without the need for a global clock buffer– Output clock will not be aligned to input

clock

More clock frequencies can thus be generated

MMCM-to-MMCM Connection

IBUFG

BUFGCLKIN

CLKFBIN

CLKOUT0

CLKFBOUT

BUFG

CLKIN

CLKFBIN

CLKOUT0

CLKFBOUT

CLKOUT1

To Logic

To Logic

BUFG

To Logic

MMCMs in the same CMT can be connected without the need for a global clock buffer– Output of first MMCM connected to

CLKIN of second MMCM– BUFG inserted from CLKFBOUT to

CLKFBIN of the first MMCM to align output clock with input clock

– CLKFBOUT of first MMCM can also drive logic

Enables more phase-aligned clock frequencies to be generated

Example

Requirement– 33.3-MHz external oscillator controls

• 533-MHz data being generated by I/O logic (BUFIO)

• Large amount of logic at 66 MHz (BUFG)• Small design at 54 MHz (BUFH)

– Phase relationship between input clock and output clock is irrelevant

Solution– MMCM values

• M=16, D=1, O0=9.875, O1=1, O2=8– Generates

• 54 MHz on clkout0 O0 set to 9.875 using fractional counter

• 533 MHz on clkout1• 66 MHz on clkout2

MMCM

PerformancePath

CCIO

BUFIO

BUFH

BUFG

CLKIN1

CLKOUT0

CLKOUT1

CLKOUT2

CLKFBINCLKFBOUT

Summary

Clock regions = 40 CLBs, 40 IOBs in height– One or two I/O columns per region

32 global clock buffers (differential)– 8 global clock input pins (differential)– 12 global clocks per region

4 BUFIOs per I/O bank (differential)– 2 can drive adjacent I/O banks, others are local only

2 BUFRs per I/O bank– 6 regional clock networks– Can drive adjacent clock regions

The Clock Management Tile (CMT) has two Mixed-Mode Clock Managers (MMCMs) – Each MMCM includes a PLL– Jitter filtering and frequency synthesis capabilities

Where Can I Learn More?

User Guides – Virtex-6 FPGA Clocking Resources User Guide

• Describes the complete clocking structures

Xilinx Education Services courses– www.xilinx.com/training

• Designing with the Virtex-6 and Spartan-6 Families course• Xilinx tools and architecture courses• Hardware description language courses• Basic FPGA architecture, Basic HDL Coding Techniques, and other Free

videos!

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