HW/SW Codesign & JAVA Part 1: Introduction to …kom.aau.dk/group/05gr943/literature/introduction/hwswslides.pdf · Part 1: Introduction to Hardware/Software Codesign Ahmed A. Jerraya

Part 1: Introduction to

Hardware/Software Codesign

Part 1: Introduction to

Hardware/Software Codesign

Ahmed A. JerrayaTIMA Laboratory

46 Avenue Felix Viallet

38031 Grenoble Cedex France

Tel: +33 476 57 47 59

Fax: +33 476 47 38 14

Email: [email protected]

Ahmed A. Jerraya Tutorial DATE 9-03-99

HW/SW Codesign & JAVAHW/SW Codesign & JAVA

System Level Specification

g Principle: Joint development of hardware and software

starting from a high level specification

g Application: Telecommunication, Automotive, Consumer, …

g Challenges: hReducing the design time

hReducing the cost of modification/evolution

hOptimizing the hardware software partitioning

Co-design

Electronic System

Software

- processor - programs

Hardware

- ASICS - COTS

Hardware Software CodesignHardware Software Codesign


ObjectivesObjectives

8Mixed HW/SW Systems

8Co-design techniques

8Models for Co-design

8Tools and Methods: State of the Arts


Outline Part 1Outline Part 1


1. Introduction- System design- Models for codesign

2. Codesign techniques- Refinement from system-level specification- HW/SW co-simulation

3. Example : Codesign from SDL- SDL- Design example

4. Future directions and conclusion

Video Codec (H261)Video Codec (H261)

Camera Display

Grabber VLD IDCT MCC

MSQ busMCC bus

Unframer Framer DCT Pred.Filter

M.E. VLCISDN Line

CODEC

µP+code

HW

- SW PROCESSORS

- HARDWARE PROCESSORS

MSQ


Mobile Telecom Terminal(e.g. GSM)

Mobile Telecom Terminal(e.g. GSM)

g Different Kind of Expertises

g Different Kind of Languages

hProtocol : SDL

hDSP : COSSAP, Matlab

hRF : VHDL-AMS, SABER

hOCI : SDL, VHDL

ON

CH

IP IN

TE

RF

AC

ES Protocol

& MMI

DSP

RF



Automotive SystemsAutomotive Systems

Mechanical part

Electronic components

HardwareSoftware

Vehicle model

Electronic parts

- may amount to > 10% of the total cost

- critical part of car design

Mixed HW-SW DesignMixed HW-SW Design

MAIN PROBLEM: - Different cultures.

H/W design tools(COSSAP,VHDL,

Verilog, VHDL-AMS,...)

(System Design ToolsSDL,StateCharts, Java, Matlab, ...)

HW + SW

System-Level Model

LINKING CASE TOOLS & IC CAD TOOLS








Models and Steps for CodesignModels and Steps for Codesign

Protocol e.g. IEEE 488

OtherSubsystems

AnalogSubsystems

ASIPSµ controllersDSP

ExistingHardware& ASICs

1- System Level Modeling Language

2- System Level Synthesis Intermediate Form

3- Architectural Model

System-Level Modeling

System-Level Synthesis


Architecture for CodesignArchitecture for Codesigng MONO-PROCESSOR:- A top Controller FSM Programmable Controller (ASIP), (standard Processor)

- Execution Part Fus: (Operators, Coprocessors, Memory, Interface Units) Communication (Muxes, Buses, Registers, …)

CTRL

Comm-Network

FU2 I/O (FU)

CTRL

Comm-Network

FU2 I/O (FU)

CTRL

Comm-Network

FU1 FU2 I/O (FU)

Com. Control

g MULTI-PROCESSOR:

- Set Of Communicating Processors- Communication Network (Bus-Controllers, arbiters, layered Networks …)

- Very difficult to model using a pure synchronous language

FU1

FU1



Architecture for MultiprocessorCodesign

Architecture for MultiprocessorCodesign

Software Processors

Bus

ASIC

ExistingComponents

Bus

CPU+ROM+

I/O

HW Processors

COMMUNICATIONPROCESSORS

I/O

FPGA

BusFPGA

FIFO

Memory

Example

Software Hardware

CommunicationController

Model

n Components: Processors

n Links: Communication

n Composition: Hierarchy

Models for Hardware/SoftwareSpecification

Models for Hardware/SoftwareSpecification

TransactionSystemLevel

Algorithmic

RTLLevel

Time Unit HW/SW Models SW LanguageHW Language

Computationstep

Clock cycle

- Task graph- Communicating Processes

CFG-DFG

FSM-Bool.eq Low Level code

SPW, COSSAP,StateCharts, SDL,

Java, ...

VHDL, VERILOG,C

VHDL

SDL, Matlab, SART, Java, ...

C, C++

ASM, RTL-C



50k SLDLTransactions

150k VHDLcomputation steps

350k RTL VHDLclock cycles

System-levelSpecificationSystem-levelSpecification

SW High LevelC

SW High LevelC

HW BehaviourVHDL

HW BehaviourVHDL

ProcessorProcessor HWHW

Architecture exploration

SoftwareCompilation &

Processor Design BehavioralSynthesis

CODECODE

1000k Gates

Increasing the Abstraction LevelIncreasing the Abstraction Level







Refinement from System LevelSpecification

Refinement from System LevelSpecification

g Partitioning:h Allocation: fixes number and types of processorsh Binding: assign function to processors

g Communication Synthesis:h Protocol selection: select a protocol to execute abstract communicationh Interface synthesis: adapt the unit interfaces to the selected protocols

g Interface synthesis: adapts the application to the interface of the processor

g Software synthesis:h fixes the execution order of parallel tasks

h Targets a specific processor

g Hardware Synthesis: decomposes computation steps into clock cycles


PartitioningPartitioning

g Allocation: Fixes the number and types

of processors

g Binding: Assign functions to processors

g Main Problems

h Cost function

h Granularity

h Communication estimation

P2

P3

P1

P4

P5

P2 P5P1 P4

P5

HW1

SW2

SW1


Communication SynthesisCommunication Synthesis


Communication SynthesisCommunication Synthesis

Pi : Processor

Li : Logical Channel

Ri : Physical Channel

STEPS :

g Protocol Selection

g Interface SynthesisPROCESSES + PHYSICAL

COMMUNICATION

COMMUNICATION Library

R1 R2

R3 R4

PROCESSES + ABSTRACTCOMMUNICATION

1

2


L1

L2

L3

P2 P1

R1

P1 P2R2

R3

R1

P1 P2R4


HW/SW Interfaces SynthesisHW/SW Interfaces Synthesis

SW-ModelABCD

IOHW

ABCD

Micro-ProcessorDataADR

Interrupt

HW/SW interfaces synthesis

Processor Library

Low-Level C code

HW Model

RTL HDL


SW Code GenerationSW Code Generation

u The problem:

Input = A task graph

Output = Code for

a specific architecture

u The solutions:

8RTOS-based

8Software synthesis

8RTOS synthesis

Task

Task

Task

Executable Code

Specific ProcessorINT

ER

FA

CE

S

ME

MO

RY


Problems to be solvedProblems to be solved

u Task inter-dependence = avoids dead locks

u I/O = adapts to different I/O schemes

u Synchronization = avoids active waiting

u Performances = code size, execution speed

u Quality


Hardware SynthesisHardware Synthesis

System-Level modelTransition = Computation step

State 2State 3

State 2State 3

ss 1

ss 2

SynthesizableTransition = clock cycle

State1State1

T3

T2

exp1 exp2

exp3




2. Codesign techniques- Refinement from system-level specification

- HW/SW co-simulation




Co-simulationCo-simulationg Principle: Simulation of a multilanguage model

g Engine Model- Single-engine: Code-level simulation

- Multi-engine: Source-level simulation

g Synchronization- Master-slave model

- Distributed model

g Timing model- Zero delay operations: functional validation

- Timed operations : timing validation.


Co-simulationCo-simulationSingle engine vs multi-engine Co-simulation Approach

UnifiedModel

Single Simulation engineg Code-level simulation

g High speed

g Efficient when restricted to specific application domain

g Source-level simulationg Modular design simulation & debug

g Keeps the model semantic

L1L2

Ln

Simulator 1 Simulator 2 Simulator n

COSIMULATION BUS

L1 L2 Ln

Multiple Simulation engine

Co-simulation (C-VHDL)Co-simulation (C-VHDL)

MASTER SLAVE MODEL

VHDLHW BEHAVIOR

CLI

C- PROGRAM

DISTRIBUTED MODEL

VHDL

CLI C- PROGRAM

SW BUS: UNIX (IPC/Sockets)

g Makes use of VHDL extension ( CLI)

g C program is called as a procedure

g When distributed computation

required, the C code needs to be

organized as an FSM (scheduled)

g Uses UNIX-like Communication Model

g Fully distributed Computation Model

g Needs a Synchronization Model

g Allows to debug HW and SW using

specific debug Tools

g Multi-C ModulesAhmed A. Jerraya Tutorial DATE 9-03-99


Implementing DistributedC - VHDL Co-simulation

Implementing DistributedC - VHDL Co-simulation

SOCKETS(IPC, Lightweight…)

ROUTERConfiguration

file

main() { int a,b; exin(a); b=f(a); exout(b);}

Shared Memory

INTERFACE COSIM

Shared memory

INTERFACE COSIM

VHDL entityEach simulator communicatesvia a fragment of sharedmemory(or queues or …).

The router secures thecoherence between severalmemories via sockets.

Multilanguage Co-simulation(Distributed Model)

Multilanguage Co-simulation(Distributed Model)

Co-simulation BUS (e.g. UNIX/IPC)

VHDL

CLI C- PROGRAM

LX

INT


Automatic Generation of Co-simulationInterfaces

Automatic Generation of Co-simulationInterfaces

Module 1 Module 2 Module n Configuration file

Co-simulation Interfacesgeneration

...

Module 1

Interface 1

...

Co-simulation Bus

Module 2

Interface 2

Module n

Interface n



Control of MotorsControl of Motors








SDLSDL

System Exampleblock b1

block b2

P12

P11

P21

P21

P11

P12

Underlying Communication Process

hSDL (Specification and DescriptionLanguage): an ITU-T Standard for theSpecification of telecommunications systems

hConcurrency: Distributed systems

hHierarchy: System, Block, Process

hCommunication: message passing

hSynchronization: AsynchronousCommunication Implicit Queues


The Process: BehaviorThe Process: BehaviorSDL-GRSDL-PR

PROCESS SENDER;

DCL Next_to_Send INTEGER;…START; TASK Next_to_Send := 0; TASK Data :=Next_to_Send; OUTPUT Data; NEXT STATE WAIT_Ack;

STATE WAIT_Ack; INPUT Nack; … INPUT Ack; ...

ENDPROCESS SENDER;

Next_to_Send := 0 Data := Next_to_Send

Data

WAIT _Ack

Nack Ack

Next_to_Send := Next_to_Send + 1 Data := Next_to_Send

Data

Data


Communication in SDLCommunication in SDL

System Exampleblock b1

block b2

P12

P11

P21

P11

Underlying Communication

c1

c2c1 c1

hTwo Communication Levels: - Inter blocks: Channels - Inter Processes: SignalRoutes

hProcesses exchange messages

(ADT)hLayered Communication:

A channel may be specified as asystem (blocks + channels)

P12

P21



Robot Arm ControllerRobot Arm Controller


Process BehaviorProcess Behavior








CODESIGN from SDLCODESIGN from SDL

g Rapid prototyping

g Flexible Synthesis Flow: Designer in the Loop

Initial model

SDLInitial model

SDL

Architecture

SYSTEMREFINEMENT

Virtual PrototypeVirtual Prototype

C

VHDL

CommunicationSynthesis

Co-design flowCo-design flow

P1 (SW)P1 (SW) P2 (HW)P2 (HW) P3 (SW)P3 (SW)

System-Level SpecificationSystem-Level Specification

F1 F3F2

FunctionalPartitioning

F4

HW-SW Co- Generation

HW-SW RTL Architecture

Virtual ProcessorAllocation

P1 (SW)P1 (SW) P2 (HW)P2 (HW) P3 (SW)P3 (SW)Processor

ModelProcessor

ModelCode Code

Interfaces (HW)Interfaces (HW) Interfaces (HW)Interfaces (HW)

SinthetisableHardware

FunctionalPartitioning

CommunicationSynthesis

F1 F2F3’

F4’

F3’’F4’’

Com

mun

ic.

Com

mun

ic.

Com

mun

ic.

Communic.

Com

mun

ic.

Com

mun

ic.

Com

mun

ic.

Communic.

F3’’F4’’

F1F2

F3’

F4’

P1 (SW) P2 (HW) P3 (SW)

Virtual ProcessorAllocation

F1

Com

mun

ic. F3’’

F4’’

F3’’F4’’

Commu.

F2F3’

F4’

Com

mun

ic.

Com

mun

ic.

HW-SW Co- Generation

ProcessorModel

ProcessorModelCode Code

Interfaces (HW)Interfaces (HW) Interfaces (HW)Interfaces (HW)

SynthetisableHardware

F1

Com

mun

ic. F3’’

F4’’

F3’’F4’’

Commu.

F2F3’

F4’

Com

mun

ic.

Com

mun

ic.



Example: ATM Network InterfaceCard

Example: ATM Network InterfaceCard

TCPIP

AALATM

TCPIP

AALATM HW

SW

Application Application

FlexiblePartitioning

Physical layer


System Specification in SDLSystem Specification in SDL

Software166Mhz PentiumProcessor

Har

dw

are

AS

IC


TCP - Process BehaviorTCP - Process Behavior


Architecture ExplorationArchitecture ExplorationResources: Pentium based SW / Dedicated HardwareConstraints: Performance (5k cycles / cell = 25 Mb/s)

SW HW

TCP IP AAL ATM Performance (cycles/frame)

6 Mb/s

SW SW SW SW

HW

SW HW

0 5000 10000 15000 20000

12 Mb/s

19 Mb/s

60 Mb/s

41 Mb/s

SW

SW HW

Co-Design FlowsCo-Design FlowsM

on

ths

z Manual

S.L.Specification

Hand Coding

ArchitectureHW-SW

Implementation

Constraints

ArchitectureEvaluation

S.L. Specification

Executable Model

ArchitectureHW-SW

Day

s/H

ou

rs

Co

nstrain

ts

Automatic Partitioning,HW-SW Co-Generation

z Interactive

ArchitectureEvaluation

Implementation

z Manual

Late

z Interactive z Automatic

Implementation

AcceptableArchitecture

Synthesis

Specification

Executable Model

Cons-traints

z Automatic









State of the ArtsState of the Arts

g Plethora of academic tools:

COSYMA, POLIS, COSMOS, VULCAN, LYCOS, …

g Emerging commercial solutions:

Eagle, Felix, Seamless, Archgen, C-level-design,CoWare, Arexsys

Gap between Dreams & RealityGap between Dreams & Reality

1- An under-estimation of the gap between system specification and state of the art

tools: system-level is far from RTL.

2- An over-estimation of language’s capabilities: systems are heterogeneous.

3- An under-estimation of the importance of behavioral synthesis.

4- An under-estimation of multiprocessor architecture models.

Early codesign tools have created exageratedhopes because:



What is needed: linking system designtools to implementation

What is needed: linking system designtools to implementation

HW DESIGN?????

Co-simulation

SW DESIGN

MISSING LINKSGlobal validation: System, Environment, IP

Architecture explorationHW-SW Co-generation

System-level modelling and design tools

SPW, Cossap ….IP (C, VHDL,…)SDLMatlab

ConclusionConclusion

g KEY POINTS

hCodesign applications: Circuits & large distributedsystems

hCodesign models:

- One processor vs multiprocessor- Homogeneous models vs Heterogeneous models

hCodesign techniques:

- Refinements

- Cosimulation

hState of the Arts

- Emerging solutions


Documents

HW/SW Codesign & JAVA Part 1: Introduction to …kom.aau.dk/group/05gr943/literature/introduction/hwswslides.pdf · Part 1: Introduction to Hardware/Software Codesign Ahmed A. Jerraya