I. ASIC 및FPGA부 - pds5.egloos.compds5.egloos.com/pds/200704/11/49/ch3.pdf · 광운대학교-13-전자정보대학 Antifuse Technology (a) unprogrammed (erased) antifuse element

- 1 -광운대학교전자정보대학

I. ASIC 및 FPGA부

1장. 집적회로개요

2장. VLSI 설계방법

3장. 프로그래머블논리소자


History of FPGAEarly 1990, Greater functionality, Higher performance, Lower cost, Lower power consumption, Smaller dimensionSubmicron process, PCB manufacturing, Surface mounting technologyKey elements are PLD, VHDLGlue logic(TTL, CMOS) requires logic and multilevel minimization



FPGA vs. ASICLarge amount of digital logic (common)Tighter schedule (short time-to-market)Low volume productFirst production run with high-volume productsGood testabilityProgrammable



FPLD Architecture

I/O Block

Logic Cell

Interconnection



Programmable Logic FamiliesPLD (Programmable Logic Device): < 500 gates, K-map, decoder, consists of AND, OR gate array AND array is programmable, OR gate is fixedCPLD (Complex Programmable Logic Device)FPGA (Field Programmable Gate Array)



Advantage of Programmable LogicFewer devices are used ( > 10 TTL)Cost effective (Packaging and testing cost is high)Mnfg. cost of PAL is same as TTL (additional logic at the same mnfg. Cost)Saves PCB area, power, debug timeIncrease performance and design securityFlexibility is the greatest advantageUse process automation design tools



Design cycle of FPGADesignSpec

TruthTable

Booleanexpression

Logicminimization

Implementation

Logic design

Logic simulation

Place and route

Timing simulation

Test pattern generation

Fault simulation

Wafer fabrication

Testing

Prototype debug

Production

Logic design

Place and route

Configure

Prototype debug

Design cycle of ASICDesign cycle with TTL


Comparisons of Design cycle


FPLD Logic Cell ElementsLogic Cell

Transistor pairsBasic small gates (NAND, XOR’s)MultiplexersLook-Up Tables (LUT)Wide fan-in AND-OR



Major Programming TechnologiesSRAM

pass switch is controlled by state of SRAM bitEPROM

floating gate TR is turned-off/on by gate voltageAntifuse

Electrically programmed, low resistanceJTAG port is used A few pins are used for programming



Typical SRAM FPGA Architecture

SRAM has the program. On power up, external memory dumps program to SRAMLogic is implemented as LUTFunction input is address lines. N lines implement 2N functionsLUT with F/F : Configurable Logic Block (CLB)


SRAM Programming Technology

State of SRAM bits controls ON/OFF of pass gate TR.SRAM is volatile. On power up, SRAM contents should be loaded and configured

Requires external permanent memoryAdvantage: Reprogrammable while system is operating (SRAM!!!!)Disadvantage: Large size. 5 TR is needed for SRAM cell



Floating Gate Technology (EPROM)

High Voltage on floating gate injects charges and TR is turned OFFUV Advantage : no external permanent memory is requiredDisadvantage : Not reprogrammable as SRAM. Erase and programEEPROM requires more process steps than CMOS process



Antifuse Technology

(a) unprogrammed (erased)antifuse element

(b) programmed antifuse element (conductive link between the metals is created)



SRAM vs. AntifusePerformance

antifuse FPGA (higher performance, smaller R, flexible routing)Density and capacity

antifuse FPGA(small size, more gates) SRAM also competitiveEase of use:software depends on the vendor antifuse FPGA leads, routable architecture is easyIn-system programmability and reprogrammability

SRAM type leads



Comparison of Programming Technology

Technology& Process

Volatile?

Reprogrammability Area R(ohm)

(on switch)C(F)

(parasitic)

#extrafabric.steps

SRAMMUX

Pass Trans.1.2μm CMOS

Yes Yes In circuit Large 0.5-2K 10-20 0

ONOAntifuse

1.2μm CMOSNo No

FusesmallProg.trans.large

300-600 5 3

Amor-phousAntifuse

1.2μm CMOSNo No

FusesmallProg.trans.large

50-100 1.1-1.3 3

EPROM1.2μm CMOS No Yes out of

circuitSmall in

array 2-4K 10-20 3

EEPROM1.2μm CMOS No Yes In circuit 2x EPROM 2-4K 10-20 >5



PLDEPROM, EEPROM, FLASH technology is used for programmable connection Programmable macrocell and variable product-term distributionEach macrocell can be individually configuredMacrocell input is a sum-of-product



PAL 구성

(a) standard gate symbol and equiv. PAL diagram(b) schematic and PAL diagram equiv.



Examples : PAL

PAL 16R8 device architecture


PAL 16L8 device architecture


CPLDHigher integration for improvementLess board space, improved reliability, cost reductionContains multiple logic blocksLogic blocks communicates with other logic blocks with programmable interconnectsMore efficient use of die area, performance, cost reducton



Typical CPLD Architecture

Function Block (FB): Simple two-level PLD. Contains AND array and macro cell (MC)User Program: Turn on EPROM to include the selected input to AND termMacro cell(MC): OR gates to complete AND-OR logic (SUM of Product)I/O: Input or OutputUniversal Interconnect Mechanism (UIM): interconnection network



22V10 device architecture



FPGAArray of logic cells and I/O communicating with each other by wires within routing channelsSemi-custom gate arrayHorizontal and vertical routing wires are connected by programmable elements



Implementation of 3-bit counter with a FPGA



FPGA ArchitectureDeveloped to meet the market needsSystem designer likes to use FPGAPerformance

ability of system design at higher frequenciesDensity, capacity

ability of incasing integrationEase of use : quick time-to-marketIn-system programmability and reprogrammability



Generic FPGA architecture



pASIC380(Cypress) routing structure



SRAM cell used to control states of pass transistors


SRAMCell SRAM

Cell

SRAMCell

SRAMCell

SRAMCell

SRAMCell

N

E

S

W


FPGA ApplicationsData-path, I/O-intensive, register-intensive applicationsHigh-performance applications: PCI bus interface, DRAM controller with shorter setup time,DMA controller with shorter clock-to-output delayNetwork application (ATM, Ethernet)



FLEX 10K architecture (SRAM)

SRAM Architecture

Flexible RAM block2048 X 11024 X 2512 X 4



Configurable Logic Block(CLB)

Function logic (F,G) is implemented by memory LUTThird function logic(H) input from F,G, outside CLB



Fast Carry Logic in CLB

High speed carry logic for 2 bit adder



CLB function generator as R/W memory cell

Use memory LUT as RAM

Xilinx XC4000

16 X 232 X 1



In/Out Block(IOB)

IOB has programmable Pull down & Pull up resistors



FPGA TechnologiesRouting : apply the program voltage to build the conduct link

(amorphous-silicon antifuse, oxide-nitride-oxide antifuse)Small logic cell is implemented by antifuseSRAM : controls pass transistor connections between horizontal and vertical wires, volatile programming, larger than antifuseLarge logic cell with fewer wires is implemented by SRAM



FPGA TimingEasy prediction with simple FPGA designSignal propagation delay : function of cascaded logic cells, signal path, number of PI, fan-out, I/O cell delay. Design inform.(placing and routing) needed to predict propagation delay, performancePlace and route tools for static time analysis (setup time, clock-to-output delay,max operation frequencies)



FPGA selectionTechnology: size, performanceRouting : timing, performanceLogic cell architecture: Technology, Routing Logic cell architecture information is required to select FPGA Tools (VHDL, Verilog) enables benchmark design without reentering the design



Chooing DevicesDesign goal : how fast, how many gatesArchitecture features : how many signals, types of signals, Useful benchmark data : type of applications and benchmark data Benchmarking : test a design in several devices



Future of Programmable LogicPerformance and density requirements will increaseThe 3.3V market will continue to growLarge devices may work with on-board PLL to control clock skewIn-system programming will continue to be usedIn-circuit reprogramming will lead for reconfigurability


Documents

I. ASIC 및FPGA부 - pds5.egloos.compds5.egloos.com/pds/200704/11/49/ch3.pdf · 광운대학교-13-전자정보대학 Antifuse Technology (a) unprogrammed (erased) antifuse element