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Design Technology CenterNational Tsing Hua University
ICIC--SOC ProjectSOC ProjectCryptoCrypto--Processor CoreProcessor Core
Chih-Tsun Huang
icsoc2.8
OutlineOutlineOverall Network Security Processor ArchitectureCrypto-Processor CoreACM (Asymmetric Crypto-Module)SCM (Symmetric Crypto-Module)Test Chip
icsoc2.8
Network Security ProcessorNetwork Security ProcessorApplications: IPSec, SSL, VPN, etc.Functionalities:• Public (asymmetric) key: RSA, ECC• Private (symmetric) key: AES• Truly random number generator
Target technology: 0.25µm to 0.18µmClock rate: 200MHz or higher (internal)32-bit data and instruction word10Gbps (OC192)Power: 1 to 10mW/MHz at 3V (LP to HP)Die size: 25mm2
On-chip bus: AMBA
icsoc2.8
NSP ArchitectureNSP Architecture
MUXesAHBArbiter
AHBDecoder
AHBAHB
CPU
ExternalMemoryInterface
BRIDGE
CP
LocalSRAM
LocalSRAM
DMAController
RAM
APB
TestController
AMBAAMBA
StatusRegisters
PowerManager BIST
icsoc2.8
CryptoCrypto--ProcessorProcessorA coprocessor of NSP: scalable architectureDescriptor-based DMA interface
Test
I Buffer
Interface
Power
O BufferChannel#2
Manager
DMA RSA/ECC
AES
Hashing
RNG
Other EU
Channel#1O BufferI Buffer
AHB-Lite
icsoc2.8
Encryption ModulesEncryption ModulesACM• Asymmetric crypto-module• Operations:
RSAModular multiplication of large numbers (1024 bits)
SCM• Symmetric crypto-module• Operations:
AESMatrix operations, manipulation
RNG (Prof. T.-Y. Chang)• Random number generator
FIPS 140-1,140-2 Security Requirements for Cryptographic Modules
icsoc2.8
ACMACMAn RSA cryptography engine with small area overhead and high speed32-bit word-based modular multiplicationScalable word-width34K gates100MHz clockScalable key length
Word-based RSAcrypto-processor
core
MMU
Controller
IOinterfac
e
icsoc2.8
Test ChipTest Chip
34kGate count
1.7×1.8 mm2Die area
2.8×2.9 mm2Chip area
DIP 28 pinsPackage
0.35μmTechnology
A built-in self-diagnosis (BISD) to test 8 memory coresA builtFull-scan: 6 scan chains, each with 123 scan registersA built--in selfin self--diagnosis (BISD) to test 8 memory coresdiagnosis (BISD) to test 8 memory coresFullFull--scan: 6 scan chains, each with 123 scan registersscan: 6 scan chains, each with 123 scan registers
icsoc2.8
RSA Benchmarking (Kbps)RSA Benchmarking (Kbps)
0.230.832.88.0P-III 700M
0.62.16.618.7P-IV 1.8G
1024 bits512 bits256 bits128 bitsPC Platform
471791009.435.820
2.358.955
1024 bits(0.47f/1000)
512 bits(1.79f/1000)
Clock ratef (MHz)
icsoc2.8
SCMSCMAES cryptography32-bit external interface58K gatesOver 200MHz clockThroughput: 2GbpsSupport key length of 128/192/256 bits
Memory
I/OInterface
I/OInterface
Control Key ControllerKey Controller
Main ControllerMain Controller
En/De ControllerEn/De Controller
En/De &Key Expansion
Datapath
En/De &Key Expansion
Datapath
Response
DataInDataOut
icsoc2.8
Test ChipTest Chip
2.977 Gbps (128-bit key)2.510 Gbps (196-bit key)2.169 Gbps (256-bit key)
Throughput
250MHzMax. Freq.
63.4KGate Count
1,279 x 1,271 µm2Core Size
128CQFPPackage
TSMC 0.25µm CMOSTechnology
icsoc2.8
AES Benchmarking (Mbps)AES Benchmarking (Mbps)
0.660.710.80P-III 700MHz
1.701.902.05P-IV 1.8GHz
256 bits192 bits128 bitsPC Platform
9141066.71280100
182.8213.325620
45.753.3645
256 bits(9.14f)
192 bits(10.67f)
128 bits(12.8f)
Clock ratef (MHz)
icsoc2.8
CP Test Chip SpecCP Test Chip SpecClock Rate: 100 MHz(est.)
*1,2: Shared IO
HCLKHRESTn
HREDYM_exHRESPM_ex[1:0]HGRANTM_exHADDRM_ex[9:0]HTRANSM_ex[1:0]HWRITEM_exHBURSTM[2:0]HBUSREQM_ex
HADDRS_ex[9:0]HTRANSS_ex[1:0]HWRITES_exHSELS_exHREADYin_exHREADYout_exHRESPS_ex[1:0]
DOUT[31:0]DIN[31:0]
HRESETHCLK
HREADYSout
HRDATAS[31:0]HRESPS[1:0]
Available Test Pin: 27 or 11Functional I/O: 53/52 (105)
Package: 144 or 128Power: 12 {IO (4 X 2), Core (2 X 2)} (estimated)
HRESETHCLK
HREADYSout
HRDATAS[31:0]HRESPS[1:0] so si
so si so si
2. Muxed AES3. Muxed RAS4. Logic Test5. Memory BIST
1. FunctionalTest Mode:
UnitControl
CP
MBRMBCMSIMBOMRD
TRSTTDITMS
TDOTAM_IN[3:0]TAM_OUT[3:0]
TSCTSETCK
TestMode[2:0]
Test_si[3:0]
MSO
For MBIST (6)
For P1500 (15)
HWRITES
HSELxHREADYSin
HADDRS[5:0]
HTRANSS[1:0]HSIZEA[2:0]
HWDATAS[31:0]
AES I/O: 48/35 (83)
1
1
22
2
HWRITES
HSELxHREADYSin
HTRANSS[1:0]HSIZEA[2:0]
HWDATAS[31:0]HADDRS[9:0]
RSA I/O: 52/35 (87)
11
Test_out[3:0]
mbist
mtbist
Critical Path: 8 ns2
Test I/O: 32/24/17/11
}For Scan test (8)
AES_AHB
RSA/ECC_AHB
Test_se from TestMode
MCK = HCLKMBS from TestMode
(4,4)(13)
(13)
Gates: 123403.98Area: 2132420.75
Critical Path: 8ns
Area: 2520250.5Gates: 145847.82
Power: 300mW (est.) 1.9782W (syn.)
Power: 357 mW2.4857W(syn.)
(No MBIST)
(With MBIST)
Gates: 34044.3Area: 588286
1.6678W (syn.) Power: ?
(4,4)(4,4)
MBIST
