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ICCD 20081
Conversion Driven Design of Binary to Mixed Radix Circuits
Ashur Rafiev, Julian Murphy, Danil Sokolov, Alex Yakovlev
School of EECE, Newcastle University, UK{ashur.rafiev, j.p.murphy, danil.sokolov, alex.yakovlev} @ ncl.ac.uk
ICCD 20082
Outline
Switching Balanced Codes Conversion Driven Design (CDD)
Motivation Conversion Basics
Bitwise Approach Bitwise Gate Grouping Algorithm Artificial Combinational Loops Problem
Operandwise Approach Operandwise Gate Grouping Algorithm Benchmark Results
Conclusions
Outline
ICCD 20083
Switching Balanced Codes
M-of-N data encoding: data signal is represented with• N wires
• M of them are active (high)
Return-to-zero (RTZ) protocol: data signals are separated with dummy signals (spacers)
Application areas:• Security
• Asynchronous system design
• Network-on-chip communication
Switching Balanced Codes
ICCD 20084
1-of-2 (Dual-Rail) and 1-of-4 Encodings
multi-valued single-rail (binary)
dual-rail 1-of-4
0
1
2
3
00
01
10
11
01 01
01 10
10 01
10 10
0001
0010
0100
1000
NULL spacer 00 00 0000
ICCD 20085
Outline
Switching Balanced Codes Conversion Driven Design
Motivation Conversion Basics
Bitwise Approach Bitwise Gate Grouping Algorithm Artificial Combinational Loops Problem
Operandwise Approach Operandwise Gate Grouping Algorithm Benchmark Results
Conclusions
Outline
ICCD 20086
Conversion Driven Design: Motivation
+ Higher radix signals consume less power and reduce cross-talk effect
– Require multi-valued logic synthesis
+ Some tools and techniques already exist (e.g. MV-SIS)
– Moving away from the RTL design flow is frequently frowned upon by industry
Reuse existing popular design tools for multi-valued system design
ICCD 20087
Conversion Driven Design Flow
EDA Tool
Synthesize binary circuit from
specification HDL specification
Conversion Tool• fast• fully automated
Convert to mixed radix component
level design
Flatten components to the gate level
netlistComponent library
Place and route
Final design
AREA OF THERESEARCH
ICCD 20088
… …mixers splitters
Conversion Basics
……binaryinputs
binaryoutputsbinary
……quaternaryinputs
quaternaryoutputsquaternary
Original binary datapath is given as a structural HDL netlist.Pairs of binary signals can be grouped into quaternary.Certain part of the circuit may remain binary.
ICCD 20089
Conversion Basics
Signal converters: A splitter converts one quaternary signal into two binary. A mixer converts two binary signals into one quaternary.
The way the signals (gates) are grouped determines the efficiency of the conversion, therefore the conversion problem corresponds directly to the gate grouping problem.
ICCD 200810
Outline
Switching Balanced Codes Conversion Driven Design
Motivation Conversion Basics
Bitwise Approach Bitwise Gate Grouping Algorithm Artificial Combinational Loops Problem
Operandwise Approach Operandwise Gate Grouping Algorithm Benchmark Results
Conclusions
Outline
ICCD 200811
Bitwise Gate Grouping
A={A0, A1}B={B0, B1}Q = {Q0, Q1}
Q = A·B
Q0 = A0·B0Q1 = A1·B1
A0A1
B0B1
Q0Q1
4
4
4
a bitwise quaternary component
ICCD 200812
Bitwise Gate Grouping Algorithm
Uses heuristics to extract bitwise meaning of signals from the flat netlist.• Input and output port grouping is given
• Algorithm is iterative, based on breadth-first search
• Bitwise Regularity Ratio is used as an estimation criteria. It is calculated for each gate pair on each iteration.
Bitwise Regularity Ratio (BRR) depends on how many quaternary links a pair of gates can form with respect to the state of the conversion on the given iteration.
ICCD 200813
Bitwise Gate Grouping Algorithm: Example
BRR=2
BRR=2
BRR=2
BRR=2
BRR=2
BRR=1
BRR=1
original circuit converted circuit
* mixed radix components are shownas black boxes
BRR=1
ICCD 200814
Artificial Combinational Loops
Combinational loops can appear during the bitwise conversion while the original circuit is free of combinational loops.
Need special methodology to handle. Problems:
• If mixers wait for valid data from both inputs – deadlock.
• If mixers produce output regardless to spacers – invalid output.
• A signal should pass artificial combinational loop exactly 2 times before it produce a valid output.
ICCD 200815
Bitwise Gate Grouping
Disadvantages of the algorithm: Computational cost O(N) = 2N2log2
2N, N is a number of gates in the original circuit.
Disadvantages of the approach: Inefficient for circuits without bitwise nature of signals, e.g.
S-boxes. The algorithm can produce combinational loops.
Bitwise (naive) approach is inefficient for CDD.
ICCD 200816
Outline
Switching Balanced Codes Conversion Driven Design
Motivation Conversion Basics
Bitwise Approach Bitwise Gate Grouping Algorithm Artificial Combinational Loops Problem
Operandwise Approach Operandwise Gate Grouping Algorithm Benchmark Results
Conclusions
Outline
ICCD 200817
Operandwise Gate Grouping
Bitwise grouping is derived from the functional meaning of signals.
Operandwise grouping is derived from the structural positioning of gates – works with 2-input gates only.
A0A1
B0B1
Q0Q1
4
4
4A0B0
A1B1
Q0Q1
4
4
4
a bitwise quaternary component an operandwise quaternary component
A0
B0
A1
B1
Q0
Q1
ICCD 200818
Binary Trees Approach
For binary tree structures within a netlist we can group inputs and outputs of gates to perform an operandwise grouping.
ICCD 200819
Binary Trees Approach
Signals cannot be shared between groups, because it leads to duplication of gates.
Gates with multiple fanout block operandwise grouping.
– Remain binary
ICCD 200820
Quaternary-to-Binary Gates (Q/B Gates)
Q/B gate – a gate with one quaternary input and one binary output.
ICCD 200821
Quaternary-to-Binary Gates (Q/B Gates)
A Q/B gate is a mixed radix component. A Q/B gate is an incomplete operandwise group. It can replace a splitter followed by a binary gate.
ICCD 200822
Operandwise Gate Grouping Algorithm
Phase I: group all signals regardless of gate fanouts (some gates will be duplicated).
Output ports can be grouped arbitrarily. Phase II: analyse duplicates and discard groups leading to
duplication. Phase III: insert signal converters and Q/B gates.
Computational cost of the algorithm is O(N) = 3N, where N is a number of gates in the original circuit.
ICCD 200823
Operandwise Gate Grouping Algorithm: Example
original circuit converted circuit
Phase IPhase IIPhase III
ICCD 200824
Operandwise Gate Grouping
Advantages of the algorithm: Low computational cost. It is highly modular: one can add more passes to the
algorithm to increase efficiency of the conversion.
Disadvantages of the algorithm: Can produce significant “fractioning” of binary and
quaternary parts of the circuit increasing the number of signal converters required.
ICCD 200825
Benchmark Results
circuit
dual-rail mixed radix: dual-rail, 1-of-4
switching wires
switching energy switching wires
switching energy
average std. dev average std. dev
2-bit adder 20 11.13 0.2661 14 10.66 0.0000
16-bit ripple carry adder 160 86.31 0.9803 84 75.72 0.0000
4-bit multiplier* 56 30.08 0.5247 58 38.72 0.1074
Kasumi S-box7 250 139.13 3.4908 264 144.98 0.6993
Kasumi S-box9 256 146.51 3.7947 264 137.12 1.2070
Kasumi S-box9* 300 169.56 1.3448 326 187.96 0.7809
AES S-box* 1594 818.56 1.1914 1640 1116.03 0.4870
* original single-rail circuits were optimised in Synopsys.
ICCD 200826
Outline
Switching Balanced Codes Conversion Driven Design
Motivation Conversion Basics
Bitwise Approach Bitwise Gate Grouping Algorithm Artificial Combinational Loops Problem
Operandwise Approach Operandwise Gate Grouping Algorithm Benchmark Results
Conclusions
Outline
ICCD 200827
Conclusions
Conversion driven design technique was suggested in order to reuse popular EDA tools for MVL synthesis.
Binary and quaternary mixed radix was selected to improve the efficiency of the conversion.
Two conversion (gate grouping) algorithms were implemented and analysed.• Bitwise approach is not efficient for CDD
• Operandwise approach is fast and flexible but not efficient enough in terms of saving switching energy.
Future work: Improve operandwise component implementations. Add more heuristics to the operandwise algorithm to
increase the efficiency of the conversion.
ICCD 200828
The End
Thank you!
Questions?