Logic Analyser Instruction using Microprocessor Simulation

W. A. McKee & D. K. Hamson. Department of Engineering, Glasgow Caledonian Universitv. Cowcaddens Road. Glasgow G4 OBA

SUMMARY In this paper, the use of simulation on inexpensive personal computers as a replacement for expensive specialised microprocessor analysis systems is discussed. Comparisons are made between traditional metho& and that proposed in the areas of cost, flexibility and student acceptance. Software and hardware requirements are described.

1. Introduction

IN any course on electronic engineering, great emphasis is placed on techniques of structured design to produce systems to specification. A corresponding skill is to be able to collect signals and status and to analyse such a system when it does not work. A usefkl tool in this situation is logic analysis [ 13.

Introducing electronic engineering students to the techniques of logic analysis is not challenging in intellectual terms, and early practical sessions using simple fhction generators and counter circuits are usefd in promoting the manual skills of probe placement and analyser setup and control.

However, to properly use an analyser in the analysis of microcomputer systems significant extra complexity arises. The student is required to become familiar with the signal set of the chosen microprocessor, and to be able to map that conceptual set onto the often codusing pin-out of the actual chip.

The skill set to be encouraged requires a range of transaction sequences to be provided such that the student can apply their knowledge of the architecture to deduce what should be happening and devise an implementation of the analyser to capture evidence to support that theory.

Often the device chosen for the microprocessor section of a course is a fairly complex one to facilitate the teaching of higher level architectural concepts, and thus the chip itself may be unsuitable for probe attachment, e.g. those directly soldered or those requiring Plastic Leaded Chip Camers, which need special fitments to allow capture by a logic analyser. This predefined fitment however often removes the element of “choice” of signals to be captured from the user, as well as removing the manual probe placement element.

Even when the appropriate connections are made, the use of a microprocessor system which is not normally designed with low-level logic analysis in mind can introduce signals which only serve to coduse the beginner, such as delay cycles ( e.g. for slower memory devices such as EPROM), memory refresh cycles, and possibly even interrupts and branches from in-circuit monitors.

For this reason there are available basic microprocessor systems based on such processors as the 6502, 280, 6800 and 68000 from specialised suppliers [ 2, 3, 4 1, with simple Dual-In-Line chips with legs, or alternatively sets of test pins extended from the chips. Sample programs may be embedded in the systems, or more flexibly can be loaded from a host.

2. Objectives

The outlined strategy solves the physical problems and some of the signal problems of the teaching of logic analysis techniques. However, it significantly constrains the educational possibilities, not the least of which is that since these processors are extremely simple, they are unlikely to be useful for the architectural studies, meaning the students have to learn two architectures but only have an opportunity to analyse the simpler. It is clearly a preferred objective to allow analysis of the same model as that whose architecture is being studied.

In the dedicated systems as described above, the ability to define personalised program or timing sequences may be limited, especially with embedded systems. It is thus an objective to allow the instructor, or possibly even the student themselves, to define the execution sequence.

It is also difficult in these systems to introduce realistic fault scenarios, such as memory errors or timing faults, since to do so the hardware must be modified, not something to be advised in a working lab due to the likelihood of wear and tear or damage. Thus a final objective is to produce “designed to order” fault sequences in a controlled and repeatable manner.

3. The Simulator System.

The solution developed at Glasgow Caledonian University was to design a hybrid simulator system which provides the student with a simple set of pins to which the analyser may be connected, but allows the instructor to freely define the signals which will appear on those pins, and to present a predefined sequence at those pins at a chosen rate, with optional repetition, based on a standard PC with a simple test station.

This allows early sessions to use simple data patterns such as all-on / all-off, simple counts, and shifting bits, which will allow students to gain confidence in the manipulation of the analyser itself, while later the pins may be redefined as address, data, and control signals from the chosen microprocessor, in our case the Motorola 68000 Micro Processor Unit (68000) [ 5 1. In this way any possible progrdsignal condition can be reproduced, albeit at low rates ( which may well be a positive attribute in a learning environment ), avoiding all of the distractions referred to above. Fault conditions are easy to implement, and all sequences are absolutely repeatable over multiple test stations.

Thus the analysis is performed on the same device as is being studied theoretically, and so the first objective is hlfilled.

3.1 Hardware

The system is based on PC-XT compatible computers, from 8086 upwards, using an inexpensive and simple 24-bit U0 card [5], connected via a ribbon cable to a small converter card developed locally [ FIGURE 1 1, which expands the normal 24-bit outputs to 4O-bits, which are made easily available on a row of connector pins. Also provided is a CLOCK pin for monitoring

Output Pins and LED’s 4 4 4 4 4 4 4 4 4 4 4 4 4 ~ 4 4 ~ ~ 4 4 4 4 4 4 4 4 4

+5v .................... ......... ov

FIGURE 1 40-Channel Interface Adapter

This arrangement allows any laboratory equipped with any type of PC to be a candidate for logic analysis, with minimal expenditure.

3.2 Software

As discussed earlier, the objective of the system is to produce a set of signals on the appropriate pins. These are provided by a program, written in “C”, which allows the user to choose several options from a menu [ FIGURE 2 1.

Thus, the user can choose from the predefined list a set of signal sequences to be presented, which may be generated internally or read from an ASCII file - a set of 40- character lines, sequentially presented one line per output strobe. Presentation rate and repetition options are requested by the user, with the slowest rate also presenting the data on the screen as a row of 40 ( 1 or 0 ) characters.

Welcome to the ANALYSER simulation of 68000. Choose one of these tick cycles or 0 to exit

1 2 - 3 4 5 6 - 7 8 9 10 -

- FLASH PATTERN INCREMENTING PATTERN SHIFT PATTERN FREE RUNNINGREAD READ PATTERN READ PATTERN with FAULT WRITE PATTERN WRITE INCREASING PATTERN FAULT IN ADDRESSING OUTPUT FROM TICK FILE

Select speed from 0: fastest to 9: slowest -: Hit next menu choice to exit at end of cycles.

0101010101010101010101010101010101010101

FIGURE 2 . Menu presented by Simulator Program

As an example a PC based on an Intel 486 would produce a simulated clock rate of approximately 400 lcHz with no delays inserted, which allows long sequences to be simulated ( such as memory writehead tests) within a reasonable time.

4. System Use

There are two main categories of use - simple introductory practical sessions and more complex ,student-centred problems in analysis.

The earliest, simplest sessions use the predefined list, which is an intemal set of hnctions written to produce simple pattems. Later options on the list can produce address, data and control signal sequences to match previously defined laboratory assignments, such as memory reads, writes, and fault conditions, as fast as is possible to simulate the 68000.

For more complex situations the file presentation method allows for two usefkl scenarios:

The first is that a sequence can be produced for presentation using a simple editor - so if the developer can deduce a timing diagram, an output sequence to match may be easily produced in a very short time.

The second method uses the capability built into most logic analysers - that of the PRINT feature, which when invoked produces an ASCII output which although designed for a hard copy may easily be captured as a file. Judicious choice of channels and a little editing will allow real-life sequences to be captured and then used as often as is desirable. Thus the second objective is achieved.

Due to the simple storage method, it can be seen that it is also possible to choose to remove or add signal transitions by editing, and thus to embed into such a file a desirable condition such as a timing error or other such fault, or alternatively to remove distracting elements, thus achieving the final objective.

4. Conclusions

This system has been used for two semesters in Glasgow Caledonian University, and has successhlly achieved its objectives.

Principally the system has allowed the time students spend getting to an appropriate skill level to be reduced significantly, especially noticeable in those who find new skills more difficult to achieve. The ability to slow the output rate and to view (on screen ) the data as it is being clocked out assures the student that if the logic analyser capture is incorrect it is they who are in error and not the system under test - a position which many attempted to hold with the real systems, occasionally with justification.

For the more advanced student it has been found that when they go on to work on the real 68000 systems the students find that they have little difficulty in absorbing the practical changes required, and can produce valid results in short duration. This contrasts with the experience of directly exposing students to the real 68000 systems, which had a significant familiarisation time.

Academic staff have found they can tailor the practical sessions to illustrate particular effects, for instance the different execution durations of the various bus transactions. Interesting faults which are discovered during development on the real systems have been successhlly transferred to the simulator to improve diagnostic skills.

The success of the simulator has led to hrther developments - a project is under way to produce a graphical display of the intemal data movements of the 68000, which will hopehlly be integrated with the simulator to allow in-depth examination of the co- ordination of intemal processes and output signals.

5. References:

[ 11 Stephenson, J and Cahill, B (1988) Microcomputer Troubleshooting ( H W Sams, Indianapolis, USA)

[ 2 ] [3] [4]

Flight Electronics International Ltd, Ascupart St, Southampton, UK NOHAU Corp., 51 E. Campbell Ave, Campbell, California, USA Cambridge Micro Systems Ltd , Cambridge, UK

[ 51 MC68000 Microprocessors Reference Manual (1 99 1) Motorola Ltd, Publications Centre, 88 Tanners Dr. , Milton Keynes, UK

[6] 24-line Programmable U 0 card for PC Compatibles ( 1992) Maplin Electronics PIC, PO Box 777, Rayleigh, UK

Z 1995 The Institution of Electrical Engineers Printed and published by the IEE. Savoy Place, London WC2R OBL, UK