A Configurable Symbol Timing Recovery Based on FPGA with Fast Convergence to Synchronization

Yin Hui Chye 1, 2 1 Department of Electronic Engineering,

Faculty of Science, Macquarie University, Sydney, NSW 2109, Australia.

2 School of Electrical and Electronic Engineering, Engineering Campus, Universiti Sains Malaysia,

Nibong Tebal, 14300 Penang, Malaysia. yin-hui.chye@students.mq.edu.au

Mohd Fadzil Ain School of Electrical and Electronic Engineering, Engineering Campus, Universiti Sains Malaysia,

14300 Nibong Tebal, Penang, Malaysia. mfadzil@eng.usm.my

Abstract—As software defined radio (SDR) becomes more prevalent in wireless communications nowadays, a symbol timing recovery (STR) system with configurability of the symbol rate would be required in order to support different wireless standards. Convergence time i.e. how much time needed to achieve a synchronous status during alignment of timing phase, is one of the factors to determine STR performance. In the existing multi-symbol-rate STRs, convergence time varies depending on the moment of the symbol rate switching even without considering noise effect. A longer convergence time results in more initial errors in the symbol decision. This is undesirable because longer preamble bits are required for synchronization thus reducing the throughput rate. This paper presents a configurable STR using digital signal processing (DSP) algorithms, with fast convergence time that can be achieved by searching for the minimum timing error (which occurs at the optimal sampling instant) within each symbol period, and then capturing the associated optimal symbol sample at the zero-crossing of the filtered signal. The convergence time is calculated based on the predefined symbol period regardless the moment of the symbol rate switching. The proposed configurable STR is implemented using Xilinx Virtex-4 FPGA. Implementation results show that at least 21% of the FPGA hardware utilization has been saved for the proposed configurable STR as compared to the existing configurable STRs.

Keywords-configurable, symbol timing recovery, FPGA, synchronization, convergence time, timing error detector, zero-crossing, software defined radio

I. INTRODUCTION Wireless communications have become pervasive since the

past two decades, such as universal mobile telecommunications system (UMTS) and wireless local area network (WLAN) [1]. The rapid growth of wireless communications systems has led to the development of newer wireless systems and standards for high speed data and voice services. Traditional hardware-based radio delivers only a single communication service using a particular standard and cannot support multi-standard wireless communications due to its limited cross-functionality. Moreover, its upgrade via physical intervention would result in high development and production costs. However the emerging

software radio (SR) [2] and software defined radio (SDR) [3] have overcome the problems by providing re-configurability and programmability of different physical layer functions in one piece of hardware with lower costs. The SDR concept employs digital signal processing (DSP) techniques intensively to perform intermediate frequency (IF) and baseband signal processing tasks which are traditionally performed by analog components in transmitter and receiver [2, 4].

The common silicon solutions for implementing SDR are field programmable gate arrays (FPGAs), digital signal processors (DSPs), general purpose processors (GPPs), and application-specific integrated circuits (ASICs). However, FPGA offers the best solution in the IF stage and wideband (WB) modem processing due to high speed, high level of integration, high flexibility, and low development costs [5].

In communications systems, the received signal is always timely mismatched from the transmitted signal due to the delay imposed by the channel along with the channel impairments e.g. noise, attenuation, distortion, fading and interference [6]. This timing mismatch always causes errors in decision-making for symbol demapping in the SDR [7, 8]. Therefore, alignments of the sampling instant and symbol period using a controllable counter are required [8]. This alignment process is called symbol timing recovery (STR) or synchronization (STS).

There are two conventional STR schemes i.e. feedback and feedforward STRs. For feedback STR [8-13]: timing error (e) is used to adjust the sampling instant on the noisy baseband signal through a feedback loop. The feedback STR employs a closed-loop structure known as the digital phase-locked loop (DPLL) [14]. Whereas for feedforward STR [15-18] which employs an open-loop structure: timing error (e) is used to estimate the optimum sampling instant (nopt) near the maximum eye-opening using the maximum likelihood (ML) approach, then it is used to update coefficients of a polynomial interpolator, in order to reproduce the optimal signal sample.

Although the digital feedback STRs [8-13] and feedforward STRs [15-18] can be modified to support any single symbol rate, additional considerations and control systems would be required to support multiple symbol rates used for different

This work was supported in part by the Malaysia Communication andMultimedia Commission (MCMC), Malaysia Ministry of Science,Technology, and Innovation (MOSTI) under Grant ScienceFund 6013316, andUniversiti Sains Malaysia (USM) Fellowship.

2012 International Symposium on Communications and Information Technologies (ISCIT)

978-1-4673-1157-1/12/$31.00 © 2012 IEEE 449

wireless standards e.g. WCDMA (3.84 MSps), HSDPA (3.6 Mbps) and Bluetooth (1 MSps), thus adding more hardware costs. However, the emerging configurable STR [19-20] allows different alignments of the sampling instant to support multiple symbol rates on the same hardware via configurations. This interesting feature satisfies the flexibility of SDR for multi-standard communications. However, convergence times i.e. how much time needed to achieve a synchronous status during the timing phase alignment, for these configurable STRs vary depending on the moment of the symbol rate switching even without considering noise effect. An inconsistent convergence time is undesirable because a longer convergence time results in more initial errors in the symbol decision, leading to longer preamble bits for synchronization thus reducing the throughput.

In this paper, a new configurable STR with a fast and specific convergence time based on DSP algorithms is presented. There is only one parameter to configure i.e. the number of samples per symbol (Ns). Thus, it is simpler than the configuration parameters of STR of [19] (i.e. proportional gain Kp, integral gain Ki, and Ns) and that of [20] (i.e. Ns, step size, accuracy and threshold). The proposed configurable STR is implemented using Xilinx Virtex-4 xc4vsx35-10ff668 FPGA and simulated using Xilinx System Generator Tools in the Matlab/Simulink environment. In simulation, the convergence time is examined whether specific or not for the associated new symbol rate after symbol rate switching. Lastly, the efficiency of the proposed configurable STR is evaluated in term of FPGA elements by comparing with the existing STRs.

II. DESIGN CONSIDERATIONS

A. Design Criteria and Assumptions Multiple digital down converters (DDCs) supporting multi-

symbol rates are undesirable because the hardware cost is very high, even excluding hardware utilization of multi-symbol-rate STR [20]. Therefore, in order to use only one DDC, the system clock of multi-symbol-rate STR should be fixed at a frequency of more than twice of the Nyquist frequency of the baseband signal incoming from the DDC. Due to the fixed system clock or sampling rate (fs), the symbol rate (Rsym) can be configured by changing the oversampling factor (L), as given by

/ , 2sym sR f L L= ≥ .

As the symbol period (Tsym) and sampling period (Ts) are inverses of Rsym and fs respectively, the number of samples per symbol (Ns) is equal to the oversampling factor (L), as given by

/ /s sym s s symN T T f R L= = = .

In the SDR architecture, the proposed configurable STR is located after the single DDC along with the following assumptions [20]:

• Sampling rate (fs) is fixed, i.e. the same driving clock frequency for different supported symbol rates;

• Carrier phase recovery has been performed previously;

• Wideband signals are not supported;

• Symbol rate switching is asynchronous, i.e. it can occurs at any sample time within symbol period (Tsym);

• The supported symbol rates are known i.e. the numbers of samples per symbol (Ns) are predefined.

The symbol rate switching can be either one of the following scenarios [20]:

• Planned switching: The change to a specific symbol rate is agreed by two communication nodes via exchanged packets. The new symbol rate is updated accordingly.

• Automatic switching: The incoming symbol rate is not known, and it is estimated and updated by an optional symbol rate estimator.

B. Choice of Matched Filter Matched filter (MF) is used to match the pulse shape of the

baseband signal and reject the out of baseband noise [6]. There are many types of MFs e.g. root-raised cosine (RRC), rectangular (flat averaging), Gaussian, etc. [6] Although RRC and Gaussian MFs can achieve higher signal-to-noise ratio (SNR) than rectangular MF, rectangular MF is chosen for the proposed configurable STR due to higher configurability and lower complexity. The configurability of the rectangular MF is illustrated by the following transfer function and impulse response [20]:

( )

[ ] [ ]1

1 ;1

;

sN

s

zH zz

h n u n u n N

−

−−=−

= − −⎡ ⎤⎣ ⎦

where Ns is the only configuration parameter.

III. THE PROPOSED CONFIGURABLE STR

A. Process of Configurable STR The proposed configurable STR contains 2 types of signal

flows i.e. data and control signals, and configuration parameter, as illustrated in Fig. 1.

Figure 1. General structure of proposed configurable STR

For simplicity, the data input is assumed to be a BPSK sequence with +1 and −1 alternating every Ns samples. As the

Matched Filter

Lower Error Search

Zero-crossing Detection

Timing Error Detector

Data Update and Capture

Symbol Period

Data Out

dfilt L, C, E

e zc

|e|, le

C

Data In

NS

STR

eupd Notes: Data & Control Configuration

new new

new

(1)

(2)

(3)

(4)

450

rectangular matched filter (MF) is chosen, the filter output (dfilt) is a triangular waveform with maxima (Ns) and minima (−Ns) alternating every Ns samples. By using the Gardner timing error detector (TED) [21], the timing error (e) is detected as

[ ] [ ] [ ] [ ]( )1 2e n d n d n d n= − ⋅ − − ,

where d[n] = dfilt [n]. Assume that d[n−2], d[n−1] and d[n] are early (E), current (C) and late (L) samples respectively, it can be seen that e[n] coincides with the L sample d[n]. This implies that e[n] ≈ 0 if the C sample d[n−1] is the peak (maxima) or valley (minima) of waveform dfilt when the E and L samples are closed to each other, i.e. d[n−2] ≈ d[n]. Thus, the optimum sampling instant (nopt) coincides with the peak or valley of C sample d[n−1] when e[n] ≈ 0 (minimum). The following steps are performed to obtain the minimum timing error (emin) and the associated synchronized (optimal) symbol sample (dsync):

1) Lower error search: If the absolute timing error (|e|[n]) is lower than the previous updated timing error (eupd [n−1]), the lower error state (le) becomes ‘1’ (otherwise ‘0’).

2) Data update: If the le is ‘1’, the absolute timing error and current sample are updated i.e. eupd [n] = |e|[n] and Cupd [n] = C[n]; otherwise hold.

3) Zero-crossing detection: If L and E samples or C and E samples have opposite signs i.e. Lsign [n] ≠ Esign [n] or Csign [n] ≠ Esign [n] for even or odd Ns respectively, the zero-crossing state (zc) becomes ‘1’ (otherwise ‘0’). Note: For even Ns, Lsign is compared with Esign because C = 0 during the zero-crossing.

4) Data capture: If the zc is ‘1’, the minimum timing error and the synchronized symbol sample are captured i.e. emin [n] = eupd [n] and dsync [n] = Cupd [n]; otherwise hold.

There is only one configuration parameter in the proposed STR i.e. the symbol period. It is represented by Ns to determine the supported symbol rate using (1) and (2). During symbol rate switching, the change state (new) becomes ‘1’ (otherwise ‘0’). Consequently, all the rectangular MF, TED, zero-crossing detection, data update and capture are reset to initial conditions.

B. DSP Modeling for Simulation Fig. 2 illustrates the simulation model of the proposed

configurable STR based on DSP algorithm using Xilinx System Generator (Sys Gen) Tools [22] in the Matlab/Simulink environment.

Figure 2. Simulation model of configurable STR in Sys Gen/Simulink

All models are built by connecting blocks provided by libraries of Simulink and Xilinx blocksets. The simulation model comprises of 2 main DSP models of Matched Filter and STR which will be described in the following subheadings. The other blocks will be discussed under Heading IV.

1) Matched Filter model: As shown in Fig. 3, the BPSK sequence input d_in is converted to the triangular waveform as output d_filt, by using (3). The configurable delay of z-Ns is performed by the addressable shifter register ASR1 block in the Programmable Delay subsystem as shown in Fig. 4. Due to zero-based indexing of the input addr of the ASR blocks, the symbol period Ns is minus by 1 to be the offset symbol period Ns1 that will be used as the configuration parameter in the STR model. The condition of the symbol rate is observed by the Symbol Rate Change Detector subsystem as shown in Fig. 5. The symbol rate switching occurs when the current Ns is different from the last Ns, thus the change state output new is asserted as ‘1’ (otherwise ‘0’). In order to avoid unwanted direct current (DC) accumulation, the output d_out of the Programmable Delay subsystem is reset to 0 for Ns samples and the output d_filt is reinitialized with the current d_in. In addition, the previous offset symbol period is captured as output Ns0. The output Ns1 is delayed by 1 sample in order to be synchronous with the 1-latency Accumulator block. As the first maxima or minima of triangular waveform d_filt happens at sample n = Ns, the total latency of this model (DMF) is Ns.

Figure 3. DSP model of configurable Matched Filter

Figure 4. DSP model of Programmable Delay subsystem

Figure 5. DSP model of Symbol Rate Change Detector subsystem

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2) STR model: As illustrated in Fig. 6, detection of the timing error e is performed by the TED subsystem, and then search of the minimum timing error (emin) and capture of the synchronized symbol sample (dsync) are cooperated by the Lower Error Search, Zero-crossing Detection, Data Update and Data Capture subsystems. The operations of these subsystems and their responses to symbol rate switching will be detailed in the following subheadings.

Figure 6. DSP model of proposed configurable STR

a) TED subsystem: As shown in Fig. 7, the timing error is estimated as output e from the input d_filt by using (5). The sign of C (Csign) is used rather than the C value because multiplication by the C sample in (5) mainly indicates whether the e approaching or going away from the peak (or valley). During symbol rate switching, the outputs C and E are both reset to 0 by the input new_i of ‘1’. All the outputs L, C, E, new_o and Ns1_o are delayed by 2 samples for compensating the latency of TED (DTED) of 2.

Figure 7. DSP model of TED subsystem

b) Lower Error Search subsystem: As shown in Fig. 8 (a), the le output lower is asserted as ‘1’ (otherwise ‘0’) if the |e| output abs(e) (yielded by the Modulus subsystem) is lower than the input e_upd. In the Modulus subsystem as shown in Fig. 8 (b), the input din is either negated or not as output dout if the most significant bit of the din is either 1 or 0 respectively.

(a) (b)

Figure 8. DSP model of subsystem: (a) Lower Error Search; (b) Modulus

c) Zero-crossing Detection subsystem: As shown in Fig. 9, the zc output cross is asserted as ‘1’ (otherwise ‘0’) if Lsign ≠ Esign or Csign ≠ Esign for even or odd Ns respectively, and |L| and |E| (absolute values) are both over the threshold of 0.5. The over-threshold state of |C| (ovC) output over_th is asserted as ‘1’ (otherwise ‘0’) if |C| > 0.5 (threshold). During symbol rate switching, the over-threshold states of |C| (ovC) and |E| (ovE) are both reset to 0 by the input new_i of ‘1’. As the zero-crossings occur half symbol period (Ns/2) away from the peaks or valleys, the latency of this subsystem (DZc) is / 2sN⎡ ⎤⎢ ⎥ .

Figure 9. DSP model of Zero-crossing Detection subsystem

d) Data Update subsystem: As shown in Fig. 10, the input abs(e) and the sign of input C (±1) are updated as outputs e_upd and C_upd respectively, if the inputs lower and over_th are both ‘1’ when the input cross_i is ‘0’, or if the cross_i is ‘1’ (for renewing the search of emin for the next symbol period Ns). During symbol rate switching, the output e_upd is reset to 4 (the highest |e|) by the input new_i of ‘1’ which is delayed by 1 sample to compensate 1 latency of the Register block. While the output C_upd is not reset to 0 because additional dsync can still be captured (by the Data Capture subsystem) if Ns1 is greater than Ns0. The latency of this subsystem (DUpd) is 1.

Figure 10. DSP model of Data Update subsystem

e) Data Capture subsystem: As shown in Fig. 11, the inputs e_upd and C_upd are captured as outputs e_min and d_sync respectively, by the capture state capt of ‘1’ (from the Capture Enable subsystem). In the Capture Enable subsystem as shown in Fig. 12, the output capt is asserted as ‘1’ (otherwise ‘0’) if the input cross is ‘1’, or duplicate of the last cross (as output capt1) of ‘1’ before the input new of ‘1’ is

452

detected (if the output higher is ‘1’ i.e. Ns1_i ≥ Ns0_i). During symbol rate switching, the outputs e_min and d_sync are both reset to 0 by the reset state rst of ‘1’ (from the Capture Reset subsystem as shown in Fig. 13) which is asserted at Ns0 samples after detecting the final capt of ‘1’. On the other hand, the output e_min is only used for observing the data flow of emin, thus the Capture Min Error subsystem (indeed a Register block) is optional. The latency of this subsystem (DCapt) is 1.

Figure 11. DSP model of Data Capture subsystem

Figure 12. DSP model of Capture Enable subsystem

Figure 13. DSP model of Capture Reset subsystem

IV. RESULTS AND DISCUSSIONS

A. Simulation Results Referring to Fig. 2, the simulation parameters are set based

on the following blocks:

• System Generator block: Simulink system period (Ts): 1 unit; FPGA system clock period: 10 ns (or sampling rate fs = 100 MSps); FPGA model: xc4vsx35-10ff668.

• Input Signal block: Sample period (Ts): 1 unit; sampled data type: fixed point, 16 bits, binary point: 10.

• Period block: Sample period (Ts): 1 unit; sampled data type: unsigned integer, 4 bits. Notes: the highest supported Ns is 15 S/sym (samples per symbol).

For validating the functionality of the proposed configurable STR, the Scope STR block (refer to Fig. 2) is used to display the simulation results as illustrated in Fig. 14. The first and second plots show the input data din of ±1 alternating rectangular sequence and the corresponding Ns respectively, which are supplied from the Input Generator block (refer to Fig. 2). The third plot shows the triangular (saw) waveform dfilt yielded by the rectangular MF. The fourth and fifth plots show the final output of the proposed STR i.e. the synchronized (optimal) symbol sample dsync, and the associated minimum timing error emin respectively. Note that emin = 1 when the first dsync for the new Ns is obtained due to initial unstable feedback loop in the accumulator in the rectangular MF (refer to Fig. 3). In the last plot, the symbol rate switching (change) is indicated by ‘1’. In addition, the corresponding sample timing flows are listed in Table I.

Figure 14. Simulation results of proposed configurable STR

TABLE I. SIMULATION SAMPLE TIMING FLOWS

Rate, Rsym (Msym/s)

Period (S/sym) Sample Timing (S) Ns Ns0 nnew nstop0 nsync1 nconv

50 2 2 - - 7 7 33.33 3 2 50 55 59 9

25 4 3 100 107 110 10 20 5 4 150 158 162 12 25 4 5 200 207 210 10

33.33 3 4 248 254 257 9 50 2 3 300 305 307 7

Although symbol rate switching occurs at sample nnew, the

acquisition of dsync and emin for the previous symbol period (Ns0) still continues to compensate the overall latency of the proposed configurable STR (DSTR) as given by

,

/ 2 4.STR MF TED Zc Upd Capt

STR s s

D D D D D D

D N N

= + + + +

= + +⎡ ⎤⎢ ⎥

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453

This acquisition will stop at sample nstop0 i.e. dsync = emin = 0, before the first synchronous status for the new Ns is achieved at sample nsync1. Note that this acquisition may fail if Ns0 > DSTR. The convergence time (nconv) is calculated as the difference between nsync1 and nnew. It can be found that nconv = DSTR even the symbol rate switching is asynchronous i.e. it does not occur at the end of symbol period Ns0. Therefore, upon asynchronous symbol rate switching, nconv of the proposed configurable STR is specific and faster than that of [19] and [20] that is given by

( )0

1 1, 1 ;conv MF Capt s s sn D D mN m N m N= + + = + + ≤ <

where m denotes the samples away from the optimum time nopt.

B. FPGA Implementation Results The efficiency of the proposed (new) configurable STR is

evaluated in term of FPGA elements by comparing with the existing STRs of [19] and [20], as listed in Table II. FPGA elements consist of slices, flip-flops (FFs) and look-up tables (LUTs). It is clear that FPGA utilization of the proposed STR is lower than those of [19] and [20] by at least 21% in slices and at most 65% in LUTs. In addition, the highest supported symbol rate of the proposed configurable STR is 50 Msym/s, higher than [19] and [20] of 10 and 3 Msym/s respectively.

TABLE II. FPGA UTILIZATIONS OF CONFIGURABLE STRS

FPGA Element

STR Difference: New vs. [19] [20] New [19] [20]

Slices 243 509 192 −51 (21%) −317 (62%) FFs 208 245 155 −53 (25%) −90 (37%) LUTs 400 821 291 −109 (27%) −530 (65%)

V. CONCLUSION A configurable STR with a fast and specific convergence

time has been presented. The convergence time is determined based on the number of samples per symbol that represents different symbol periods and rates by deriving from the same driving system clock. Simulation results indicate no initial loss of optimal symbols during the timing phase alignment upon symbol rate switching under noise-free condition, as contrasted to the existing STRs. However, the loss of optimal symbols before symbol rate switching may occur if the previous symbol period is greater than the overall latency of the proposed STR. With a fast and specific convergence time, the preamble bits (training sequence) can be fixed and short enough for faster synchronization, thus increasing the throughput rate. Moreover, the proposed STR is more efficient than the existing STRs by saving at least 21% of FPGA resources (slices). Besides, a higher symbol rate up to 50 Msym/s can be supported by the proposed STR. Future work will focus on analyzing the proposed STR performance under noisy condition.

ACKNOWLEDGMENT Thanks to Mr. Mazlaini Yahaya from TMRD (Telekom

Malaysia Research and Development) for giving guidance and information related to Xilinx FPGA implementation.

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