The Influence of Parasitic Resistances on the fT-Optimisation of High-speed SiGe-HBTs

P. Agarwal’, H.G:A. Huizing*, P.H.C. MagnCe Philips Research Leuven, Kapeldreef 75, B-3001 Leuven, Belgium

prabhat.agarwal@philips.com

Abstract

We study the influence of parasitic series resistances on the cut-off frequency of high-speed SiGe hetero-junction bipolar transistors. Due to coupling of the parasitic resistances with the intemal collector-base capacitance signifcant extra delay time is introduced. This a t r a delay will cause saturation, or even a decrease, of fr at higher collector doping levels. In addition, we study the optimisation of an n-cap emitter profile, which is only passible when the collector delay is reduced to a minimum, and the series resistances are properly included.

1. Introduction

High performance bipolar transistors have benefited over the years from the advances in the lithographic printing of deep-sub-micron structures driven by the mainstream CMOS development.

With the resulting reduction of lateral dimensions, many parasitic capacitances and resistances in a bipolar device have been reduced. At the same time, rapid developments in epitaxial growth have enabled impressive vertical scaling, with nanometer-control of the grown layers. In addition, epitaxy has allowed the manufacturing of hetero-junction transistors, increasing the current drive by orders-of-magnitude through the use of SiGe alloy.

Together, these improvements have led to devices with collector-emitter delays of less than Ips, corresponding to cut-off frequencies above 150 GHz. Despite the reduction in feature size, delays due to parasitic resistances now represent a significant fraction of the overall delay. In older transistor generations such “parasitic delays” were negligible.

In this paper we show that it is essential to include these parasitic resistances when optimising’the doping profile in high-speed devices. Here we focus on the collector and emitter region. In particular, we study the emitter resistance since it scales to larger values for smaller transistor dimensions. We demonstrate that most of the parasitic delay is due to the RC-delay of parasitic emitter and collector resistances, in conjunction with the base- collector capacitance. We also show that the order in

which different regions are optimised is important. In our case the dominant delay is initially in the collector. Once this delay is minimized, it is possible to see the effect of changes on the emitter side.

2. Simulation Method

We study the problem of profile optimisation with the 2D drift-diffusion simulator MEDICI, calibrated to a 150 GHz process [I]. We explicitly include a network of parasitic resistors and capacitors, the size of which has been estimated from process parameters [2].

The simulated structure is shown in Fig. I , a schematic I D cross section in Fig. 2. The vertical profile is fitted to SIMS-measurements.

Base Emitter 0.25pn

Figure 1. A schematic representation of the simulated structure. We explicitly include a network of external resistances and capacitances. In our simulations, RE is varied. For all other external lumped elements, we use measured values.

DC- and AC-characteristics have been calculated in a straightforward way. However, breakdoun calculations are carried out separately, using a method based on the energy-balance equations. This is done in order to account for the non-local nature of the generation due to impact-ionisation. [3]. We use a constant energy- relaxation length of 65 nm for electrons, and 50 nm for holes [4].

* These authors contributed equally to. this work

29 I 0-7803-7999-3/03/$17.0002003 IEEE.

150 20%-SiGe base t i r

depth

Figure 2. A schematic representation of the vertical doping profile. The eminer cap-layer is u-type doped. The highly doped collector is processed using multiple implants through the emitter window [I]. In our simulations we approximate this by a constant doping concentration Ncop

3. Results and Discussion

Collector Optimisatiun

The delay time associated with the collector space- charge region has traditionally been considered to be one of the major components of the overall delay. Using the simulation method described in the previous section we first study how the collector doping affects the cut-off frequency. In these simulations, we use the emitter resistance ‘as . a parameter, keeping the collector resistance .fixed. Fig. 3 shows the result of these

’ ~ simulations.

W e observe that -for moderate doping levels, of around lx1017 cm”, the peak fT increases with increasing doping level, as expected. This increase in peak fT occurs at increasing current. densities, up to -4-5 mA/,m2. However at collector doping levels above 1 ~ 1 0 ’ ~ the cut-off frequency saturates, or even decreases with increasing doping levels, depending on the series resistance. Confirming the experimental findings in 151, this is in marked contrast to the perception that high collector doping levels are only detrimental for the breakdown voltage but not for fr. We also observe that a low emitter resistance allows a higher fr at higher collector doping levels.

W e attribute the drop in fT to extra RC-delay in conjunction with the base-collector capacitance. This capacitance increases with increasing doping. When series resistances are added, the extra delay counters the

-effect of the faster collector delay.

to^ verify this, we have performed simulations without any parasitic resistance, and extracted a “parasitic delay” as follows.

’

. . .

I 10” loi8 1 0l9

Collector Doping (cm.3

Figure 3. The peak cut-off frequency fr as a function of collector doping, calculated using 2D devices simulations, including full network of parasitic elements. The emitter resistance is used as a parameter, while the collector resistance is set to Re100 R.

I I

V*=l v

2.5 25%

0% io i7 10’8 10’9

Collector Doping (cm-’) 100%

75%

50%

50

”I

0%‘ 1 0 ’ ~ 10’8 10’9

Collector Doping (cm“) Figure 4. (a) The parasitic delay vs. collector doping for various values of the emitter resistance. The parasitic delay becomes an increasingly important component of the overall delay. (b) The approximate fraction of the parasitic delay due to (RE+RJxC,,. Almost all of the parasitic delay can be accounted for by this term alone.

Here superscript “bare” refers to the maximum +-off frequency ignoring the parasitic elements, and ‘‘full’’ refers to the complete .calculation including the parasitics. Fig. 4 shows how the parasitic delay becomes an increasingly important part of the total delay.

This parasitic delay is mainly caused by emitter and collector resistances RE and Rc which couple to CBc To illustrate this, asimple estimate for the parasitic delay is calculated, namely

.

Z, ,=(RE+Rc)XCcs .. ’ (2)

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Here C,, is taken from the simulations at low current conditions. We see in Fig. 3 that this delay time accounts for most of the extracted parasitic delay. This means that in our devices T ~ ~ ~ = T ~ ~ , to a good approximation. Note that this simple estimate ignores the reduction in the intemal base-collector bias due to the collector resistance. This may account for some of the remaining disagreement.

Our preceding analysis shows that the series resistances do not couple to the base-emitter capacitance, unlike the analytical model in [5]. Our model is, however, in agreement with previous work based on equivalent circuit models of the bipolar transistor [6].

The observation that T ~ , * T ~ ~ affords a fast altemative to time-consuming 2D simulations when optimising a given device technology. Since most of the parasitic delay can be accounted for in a simple way, it is possible to tum to fast I D simulations, and add parasitic delays in post- processing. This allows for rapid exploration of the design parameter space. Fig. 4 shows a comparison of

....9 0 (a) 2d simulations

50 ' I 1 oi7 loi8 lotg

Collector Doping (cm-') 200

150

100

50

50 R inum'l-loo

0 1oi7 1 0 ' 8 10'8 ..

Collector Doping

Figure 5. Approximations to the 2D cixuit-mode simulations of Fig. 2. (a) The symbols show the peak fr calculated using the "bare" 2D simulations, corrected with an additional delay (R,+RJxC,,. The solid lines show the same data as Fig. 2. (b) Here the symbols show the peak fi. calculated using the "bare" ID simulations, similarly corrected. The 1D collector capacitance is corrected with an additional overlap capacitance of 0.34 F.

the full 2D simulations with both 2D 'bare' as well as ID calculations. The RC-delay time is calculated using measured values for RE and Rc and simulated CBc. In the ID-case, a small extra delay is added, caused by the

extrinsic base capacitance. From comparisons of ID and 2D simulations of C,, gave -0.2 F/pm difference, which is added as an overlap capacitance. As can been seen from Fig. 4, we find that simple I D simulations in combination with the calculation of the parasitic RC delay time capture the behaviour. This is an indication that there is no significant current-crowding or spreading in our devices, and may not be generally true. The narrow emitter dimension together with SIC implants through the emitter window reduce such 2D effects.

With the collector doping levels considered here, a question arises about the breakdown voltage. We also studied the BVCBo of these devices which we obtain from the base-current reversal at Vk=700 mV, assuming a current gain of 100. In this bias range, the currents are small, and so the breakdown voltage is comparatively insensitive to the extemal series resistance.

In Fig. 6 we see that the breakdown voltage saturates at high doping levels according to our simulations.

4

- 3 L

* 2

0

1 1 7 lo i8 lo ig

Collector Doping (cm?)

Figure 6. The open-base breakdown voltage BV,,,, as a function of collector doping. The simulation accounts for non-local effects in the avalanche generation.

We attribute this to the increasingly n m o w spatial extent of the high electric field at the collector junction. Because of the 'dead-space' in the initial -65 nm of the junction [7], the impact-ionisation rate becomes increasingly insensitive to the peak of the electric field at the metallurgical junction. We thus observe that, while BVcEo saturates at high collector doping levels, fr actually shows an optimum, depending on the parasitic resistances.

Emilter Cap Optimisation

Having identified the optimal collector doping, we next turn to the tuning of the n-type emitter cap. Differences in the emitter delay are now no longer masked by the collector delay time. In contrast to the more widely used p-type cap-layer, devices with an n-type cap generally do not suffer from any significant reverse Early effect [l].

Fig. 7a shows experimental results and ID-simulations on the effect of varying the SiGe spacer layer thickness

293

tzzm in the cap. As before, the simulations account for the series resistances at the emitter and collector side. Fig. 7b shows experimental and simulation results on thickness variations of the Silicon layer tEMFap in the n- type emitter cap.

We first observe that simulations and experiments agree well with our experiments. They correctly predict both the magnitude and the trend of the experiments.

In Fig. 7b, we see that fT increases with decreasing Si cap layer thickness. We attribute this drop to a reduction in diffusion capacitance in the emitter-base junction. On the other hand, we observe in Fig. 7a that there is an optimum of +I50 GHz for a SiGe cap thickness of 3 nm. For thinner SiCe layers, the boron spike is partially outside the SiCe layer, increasing the total base Gummel number significantly. Thicker layers, however, increase the diffusion capacitance as above.

In Fig. 7, we also show simulations of the same variations, but with a collector doping of IxlO” and 6 ~ 1 0 ~ ’ cm”. In the former, the variations in the emitter thickness are totally obscured by the collector delay. In the latter, the collector doping appears to be irrelevant when comparing with 1 ~ 1 0 ~ ’ c d . One might

................. - 150 P cr ,+

0 4 8 SiGe spacer thickness i::: (nm)

300 1

....... ...... ......... - 6x10‘”

c

i 2 100 ~

. . . . . ........... ............ - /-’

N~~,= I ~ 1 0 ”

20 40 60 0

Si spacer thickness tEMcap (nm)

Figure 2. The emitter cap optimisation for an n-type doped emitter cap. Dots show measuremenls [ I ] , while solid lines show I D simulations corrected for the series resistance, as in Fig. 4b. Dashed lines show I D simulations without correction. (a) The peak fT vs. the SiGe spacer thickness. (b) Peak fT vs. the silicon cap thickness.

erroneously conclude that the collector delay is negligible. However, the bare device does get faster, but the speed improvement is lost in higher RC-delay times due to the extra CBC.

4. Conclusion

We have presented a study of a ISOGHz SiGe technology currently in development [I]. We show that we have to explicitly account for the series resistances at the emitter and collector side when optimising the cut-off frequency. These resistances contribute significantly to the overall delay time by coupling to the collector-base capacitance. We also show that fast ID-simulations, in conjunction with an approximate RC-delay, capture this behaviour quantitatively.

We apply this to optimise the n-type emitter cap of high- speed SiGe devices. Using the nanometer control of epitaxial growth, we find the optimumfT as the capping layers are varied. We show that the modelling of these effects depends critically on the proper inclusion of parasitics in conjunction with an optimised collector.

5. Acknowledgements

We are grateful to G.A.M. Hurkx, J.W. Slotboom, 1.C.J Paasschens, A. Heringa and A.H. Montree of Philips Research, and S . Decoutere of IMEC, for stimulating discussions. J.J.T.M. Donkers, E. Aksen, P. Meunier-Reillard and R.J. Havens carried out the processing, growth and RF measurements.

References

[l] J.J.T.M. Donkers et al., “Vertical Profile Optimisation of a Self-Aligned SiGeC HBT Process with an n-Cap Emitter”, submitted to BCTM 2003. [2] M. Mastrapasqua et al., “Device Simulations for Advanced Si,.,Ge, HBTs”, in Proc. Biplor/BiCMOS Circuits und Technology Meeting, 2001, pp. 42-5 1. [3] J. Slotboom et al., “Non-local electron and hole impact ionization io advanced Si BJTs”, in Tech. Dig. Intemational Electron Device Meeting, 1991, pp. 127- 130. [4] P. Palestri et al., “A Drift-DiffusiodMonte-Carlo Simulation Methodology for Sil.,Ge, HBT Design”, IEEE Trans. Electron Devices, vol. 49, pp. 1242-1249, July 2002. [5] P. Kempf and M. Racanelli, “Silicon Germanium BiCMOS Technology”, in Tech. Dig. IEEE GaAs IC Symposium, 2002, pp. 3-6. [6] H.C. de Graaff and F.M. Klaassen, Compact Transistor Modeling for Circuit Design. Vienna: Springer, 1990. See also J. Weng, “A physical model of the transit time. in bipolar transistors”, Solid-state Electronics, Vol. 36, No. 8, pp 1197-1201, 1993. [7] E.F. CrabbC et al., “The impact of Nonlequilibrium Transport on Breakdown and Transit Time in Bipolar Transistors”, in Tech. Dig. International Electron Device Meeting, 1990, pp. 463.467.

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