ESSCIRC/ESSDERC 2019 Challenges and capabilities of 3D

ESSCIRC/ESSDERC 2019Challenges and capabilities of 3D integration in

CMOS imaging sensors

Dominique Thomas, Jean Michailos, Krysten RochereauJoris Jourdon, Sandrine Lhostis

STMicroelectronics, [email protected]

September 23-26, 2019

ESSDERC 2019 IPCEI on microelectronics focus session

1D. Thomas

Outline

3D Integration principles

3D Integration for imagers

Hybrid bonding for imagers demonstration

Fine pitch Hybrid bonding Issues and demonstration

Future directions

D. Thomas 2ESSDERC 2019 IPCEI on microelectronics focus session

3D-Integration: principle

New system design paradigm: 3D partitioning

Key technological benefits

Reduction of interconnects lengths RC delay decrease

Heterogeneous integration

Density vs form factor

3

Wire Bonding

BGA

PCB

Interconnect

RDL

Cu/Low-k

Interconnect

Large Foot-print

L2D

2D Chip SetSystem-in-Package

L3D

Die-scale

RDL

Cu/Low-k

Interconnect

TSV

Interconnect

Block-to-Block Length

1 mm ~ 1 cm 10 ~ 100 mm

3D Chip SetSystem-on-chipS

Single ChipSystem-on-Chip

D. Thomas ESSDERC 2019 IPCEI on microelectronics focus session

3D-Stacked Image sensors

Form factor improvement

Optimized process dedicated to each silicon layer

Area in the logic die available for added value

Great interest of 3D integration for image sensors

4D. Thomas ESSDERC 2019 IPCEI on microelectronics focus session

CIS

AddedISPvalue

Smart sensors

CMOS ImageSensor

Image Signal Processor

CIS: Driver for 3D technologies

Different integration schemes have been developed specifically for the CMOS Image Sensor (CIS) market


Source: System Plus

What is Hybrid Bonding (HB)?


6

Flip

Align

Bond

CMOS

IMG

Back Side ProcessingThinning, I/O PAD, Passivation, color, µ-lens…

Face to face interconnections

Double Damascene Copper stack between top chip last metal and bottom chip last metal.

Pitch ≤ 10µm

Morphology

No glue but molecular bonding

Direct SiO2/SiO2 bonding: SiOH-SiOH Si-O-Si

At Cu-Cu interface: grain growth/migration by anneal


Top Wafer

Bottom Wafer

Top Ox

Bot Ox

Top Cu

Bot Cu

Via HBVBot.

Via HBVtop

Misalignment

3D HB-stacked imager demo


8

Computer Vision system:• Face identification• Gender identification• Age estimation• Happiness estimation• …

First Generation Pixel 1.5 µm

Bonding pitch 9.3 µm

But…

High density BH (~1 µm) will

Reduce footprint

Allow pixel-level optimization

Fine pitch Interconnect

Pitch shrinkage

Opportunity of new pixel architecture


7.2 µm 1.44 µm

Hybrid bonding process flow


10

TOP

BOTTOM

Bonding annealingat 400 °C

Bonding pad + viasdual-damascene

Bonding atroom temperature

S. Lhostis, ECTC, 2016

Copper

Diffusion barrier

SiO2

Capping

Fine pitch Intconnects’ challenges


11

Overlay Copper diffusion

Electromigration

Delamination

Yield

V- V+J J

Process Reliability

Electrical yield

Resistance measurement of 30k interconnects daisy chains

Yield not affected by the 5x reduction of bonding pitch

Tool alignment capability (200 nm @ +/- 3s) is sufficient


Pitch 7.2 µm1 pad -4 vias

Interconnect resistance (mΩ)

Cum

ula

tive

dis

trib

ution (

%)

020406080

100

100 200 300

100% yield Pitch 1.44 µm6 pads – 6 vias

Yield

Overlay

Delamination (stress)

Fine pitch Higher average stress: a priori higher risk of delamination

-55°C/+150 °C 500 cycles Results: resistance well within specifications

Electromigration was also tested (not shown here): Results OK


Delamination

Von M

ises s

tress a

t ro

om

tem

pera

ture

Pitch 1.44 µm

Coupling effect

1 µm

Pitch 7.2 µm

1 µm

Pads spacing allows stress release

Image sensor comparison

The image quality is not degraded by going to finerwafer to wafer interconnection pitch


Standard pitch 7.2 µm Fine pitch 1.44 µm

Photo response non-uniformity (%)

0

20

40

60

80

100

0.5 0.6 0.7

7.2 µm

1.44 µm

Pitch:

Cum

ula

tive

Dis

trib

ution (

%)

Sequential Stacking:smaller pitch


15

Further steps: 3 layers


16

Oxide-Oxide DIRECT

Bonding + TSV

Oxide- oxide bonding

Oxide- oxide bonding

Source LETI/IRTSony ISSCC 2017 and TechInsights May 2017

CONCLUSION

3D Integration is a powerful tool to increase imaging sensors capabilities

Hybrid Bonding allows µm scale device to device interconnect

Permitting pixel level contacts improvement

Preliminary electrical and reliability show industrial viability

Further work include

Fully exploring the capabilities ans limitations of fine pitch Hybrid bonding

Pitch reduction using sequential stacking: allows deep pixel 3D architecture exploration

Adding more layers for system integration


Include Key References

[1] Y. Akasaka, Proceedings of the IEEE, Vol. 74, No 12, pp. 1703-1714, 1986

[2] T.Al abbas; N. Dutton; O. Almer; S. Pellegrini; Y. Henrion; R.Henderson “Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology”, 2016. IEDM Conference, San Francisco, United States

[3] V.C. Venezia, “1.0um pixel improvements with hybrid bond stacking technology”, International Image Sensor Workshop 2017, IISW 2017

[4] Toshiki Arai et al. “1.1-μm 33-MPIXEL 240-fps 3-D-STACKED CMOS IMAGE SENSOR”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 12, DECEMBER 2017, p4992

[5] J. Michailos, 3D ASIP workshop, 13th-15th December 2016, San Francisco

[6] S. Lhostis “Hybrid Bonding Toolbox for 3D Image Sensor”, European 3D TSV Summit – January 23-25, 2017 Grenoble France

[7] J Jourdon, et.al. Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness; 2018. IEDM Conference, San Francisco, United States


18

Documents

ESSCIRC/ESSDERC 2019 Challenges and capabilities of 3D