Design Considerations for Integrated Continuous-time Video Filters

Venugopal Gopina than and Yannis P. Tsividis Depar tment of Electrical Engineering

and Center for Telecommunications Research

Columbia University, New York, NY 10027

1 . Abstract

111 (.his paper, we report on an approach that has made possi- l ) l ~ tlic reliable integration of high performance video filters using conl.iiiitous-tinie techniques. Both delay equalization and magni- tiid(, filtering will be discussed. As an example, a 7th order Elliptic l i l k r is designed to mcet a certain set of specifications. The chip was fal)rica.tcd and the measured results are included.

2. D e s i g n A s p e c t s

‘l’li(> dosign coilsiderations for video frequency continuous-time fil- tcrs are qiri~c diffcrent from those for filters operating a t a lower fr(~~ircncy range. Tlic design aspects discussed in the following sc~rtiotis d(,;tl with implemcnting a low-pass video filter tuned by ii.ti oil-chip master-slave tuning system [l-41. Most of the con- sitlcr;it.ions discussed can also be extended to band-pass filters as WClll.

2.1 Fi l te r Topology

Sittcc. ~ . l i c master-slave tuning system relies on component match- iiig across rc,latively large distances on the chip, i t is important 1.0 c.lioose a liltcr topology that is insensitive to component varia- ~,ioris. ‘I’hc passbaud ripple amplitude and the order of the filter sliniild be lirialized only after simulations are carried out to en- sur(’ t,liat, the filtcr remains within specifications even with worst c a s c coutpoiicnt mismatches. In most cases the ripple amplitude c.11oscti should be much lower than what would just meet the spec- ific:it,iotis. llowever this may make necessary an increase in the

o r d o r of the filter leading to a different problem. When the order of Olic fillkr is increased, the passband edge becomes very sensi- 1.ive 1.0 phase errors at the unity-gain frequencies of the constituent i ii lcgra tbrs.

AI. video frequencies. a transconductance-C topology is pre- fcrrcd for i1.s superior high-frequency performance, provided de- IhiI~d device-level design (as opposed to using standard cells) is fcwiblc.

Most video filters also require an equiripple delay characteris- tics over most. of its passband. We describe, later in this paper, a ~ ~ ~ i t i h l ~ equalizer topology with low magnitude sensitivity.

2.2 Transconduc tance Amplifier

All.horigli iiew transconductance amplifier designs with tunable l.raiisc.ontluctors have bcen reported wit.h very high output current liiacnrity wi1.h input voltage, they are not always suitable for video iipplic~itions. In some topologies, the non-quasistatic behaviour of 1 . 1 1 ~ MOS transistor [5] causes significant levels of distortion a t video frequencies. This problem is aggravated by the fact that devices which determine the G, need to be long to preserve good matching across the chip. Also, this effect is poorly modeled in iuost simuhtion programs or is not modelled at all. (One way to partially model this effect is to split these critical devices into a number of sliort but fictitious devices connected in series.) The size of the amplifier is made as small as possible because, apart from saving chip area, it becomes easier to match components across the chip if the distances involved are small. For phase t.iining purposes, the transconductance amplifier configured as an

integrator should have a variable phase a t unity gain frequency.

2.3 T u n i n g Circuit

Although many different types of tuning systems were reported in the recent past, we will use the well known master-slave tech- nique as a representative example. The tuning scheme maintains stable gain-constant G, - C integrators by phase-locking a self- tuning biquad to an external reference frequency [l-41. Since the integrators in the slave filter are also controlled by the same volt- age, they are also properly tuned. This technique is extended to control both the unity gain frequency and the phase of the integrators constituting the filter [6]. The phase detectors used for phase locking purposes are usually high-speed EXOR gates requiring square waves a t their inputs. Some important sources of frequency tuning error {=(Ref. frequency - Master resonance frequency)/Ref. frequency} are finite rise times of these square waves a t the input and output of the EXOR gates and systematic and random amplifier offsets. This is especially so in video filters where the reference frequency is in the MHz range. The topology of the tuning system should at least be able to correct for system- atic offsets and finite rise-times of the square waves. An example of such a system will be discussed later in the paper. The phase margins that exist in the feedback loops of both master and slave filters should be high enough such that these circuits do not os- cillate even if the phase control voltage (used to vary the phase of the integrators at unity gain frequency) is a t either limit of its possible range. This sets an upper limit to the Q of the master filter.

3. Low-sensitivity Delay Equalization

Most video applications require an equiripple delay characteristic over most of the passband. Although many delay equalization techniques exist in passive filter design methods [7], delay equal- ization is usually done using a cascade of biquads that implement the nccessary allpass functions. If the order of the equalizer is 4 or more, the poor magnitude sensitivity characteristics of the cascade of biquads obliterates the low sensitivity properties of the magnitude filter. Some additional requirements in the design of the equalizer are the following:

1) The poles and the corresponding mirrored zeros of the equalizer should be determined by the same set of reactive elements. Otherwise, matching the pole and zero frequencies, determined by different sets of components, is very difficult. 2) The active implementation of the topology (using G, - C type integrators, in this case) should not require the use of more than one value of G,. This is because it is much easier t o match equal G, transconductors. 3) The topology should be fully differential to facilitate a G, - C type implementation similar to the magnitude filter. The effort in this section is to achieve delay equalization while

keeping magnitude sensitivity of the complete filter low. The pas- sive prototype of the equalizer is as shown in Fig. 1.

The transfer function, H,(s) is given by:

CH2868-8/90/0000-1177$1.00 0 1990 IEEE

1---- 1

where

w, = 1/m = wp

This topology also exhibits low sensitivities

(3)

(4)

Also, a t w = wp = w, ,

Lossless p a r t

Doubly-terminated

Ladder

Flgure 1: Delay equalized doubly-termmated lossless networh

When all the 9,'s are equal, (= g,), the impedance, V / I is equal to l/gm. This resistive impedance provides the necessary ter- mination for the lossless network of the magnitude filter. The important advantage is that the network inside the dotted lines is still a lossless network, and so the complete filter retains the low sensitivity properties of a doubly terminated lossless ladder at points of maximum power transfer [8]. This technique can also be extended to higher order delay equalization.

The active version of a delay equalizcd llth order filter (7 th order Elliptic magnitude filter and qth order delay equalizer) is shown in Fig. 2.

1- -

rigurc 2: 7 t h order elliptic magnitude filter PIUS a. ,Ifh order equal- izcr

The equalizer used is a leapfrog realization of a lossless network similar to the one in Fig. 1, except that the order is 4 instead of 2. The gyrators are implemented using transconductance amplifiers connected back to back. In integrating this into a monolithic chip, these pairs of transconductance amplifiers can be laid out close

&'IN- ~- Figure 3: Biquad equalizer

t

I , . , I IO ~ " ~ ' ~ ~ " ' " " ' ' ' " " " " " " ~ " ' " " ~ ' ~ ' ' ' I 0 2 0 3 0 5 0

Frequency IMHz)

1:iSure 4: Slonte Carlo analysis of the delay-equalized 1 l th order filter ( a ) For the proposed topology (b) For the cascaded biquad type rcalization

together, so that the forward and reverse gyration conductanc, are matched preserving the losslessness of the gyrator as much as possible.

In order to appreciate the performance of the proposed topol- ogy, one can compare i t to a realization composed of a cascade of two all-pass biquads, of the type shown in Fig. 3. Each of those is constructed out of a G, - C version of the classical Tow-Thomas biquad using feed-forward paths. A cascade of two such biquads was used to achieve the 4th order equalization. A Monte Carlo analysis was done on both types of realizations and the results are shown in Fig. 4a (for the proposed topology) and Fig. 4b (for the biquad-type realization). -411 component values were uni- formly distributed around the nominal value, with a maximum deviation of 1% and 20 simulations were done for each topology.

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' l ' l i c following comparisons can be made: 1) The sensitivity of t l i v I ~ i q n a d t,ypc realization seems larger than that of the realiza- (.ion tlcscribed abovc. 2 ) The total number of transconductance amplifiers nccdcd for the biquad-type realization, namely 35, is 4 morc tha.11 that required by the proposed type, namely 31. Ap- proximately a savings of two amplifiers for every extra pair of iiiirrorcd poles and zeros. The resulting reduction in chip area i i l s o iriiprovcs the matching attainable, across the filter.

Random samples of 100 (Standard Deviation = 2%)

1,'igurc 5: 7''' order elliptic magnitude filter

4. Implementation of a T t h order elliptic magnitude Frequency (MHz) filter

I I

I

1 ,o . . . ~ ~ ~ . . , . ~ ~ ~ . ~

' I ' I i ( ~ specifications that were used were typical of a video anti- ;iliasing liltcr. (These specifications are indicated in Fig. 6). This rcyiiircd the usc of a. order elliptic approximation, which was iiiiplcmentcd using thc topology shown in Fig. 5 .

0.5 ....... J . ..

A G,,, - C continuous-time topology was used for superior high frcqucncy performance. Using signal flow graph analysis, i t c;i.ii I)c shown that the transmission zeros can be implemented hy connecting capacitors between appropriate nodes as shown in tlic figure. Matching achievable between two transconductance miiplifiers with non-integer G, ratios is usually quite worse than t , l i i ~ t , bctwocn two idcntical transconductance amplifiers. So, for dynamic range optimization, the nodes were scaled with multiple t y 11 i d - valii cd t ranscoii duct ance amplifiers.

Tlic niiist,er slave approach requires a filter topology suffi- cicntly iuscnsitivc to element mismatches across the chip. This is tlciiioiistrated i n Fig. 6, in which we show Monte Carlo simu- Iii.tioiis superimposed on the magnitude specifications to be met. ' l ' l i (~ clemcnt, mismatch standard deviation s.ssumed in the simu- 1;ihotis was 2%.

Tlic tralisconductsnce amplifier used is similar to the one sug- gcst.c~l i n [9], except for a folded cascode output stage to improve t l i ( y I)C ga,iii.

The dct.ails of tlic internal construction of the slave filter, tr~i.tiscoiiductaiice amplifier and the tuning circuit are reported chwhcre [lo].

b'ig. 7 shows the configuration of the master-slave tuning cir- cuit. Tlic inaster filter is a biquad which is scaled such that a t res- ona.nce, thc gain from input to its bandpass output is unity. The f,iiiiii~g scheme maintains a stable gain constant for the G, - C intcgrat,ors by phase-locking the master filter t o an external ref- ( I~CI ICC frcquency. Any phase errors in its integrators would cause i.he Ilandpass gain at resonance to deviate from unity [ll]. Using full-wavc rectifiers to detect the amplitude of both the incoming rcfcroncc signal and the bandpass output, any deviations of the gaiii from unity can be detected. The error signal thus generated can bc used to trim the phase of the integrators at unity gain frcqnciicy, using the phase control voltages Vphz and Vphp. The tlctails of how the two control voltages introduce a variable phase lead (or lag) in the transconductors is reported elsewhere [lo].

Thc tuning loop performs phase detection using the following scheme. Lowpass ontput from the biquad is converted into two complemcntary square waves A and A using a balanced compara- t,or. Similarly, anothcr pair of complementary square waves B and U are gcncrated from the input reference signal. Since the topol- ogy is fully balanced, each wave and its complement have similar

0 I 2 3 4 5 F r q u e n c y (MHz)

Figure 0: hlontc Carlo analysis of the slave filter

non-idealities. Also, an identical path is maintained for both the output from the biquad and the reference signal. To detect the phase difference between the square waves A and B (or A and B ) , instead of using a simple EXOR gate, two such gates are used, fed by A , A, B and B as shown in the figure, generating a pair of complementary outputs C and C. The tuning system forces C and c to have the same DC component. The lowpass output of the biquad is then in quadrature with the input reference signal. Since these outputs C and C , having the same non-idealities, are subtracted, the system is insensitive to the exact shape of square waves a t the output of the comparators and EXOR gates. The reference frequency used was 2.75 MHz.

The 7th order magnitude filter was implemented in a l p n-well CMOS process. Details about the chip implementations can be found elsewhere [lo]. The measured characteristics from [lo] are repeated for convenience in Table 1. 92 chips from various wafers were tested, and the design specifications were met with a high yield. The complete llth order filter consisting of a similar 7 th order elliptic filter and a 4th order equalizer is in fabrication.

5 . Conclusions

Our experience with this project indicates that transconductance- capacitance techniques can yield filters with tight specifications, suitable for video antialiasing applications. However to make this possible, one must be willing to delve into detailed device-level design, including careful consideration of parasitics.

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Acknowledgement The authors would like t o thank Texas Instruments, Dallas

for fabricating the chip, Khen-Sang Tan, R. K. Hester, John Fat- taruso and Michael DeWit for useful discussions and David Franck for helping in the layout.

References

[I] J. R. Canning and G. Wilson, ‘‘ Frequency discriminator cir- cuit arrangement,” UK Patent No. 1 4 2 1 093, Jan. 1976

121 K. Radhakrishna Rao, V. Sethuraman, and P. K. Neelakan- tan, “A novel ‘follow the master’ filter,” IEEE Proceedings, vol. 65, no. 12, pp. 1725-1726, Dec. 1977

[3] K. S. Tan and P. R. Gray, “Fully integrated analog filters using bipolar-JFET technology,” IEEE Journal of Solid-state Circuits, vol. SC-13, no. 6, pp. 811-821. Dec. 1978.

[4] F. Krummenacher and N . Joel, “ A 4 M H z CMOS Continuous-time filter with On-chip Automatic Tuning.’’ IEEE Journal of Solid-state Circuits, vol. SC-23, pp. 750- 758, June. 1988.

[5j Y. P. Tsividis, Operation and Modeling of the MOS Transis- lor, McGraw Hill, New York, 1987.

[6] D. Senderowicz, D.A. Hodges and Gray, P. R., “An NL4OS integrated vector-locked loop”, IEEE International Sympo- sium on CAS, pp 1164-1167, 1982.

[i] L. T. Bruton, RC-Active Circuits, Theory and Design, Prentice-Hall, Inc., Englewood Cliffs, 1980.

[8] H. J. Orchard, “Inductorless filters”, Electronics I.etters, pp

[9] Y. Tsividis, Z. Czarnul and S. C. Fang, “MOS transconduc- tors and integrators with high linearity”, Electronics Letters, vol 22: no. 5, pp. 245-246, Feb 27, 19%

[lo] V. Gopinathan, Y. Tsividis, R . K . Hester and E;. S. Tan, ”.? 5V, 71h-order Elliptic Analog Filter for Digital Video Appli- cations”, Digest, 1990 International Solid-state Circuits C o ~ i - ference, San Francisco.

i l l ] C. F. Choi and R. Schaumann, “Design and performance of a fully integrated bipolar 10.7 MHz analog bandpass filter,’‘ IEEE Journal of Solid-state Circuits, vol. SC-21, pp. 6-14, Feb. 1986.

224-225, NO. 2, 1966

Measured Chip Characteristics

Power supply voltage i2 .5 V

Passband edge frequency: Mean 4.36 MHz

Standard Deviation 0.1 1 MHz ~0 .08 MHz Temperature variation (0 to 70°C)

Passband ripple: Mean 1.24 dB

Standard Deviation 0.26 dB 20.20 dB

Better than 60 dB

Temperature variation (0 to 70T)

Stop-band attenuation

Differential input swing at 0.5% THD (worst case over the freq. range 0 to 4.4 MHz) 0.8 Vpp

Input referred in-band random noise 210 pv rms

Rcference signal feedthrough. referred to the input

Dynamic range [Signal / (Noise + Feedthrough))

Power supply rejection ratio (at passband edge):

130 pV rms

61 dB

VDD 49 dB vss 44 dB

Lock range of the tuning circuit

Power dissipation 75 mW

600 KHz to 6.8 MHz

Table 1:

Fraquenyl Contro l clrcult

Figure 7: Automat ic tuning circuit for frequency and phase control

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