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12

IEEE Std 1800-2009(Revision of

IEEE Std1800-2005)

IEEE Standard for SystemVerilog Unified Hardware Design, Specification, and Verification Language

SponsorDesign Automation Standards Committee of theIEEE Computer Society

and the IEEE Standards Association Corporate Advisory Group

Approved 11 November 2009IEEE-SA Standards Board

Abstract: This standard represents a merger of two previous standards: IEEE Std 1364-2005Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unifiedhardware design, specification, and verification language. The 2005 SystemVerilog standarddefines extensions to the 2005 Verilog standard. These two standards were designed to be usedas one language. Merging the base Verilog language and the SystemVerilog extensions into asingle standard provides users with all information regarding syntax and semantics in a singledocument.

Keywords: assertions, design automation, design verification, hardware description language,HDL, HDVL, PLI, programming language interface, SystemVerilog, Verilog, VPI

The Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USA

Copyright 2009 by the Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 11 December 2009. Printed in the United States of America.

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PDF: ISBN 978-0-7381-6129-7 STD96001

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Introduction

The purpose of this standard is to provide the electronic design automation (EDA), semiconductor, andsystem design communities with a well-defined and official IEEE unified hardware design, specification,and verification standard language. The language is designed to coexist and enhance the hardwaredescription and verification languages (HDVLs) presently used by designers while providing the capabilitieslacking in those languages.

SystemVerilog is a unified hardware design, specification, and verification language based on the AccelleraSystemVerilog 3.1a extensions to the Verilog HDL [B3]a, published in 2004. Accellera is a consortium ofEDA, semiconductor, and system companies. IEEE Std 1800 enables a productivity boost in design andvalidation and covers design, simulation, validation, and formal assertion-based verification flows.

SystemVerilog enables the use of a unified language for abstract and detailed specification of the design,specification of assertions, coverage, and testbench verification based on manual or automaticmethodologies. SystemVerilog offers application programming interfaces (APIs) for coverage andassertions, a vendor-independent API to access proprietary waveform file formats, and a directprogramming interface (DPI) to access proprietary functionality. SystemVerilog offers methods that allowdesigners to continue to use present design languages when necessary to leverage existing designs andintellectual property. This standardization project will provide the VLSI design engineers with a well-defined IEEE standard, which meets their requirements in design and validation, and which enables a stepfunction increase in their productivity. This standardization project will also provide the EDA industry witha standard to which they can adhere and which they can support in order to deliver their solutions in thisarea.

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This document is copyrighted by the IEEE. It is made available for a wide variety of both public and privateuses. These include both use, by reference, in laws and regulations, and use in private self-regulation,standardization, and the promotion of engineering practices and methods. By making this documentavailable for use and adoption by public authorities and private users, the IEEE does not waive any rights incopyright to this document.

aThe numbers in brackets correspond to the numbers in the bibliography in Annex R.

This introduction is not a part of IEEE Std 1800-2009, IEEE Standard for SystemVerilogUnified HardwareDesign, Specification, and Verification Language.iv Copyright 2009 IEEE. All rights reserved.

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Users of IEEE standards should be aware that these documents may be superseded at any time by theissuance of new editions or may be amended from time to time through the issuance of amendments,corrigenda, or errata. An official IEEE document at any point in time consists of the current edition of thedocument together with any amendments, corrigenda, or errata then in effect. In order to determine whethera given document is the current edition and whether it has been amended through the issuance ofamendments, corrigenda, or errata, visit the IEEE Standards Association website at http://ieeexplore.ieee.org/xpl/standards.jsp, or contact the IEEE at the address listed previously.

For more information about the IEEE Standards Association or the IEEE standards development process,visit the IEEE-SA website at http://standards.ieee.org.

Errata

Errata, if any, for this and all other standards can be accessed at the following URL: http://standards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL forerrata periodically.

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Current interpretations can be accessed at the following URL: http://standards.ieee.org/reading/ieee/interp/index.html.

Patents

Attention is called to the possibility that implementation of this amendment may require use of subjectmatter covered by patent rights. By publication of this amendment, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEEE is not responsible for identifyingEssential Patent Claims for which a license may be required, for conducting inquiries into the legal validityor scope of Patents Claims or determining whether any licensing terms or conditions provided in connectionwith submission of a Letter of Assurance, if any, or in any licensing agreements are reasonable or non-discriminatory. Users of this amendment are expressly advised that determination of the validity of anypatent rights, and the risk of infringement of such rights, is entirely their own responsibility. Furtherinformation may be obtained from the IEEE Standards Association.Copyright 2009 IEEE. All rights reserved. v

http://standards.ieee.orghttp://ieeexplore.ieee.org/xpl/standards.jsphttp://ieeexplore.ieee.org/xpl/standards.jsphttp://standards.ieee.org/reading/ieee/updates/errata/index.htmlhttp://standards.ieee.org/reading/ieee/updates/errata/index.htmlhttp://standards.ieee.org/reading/ieee/interp/index.html

Participants

The SystemVerilog Language Working Group is entity based. At the time this standard was completed,the SystemVerilog Working Group had the following membership:

Karen Pieper, Accellera Representative, Tabula, Inc., Chair Neil Korpusik, Sun Microsystems, Inc., Vice Chair Johny Srouji, Apple Computer, Inc., Chair emeritus

Dennis Brophy, Mentor Graphics Corporation, Secretary Neil Korpusik, Sun Microsystems, Inc., Technical Chair

Stuart Sutherland, Sutherland HDL, Inc., Technical Editor

Work on this standard was divided among primary committees.

The Champions Committee was responsible for ensuring consistency in the work done by each committee.

Neil Korpusik, Sun Microsystems, Inc., Chair Dave Rich, Mentor Graphics Corporation, Co-Chair

The Basic/Design Committee (SV-BC) was responsible for the specification of the design features ofSystemVerilog.

Matt Maidment, Intel Corporation, Chair Brad Pierce, Synopsys, Inc., Co-Chair

The Enhancement Committee (SV-EC) was responsible for the specification of the testbench features ofSystemVerilog.

Mehdi Mohtashemi, Synopsys, Inc., Chair Neil Korpusik, Sun Microsystems, Inc., Co-Chair

Charles Dawson, Cadence Design Systems, Inc.Yossi Levi, Intel Corporation

Mehdi Mohtashemi, Synopsys, Inc.

Shalom Bresticker, Intel CorporationSurrendra Dudani, Synopsys, Inc.

John Havlicek, Freescale, Inc.

Francoise Martinolle, Cadence Design Systems, Inc. Brad Pierce, Synopsys, Inc.

Stuart Sutherland, Sutherland HDL, Inc.

Tom Alsop, Intel Corporation Shalom Bresticker, Intel Corporation

Heath Chambers, HMC Design Verification, Inc. Cliff Cummings, Sunburst Design, Inc.

Alex Gran, Mentor Graphics Corporation Mark Hartoog, Synopsys, Inc.

Francoise Martinolle, Cadence Design Systems, Inc.

Don Mills, LCDM Engineering Karen Pieper, Accellera, Tabula, Inc.

Dave Rich, Mentor Graphics Corporation Steven Sharp, Cadence Design Systems, Inc.

Stuart Sutherland, Sutherland HDL, Inc. Gordon Vreugdenhil, Mentor Graphics Corporation

Doug Warmke, Mentor Graphics Corporation

Jonathan Bromley, Doulos, Ltd. Mike Burns, Freescale, Inc.

Heath Chambers, HMC Design Verification, Inc. Geoffrey Coram, Analog Devices, Inc. Cliff Cummings, Sunburst Design, Inc.

Mark Hartoog, Synopsys, Inc. Francoise Martinolle, Cadence Design Systems, Inc.

Don Mills, LCDM Engineering Mike Mintz, Trusster, Inc.

Dave Rich, Mentor Graphics Corporation Ray Ryan, Mentor Graphics Corporation

Arturo Salz, Synopsys, Inc. David Scott, Mentor Graphics Corporation

Steven Sharp, Cadence Design Systems, Inc. Stuart Sutherland, Sutherland HDL, Inc.

Gordon Vreugdenhil, Mentor Graphics Corporation Doug Warmke, Mentor Graphics Corporation vi Copyright 2009 IEEE. All rights reserved.

The Assertions Committee (SV-AC) was responsible for the specification of the assertion features ofSystemVerilog.

Dmitry Korchemny, Intel Corporation, Chair Tom Thatcher, Sun Microsystems, Inc., Co-Chair

The C API Committee (SV-CC) was responsible for on the specification of the DPI, the SystemVerilogVerification Procedural Interace (VPI), and the additional coverage API.

Charles Dawson, Cadence Design Systems, Inc., Chair Ghassan Khoory, Synopsys, Inc., Co-Chair

The Special Committee (SV-SC) was responsible for defining the new checker constructs, while alsomaintaining consistency among checkers, assertions, and other aspects of SystemVerilog.

Erik Seligman, Intel Corporation, Chair Tom Thatcher, Sun Microsystems, Inc., Co-Chair

The following members of the entity balloting committee voted on this standard. Balloters may have votedfor approval, disapproval, or abstention.

Doron Bustan, Intel Corporation Ed Cerny, Synopsys, Inc.

Surrendra Dudani, Synopsys, Inc. Yaniv Fais, Freescale, Inc.

John Havlicek, Freescale, Inc.

Manisha Kulshrestha, Mentor Graphics Corporation Johan Martensson, Jasper Communications, Inc.

Lisa Piper, Cadence Design Systems, Inc.Erik Seligman, Intel CorporationBassam Tabbara, Synopsys, Inc.

Anil Arora, Mentor Graphics CorporationChuck Berking, Cadence Design Systems, Inc. Steven Dovich, Cadence Design Systems, Inc.

Ralph Duncan, CloudShield TechnologiesAmit Kohli, Cadence Design Systems, Inc.

Andrzej Litwiniuk, Synopsys, Inc.

Francoise Martinolle, Cadence Design Systems, Inc. Abigail Moorhouse, Mentor Graphics Corporation

Michael Rohleder, Freescale, Inc. John Shields, Mentor Graphics Corporation

Bassam Tabbara, Synopsys, Inc.Jim Vellenga, Cadence Design Systems, Inc.

Mike Burns, Freescale, Inc.Eduard Cerny, Synopsys, Inc.

Mirek Forczek, Aldec, Inc.Mark Hartoog, Synopsys, Inc.John Havlicek, Freescale, Inc.

Dmitry Korchemny, Intel CorporationNeil Korpusik, Sun Microsystems, Inc.

Manisha Kulshrestha, Mentor Graphics Corporation

Francoise Martinolle, Cadence Design Systems, Inc.Mehdi Mohtashemi, Synopsys, Inc.

Abigail Moorhouse, Mentor Graphics CorporationLisa Piper, Cadence Design Systems, Inc.Dave Rich, Mentor Graphics Corporation

Steven Sharp, Cadence Design Systems, Inc.Gordon Vreugdenhil, Mentor Graphics Corporation

Jin Yang, Intel Corporation

ARM Ltd.Accellera

Cadence DesignFreescale Semiconductor

Intel

JEITAMentor Graphics

Sun MicrosystemsSynopsys

XilinxCopyright 2009 IEEE. All rights reserved. vii

When the IEEE-SA Standards Board approved this standard on 11 November 2009, it had the followingmembership:

Robert M. Grow, ChairThomas Prevost, Vice ChairSteve M. Mills, Past ChairJudith Gorman, Secretary

*Member Emeritus

Also included are the following nonvoting IEEE-SA Standards Board liaisons:

Howard L. Wolfman, TAB RepresentativeMichael Janezic, NIST Representative

Satish K. Aggarwal, NRC Representative

Michelle TurnerIEEE Standards Program Manager, Document Development

Chris VigilIEEE Manager, Standards Development Services

Noelle HumenickIEEE Corporate Client Manager

John BarrKaren BartlesonVictor BermanTed BurseRichard DeBlasioAndy DrozdMark Epstein

Alexander GelmanJim HughesRichard H. HulettYoung Kyun KimJoseph L. Koepfinger*John Kulick

David J. LawTed OlsenGlenn ParsonsRonald C. PetersenNarayanan RamachandranJon Walter RosdahlSam Sciacca viii Copyright 2009 IEEE. All rights reserved.

Contents

Part One: Design and Verification Constructs1. Overview.................................................................................................................................................... 2

1.1 Scope................................................................................................................................................ 21.2 Purpose............................................................................................................................................. 21.3 Merger of IEEE Std 1364-2005 and IEEE Std 1800-2005.............................................................. 31.4 Special terms.................................................................................................................................... 31.5 Conventions used in this standard ................................................................................................... 31.6 Syntactic description........................................................................................................................ 41.7 Use of color in this standard ............................................................................................................ 51.8 Contents of this standard.................................................................................................................. 51.9 Deprecated clauses........................................................................................................................... 81.10 Examples.......................................................................................................................................... 81.11 Prerequisites..................................................................................................................................... 8

2. Normative references ................................................................................................................................. 93. Design and verification building blocks .................................................................................................. 11

3.1 General........................................................................................................................................... 113.2 Design elements ............................................................................................................................. 113.3 Modules ......................................................................................................................................... 113.4 Programs ........................................................................................................................................ 123.5 Interfaces........................................................................................................................................ 133.6 Checkers......................................................................................................................................... 143.7 Primitives ....................................................................................................................................... 143.8 Subroutines .................................................................................................................................... 143.9 Packages......................................................................................................................................... 143.10 Configurations ............................................................................................................................... 153.11 Overview of hierarchy ................................................................................................................... 153.12 Compilation and elaboration.......................................................................................................... 163.13 Name spaces .................................................................................................................................. 183.14 Simulation time units and precision............................................................................................... 19

4. Scheduling semantics............................................................................................................................... 234.1 General........................................................................................................................................... 234.2 Execution of a hardware model and its verification environment ................................................. 234.3 Event simulation ............................................................................................................................ 234.4 The stratified event scheduler ........................................................................................................ 244.5 The SystemVerilog simulation reference algorithm...................................................................... 294.6 Determinism................................................................................................................................... 294.7 Nondeterminism............................................................................................................................. 304.8 Race conditions.............................................................................................................................. 304.9 Scheduling implication of assignments ......................................................................................... 304.10 The PLI callback control points..................................................................................................... 32

5. Lexical conventions ................................................................................................................................. 335.1 General........................................................................................................................................... 335.2 Lexical tokens ................................................................................................................................ 335.3 White space.................................................................................................................................... 335.4 Comments ...................................................................................................................................... 335.5 Operators........................................................................................................................................ 335.6 Identifiers, keywords, and system names ...................................................................................... 345.7 Numbers......................................................................................................................................... 355.8 Time literals ................................................................................................................................... 40Copyright 2009 IEEE. All rights reserved. ix

5.9 String literals.................................................................................................................................. 405.10 Structure literals ............................................................................................................................. 425.11 Array literals .................................................................................................................................. 435.12 Attributes ....................................................................................................................................... 435.13 Built-in methods ............................................................................................................................ 45

6. Data types ................................................................................................................................................ 476.1 General........................................................................................................................................... 476.2 Data types and data objects............................................................................................................ 476.3 Value set ........................................................................................................................................ 476.4 Singular and aggregate types ......................................................................................................... 486.5 Nets and variables .......................................................................................................................... 496.6 Net types ........................................................................................................................................ 506.7 Net declarations ............................................................................................................................. 566.8 Variable declarations ..................................................................................................................... 586.9 Vector declarations ........................................................................................................................ 606.10 Implicit declarations ...................................................................................................................... 616.11 Integer data types ........................................................................................................................... 626.12 Real, shortreal and realtime data types .......................................................................................... 636.13 Void data type ................................................................................................................................ 636.14 Chandle data type........................................................................................................................... 636.15 Class............................................................................................................................................... 646.16 String data type .............................................................................................................................. 646.17 Event data type............................................................................................................................... 696.18 User-defined types ......................................................................................................................... 706.19 Enumerations ................................................................................................................................. 716.20 Constants........................................................................................................................................ 776.21 Scope and lifetime ......................................................................................................................... 846.22 Type compatibility ......................................................................................................................... 866.23 Type operator ................................................................................................................................. 896.24 Casting ........................................................................................................................................... 90

7. Aggregate data types................................................................................................................................ 977.1 General........................................................................................................................................... 977.2 Structures ....................................................................................................................................... 977.3 Unions ............................................................................................................................................ 997.4 Packed and unpacked arrays ........................................................................................................ 1027.5 Dynamic arrays ............................................................................................................................ 1067.6 Array assignments........................................................................................................................ 1097.7 Arrays as arguments to subroutines ............................................................................................. 1107.8 Associative arrays ........................................................................................................................ 1117.9 Associative array methods ........................................................................................................... 1147.10 Queues ......................................................................................................................................... 1177.11 Array querying functions ............................................................................................................. 1217.12 Array manipulation methods ....................................................................................................... 121

8. Classes ................................................................................................................................................... 1278.1 General......................................................................................................................................... 1278.2 Overview...................................................................................................................................... 1278.3 Syntax .......................................................................................................................................... 1288.4 Objects (class instance)................................................................................................................ 1298.5 Object properties and object parameter data................................................................................ 1308.6 Object methods ............................................................................................................................ 1308.7 Constructors ................................................................................................................................. 1318.8 Static class properties................................................................................................................... 1328.9 Static methods.............................................................................................................................. 133x Copyright 2009 IEEE. All rights reserved.

8.10 This .............................................................................................................................................. 1338.11 Assignment, renaming, and copying............................................................................................ 1348.12 Inheritance and subclasses ........................................................................................................... 1358.13 Overridden members.................................................................................................................... 1368.14 Super ............................................................................................................................................ 1378.15 Casting ......................................................................................................................................... 1378.16 Chaining constructors .................................................................................................................. 1388.17 Data hiding and encapsulation ..................................................................................................... 1388.18 Constant class properties ............................................................................................................. 1398.19 Virtual methods............................................................................................................................ 1408.20 Abstract classes and pure virtual methods ................................................................................... 1418.21 Polymorphism: dynamic method lookup..................................................................................... 1418.22 Class scope resolution operator :: ................................................................................................ 1428.23 Out-of-block declarations ............................................................................................................ 1448.24 Parameterized classes .................................................................................................................. 1458.25 Typedef class ............................................................................................................................... 1488.26 Classes and structures .................................................................................................................. 1498.27 Memory management .................................................................................................................. 149

9. Processes ................................................................................................................................................ 1519.1 General......................................................................................................................................... 1519.2 Structured procedures .................................................................................................................. 1519.3 Block statements .......................................................................................................................... 1559.4 Procedural timing controls........................................................................................................... 1619.5 Process execution threads ............................................................................................................ 1709.6 Process control ............................................................................................................................. 1719.7 Fine-grain process control ........................................................................................................... 175

10. Assignment statements .......................................................................................................................... 17710.1 General......................................................................................................................................... 17710.2 Overview...................................................................................................................................... 17710.3 Continuous assignments .............................................................................................................. 17810.4 Procedural assignments................................................................................................................ 18110.5 Variable declaration assignment (variable initialization) ............................................................ 18610.6 Procedural continuous assignments ............................................................................................. 18610.7 Assignment extension and truncation .......................................................................................... 18810.8 Assignment-like contexts............................................................................................................. 18910.9 Assignment patterns..................................................................................................................... 19010.10 Unpacked array concatenation..................................................................................................... 19410.11 Net aliasing .................................................................................................................................. 197

11. Operators and expressions ..................................................................................................................... 19911.1 General......................................................................................................................................... 19911.2 Overview...................................................................................................................................... 19911.3 Operators...................................................................................................................................... 20011.4 Operator descriptions ................................................................................................................... 20411.5 Operands ...................................................................................................................................... 22411.6 Expression bit lengths .................................................................................................................. 22711.7 Signed expressions....................................................................................................................... 23011.8 Expression evaluation rules ......................................................................................................... 23111.9 Tagged union expressions and member access............................................................................ 23211.10 String literal expressions.............................................................................................................. 23411.11 Operator overloading ................................................................................................................... 23511.12 Minimum, typical, and maximum delay expressions .................................................................. 23711.13 Let construct ................................................................................................................................ 238

12. Procedural programming statements ..................................................................................................... 245Copyright 2009 IEEE. All rights reserved. xi

12.1 General......................................................................................................................................... 24512.2 Overview...................................................................................................................................... 24512.3 Syntax .......................................................................................................................................... 24512.4 Conditional ifelse statement....................................................................................................... 24612.5 Case statement ............................................................................................................................. 25112.6 Pattern matching conditional statements ..................................................................................... 25612.7 Loop statements ........................................................................................................................... 26012.8 Jump statements ........................................................................................................................... 264

13. Tasks and functions (subroutines) ......................................................................................................... 26713.1 General......................................................................................................................................... 26713.2 Overview...................................................................................................................................... 26713.3 Tasks ............................................................................................................................................ 26713.4 Functions...................................................................................................................................... 27113.5 Subroutine calls and argument passing........................................................................................ 27713.6 Import and export functions......................................................................................................... 28213.7 Task and function names ............................................................................................................. 282

14. Clocking blocks ..................................................................................................................................... 28314.1 General......................................................................................................................................... 28314.2 Overview...................................................................................................................................... 28314.3 Clocking block declaration .......................................................................................................... 28314.4 Input and output skews ................................................................................................................ 28514.5 Hierarchical expressions .............................................................................................................. 28614.6 Signals in multiple clocking blocks ............................................................................................. 28714.7 Clocking block scope and lifetime............................................................................................... 28714.8 Multiple clocking blocks example ............................................................................................... 28714.9 Interfaces and clocking blocks..................................................................................................... 28814.10 Clocking block events.................................................................................................................. 28914.11 Cycle delay: ## ............................................................................................................................ 28914.12 Default clocking........................................................................................................................... 29014.13 Input sampling ............................................................................................................................. 29114.14 Global clocking............................................................................................................................ 29214.15 Synchronous events ..................................................................................................................... 29314.16 Synchronous drives...................................................................................................................... 293

15. Interprocess synchronization and communication................................................................................. 29915.1 General......................................................................................................................................... 29915.2 Overview...................................................................................................................................... 29915.3 Semaphores .................................................................................................................................. 29915.4 Mailboxes..................................................................................................................................... 30115.5 Named events............................................................................................................................... 304

16. Assertions............................................................................................................................................... 30916.1 General......................................................................................................................................... 30916.2 Overview...................................................................................................................................... 30916.3 Immediate assertions.................................................................................................................... 30916.4 Deferred assertions ...................................................................................................................... 31216.5 Concurrent assertions overview................................................................................................... 31616.6 Boolean expressions .................................................................................................................... 31816.7 Sequences..................................................................................................................................... 32016.8 Declaring sequences .................................................................................................................... 32316.9 Sequence operations .................................................................................................................... 33116.10 Local variables ............................................................................................................................. 35316.11 Calling subroutines on match of a sequence................................................................................ 35916.12 System functions.......................................................................................................................... 36016.13 Declaring properties..................................................................................................................... 360xii Copyright 2009 IEEE. All rights reserved.

16.14 Multiclock support ....................................................................................................................... 38516.15 Concurrent assertions................................................................................................................... 39316.16 Disable iff resolution ................................................................................................................... 41016.17 Clock resolution ........................................................................................................................... 41216.18 Expect statement .......................................................................................................................... 41716.19 Clocking blocks and concurrent assertions.................................................................................. 419

17. Checkers................................................................................................................................................. 42117.1 Overview...................................................................................................................................... 42117.2 Checker declaration ..................................................................................................................... 42117.3 Checker instantiation ................................................................................................................... 42417.4 Context inference ......................................................................................................................... 42717.5 Checker procedures...................................................................................................................... 42717.6 Covergroups in checkers.............................................................................................................. 42817.7 Checker variables......................................................................................................................... 42917.8 Functions in checkers................................................................................................................... 43517.9 Complex checker example........................................................................................................... 435

18. Constrained random value generation ................................................................................................... 43718.1 General......................................................................................................................................... 43718.2 Overview...................................................................................................................................... 43718.3 Concepts and usage...................................................................................................................... 43718.4 Random variables ........................................................................................................................ 44018.5 Constraint blocks ......................................................................................................................... 44218.6 Randomization methods .............................................................................................................. 45718.7 In-line constraintsrandomize() with......................................................................................... 45918.8 Disabling random variables with rand_mode() ........................................................................... 46118.9 Controlling constraints with constraint_mode() .......................................................................... 46318.10 Dynamic constraint modification................................................................................................. 46418.11 In-line random variable control ................................................................................................... 46418.12 Randomization of scope variablesstd::randomize()................................................................. 46518.13 Random number system functions and methods ......................................................................... 46718.14 Random stability .......................................................................................................................... 46818.15 Manually seeding randomize ....................................................................................................... 47118.16 Random weighted caserandcase .............................................................................................. 47118.17 Random sequence generationrandsequence............................................................................. 472

19. Functional coverage ............................................................................................................................... 48319.1 General......................................................................................................................................... 48319.2 Overview...................................................................................................................................... 48319.3 Defining the coverage model: covergroup................................................................................... 48419.4 Using covergroup in classes ........................................................................................................ 48619.5 Defining coverage points ............................................................................................................. 48819.6 Defining cross coverage............................................................................................................... 49819.7 Specifying coverage options ........................................................................................................ 50319.8 Predefined coverage methods ...................................................................................................... 50719.9 Predefined coverage system tasks and system functions............................................................. 50919.10 Organization of option and type_option members ...................................................................... 50919.11 Coverage computation ................................................................................................................. 510

20. Utility system tasks and system functions ............................................................................................. 51520.1 General......................................................................................................................................... 51520.2 Simulation control system tasks .................................................................................................. 51620.3 Simulation time system functions................................................................................................ 51620.4 Timescale system tasks ................................................................................................................ 51820.5 Conversion functions ................................................................................................................... 52120.6 Data query functions .................................................................................................................... 522Copyright 2009 IEEE. All rights reserved. xiii

20.7 Array querying functions ............................................................................................................. 52420.8 Math functions ............................................................................................................................. 52620.9 Severity tasks ............................................................................................................................... 52820.10 Elaboration system tasks.............................................................................................................. 52820.11 Assertion control system tasks..................................................................................................... 53020.12 Assertion action control system tasks .......................................................................................... 53120.13 Assertion system functions .......................................................................................................... 53320.14 Coverage system functions .......................................................................................................... 53420.15 Probabilistic distribution functions .............................................................................................. 53420.16 Stochastic analysis tasks and functions ....................................................................................... 53620.17 Programmable logic array (PLA) modeling system tasks ........................................................... 53820.18 Miscellaneous tasks and functions............................................................................................... 542

21. I/O system tasks and system functions .................................................................................................. 54321.1 General......................................................................................................................................... 54321.2 Display system tasks .................................................................................................................... 54321.3 File input-output system tasks and system functions................................................................... 55421.4 Loading memory array data from a file ....................................................................................... 56521.5 Writing memory array data to a file............................................................................................. 56821.6 Command line input..................................................................................................................... 56921.7 Value change dump (VCD) files ................................................................................................. 572

22. Compiler directives................................................................................................................................ 59322.1 General......................................................................................................................................... 59322.2 Overview ..................................................................................................................................... 59322.3 `resetall......................................................................................................................................... 59322.4 `include ........................................................................................................................................ 59422.5 `define, `undef and `undefineall .................................................................................................. 59422.6 `ifdef, `else, `elsif, `endif, `ifndef ................................................................................................ 60022.7 `timescale ..................................................................................................................................... 60322.8 `default_nettype ........................................................................................................................... 60422.9 `unconnected_drive and `nounconnected_drive .......................................................................... 60522.10 `celldefine and `endcelldefine...................................................................................................... 60522.11 `pragma ........................................................................................................................................ 60522.12 `line .............................................................................................................................................. 60622.13 `__FILE__ and `__LINE__ ......................................................................................................... 60722.14 `begin_keywords, `end_keywords ............................................................................................... 608

Part Two: Hierarchy Constructs23. Modules and hierarchy........................................................................................................................... 614

23.1 General......................................................................................................................................... 61423.2 Module definitions ....................................................................................................................... 61423.3 Module instances (hierarchy)....................................................................................................... 62623.4 Nested modules............................................................................................................................ 63623.5 Extern modules ............................................................................................................................ 63723.6 Hierarchical names ...................................................................................................................... 63823.7 Member selects and hierarchical names ...................................................................................... 64123.8 Upwards name referencing .......................................................................................................... 64223.9 Scope rules .................................................................................................................................. 64423.10 Overriding module parameters .................................................................................................... 64623.11 Binding auxiliary code to scopes or instances ............................................................................. 654

24. Programs ................................................................................................................................................ 65924.1 General......................................................................................................................................... 65924.2 Overview...................................................................................................................................... 659xiv Copyright 2009 IEEE. All rights reserved.

24.3 The program construct ................................................................................................................. 65924.4 Eliminating testbench races ......................................................................................................... 66324.5 Blocking tasks in cycle/event mode............................................................................................. 66324.6 Programwide space and anonymous programs............................................................................ 66424.7 Program control tasks .................................................................................................................. 664

25. Interfaces................................................................................................................................................ 66525.1 General......................................................................................................................................... 66525.2 Overview...................................................................................................................................... 66525.3 Interface syntax............................................................................................................................ 66625.4 Ports in interfaces......................................................................................................................... 67025.5 Modports ...................................................................................................................................... 67125.6 Interfaces and specify blocks ....................................................................................................... 67725.7 Tasks and functions in interfaces................................................................................................. 67825.8 Parameterized interfaces .............................................................................................................. 68425.9 Virtual interfaces.......................................................................................................................... 68625.10 Access to interface objects........................................................................................................... 691

26. Packages................................................................................................................................................. 69326.1 General......................................................................................................................................... 69326.2 Package declarations.................................................................................................................... 69326.3 Referencing data in packages ...................................................................................................... 69426.4 Using packages in module headers .............................................................................................. 69826.5 Search order rules ........................................................................................................................ 69926.6 Exporting imported names from packages .................................................................................. 70126.7 The std built-in package............................................................................................................... 702

27. Generate constructs................................................................................................................................ 70527.1 General......................................................................................................................................... 70527.2 Overview...................................................................................................................................... 70527.3 Generate construct syntax ............................................................................................................ 70527.4 Loop generate constructs ............................................................................................................. 70727.5 Conditional generate constructs................................................................................................... 71127.6 External names for unnamed generate blocks ............................................................................. 714

28. Gate-level and switch-level modeling ................................................................................................... 71728.1 General......................................................................................................................................... 71728.2 Overview...................................................................................................................................... 71728.3 Gate and switch declaration syntax ............................................................................................. 71728.4 and, nand, nor, or, xor, and xnor gates......................................................................................... 72328.5 buf and not gates .......................................................................................................................... 72428.6 bufif1, bufif0, notif1, and notif0 gates......................................................................................... 72528.7 MOS switches .............................................................................................................................. 72628.8 Bidirectional pass switches .......................................................................................................... 72728.9 CMOS switches ........................................................................................................................... 72828.10 pullup and pulldown sources ....................................................................................................... 72928.11 Logic strength modeling .............................................................................................................. 72928.12 Strengths and values of combined signals ................................................................................... 73128.13 Strength reduction by nonresistive devices ................................................................................. 74428.14 Strength reduction by resistive devices ....................................................................................... 74428.15 Strengths of net types................................................................................................................... 74428.16 Gate and net delays ...................................................................................................................... 745

29. User defined primitives (UDPs) ............................................................................................................ 74929.1 General......................................................................................................................................... 74929.2 Overview...................................................................................................................................... 74929.3 UDP definition............................................................................................................................. 74929.4 Combinational UDPs ................................................................................................................... 753Copyright 2009 IEEE. All rights reserved. xv

29.5 Level-sensitive sequential UDPs ................................................................................................. 75429.6 Edge-sensitive sequential UDPs .................................................................................................. 75429.7 Sequential UDP initialization ...................................................................................................... 75529.8 UDP instances.............................................................................................................................. 75729.9 Mixing level-sensitive and edge-sensitive descriptions............................................................... 75829.10 Level-sensitive dominance .......................................................................................................... 759

30. Specify blocks........................................................................................................................................ 76130.1 General......................................................................................................................................... 76130.2 Overview...................................................................................................................................... 76130.3 Specify block declaration............................................................................................................. 76130.4 Module path declarations............................................................................................................. 76230.5 Assigning delays to module paths ............................................................................................... 77130.6 Mixing module path delays and distributed delays ..................................................................... 77530.7 Detailed control of pulse filtering behavior ................................................................................. 776

31. Timing checks........................................................................................................................................ 78531.1 General......................................................................................................................................... 78531.2 Overview...................................................................................................................................... 78531.3 Timing checks using a stability window...................................................................................... 78831.4 Timing checks for clock and control signals ............................................................................... 79531.5 Edge-control specifiers ................................................................................................................ 80431.6 Notifiers: user-defined responses to timing violations ................................................................ 80531.7 Enabling timing checks with conditioned events ........................................................................ 80731.8 Vector signals in timing checks ................................................................................................... 80831.9 Negative timing checks................................................................................................................ 809

32. Backannotation using the standard delay format (SDF) ........................................................................ 81532.1 General......................................................................................................................................... 81532.2 Overview...................................................................................................................................... 81532.3 The SDF annotator....................................................................................................................... 81532.4 Mapping of SDF constructs to SystemVerilog ............................................................................ 81532.5 Multiple annotations .................................................................................................................... 82032.6 Multiple SDF files ....................................................................................................................... 82132.7 Pulse limit annotation .................................................................................................................. 82132.8 SDF to SystemVerilog delay value mapping............................................................................... 82232.9 Loading timing data from an SDF file......................................................................................... 822

33. Configuring the contents of a design ..................................................................................................... 82533.1 General......................................................................................................................................... 82533.2 Overview...................................................................................................................................... 82533.3 Libraries ....................................................................................................................................... 82633.4 Configurations ............................................................................................................................. 82833.5 Using libraries and configs .......................................................................................................... 83433.6 Configuration examples ............................................................................................................... 83533.7 Displaying library binding information ....................................................................................... 83733.8 Library mapping examples .......................................................................................................... 837

34. Protected envelopes ............................................................................................................................... 84134.1 General......................................................................................................................................... 84134.2 Overview...................................................................................................................................... 84134.3 Processing protected envelopes ................................................................................................... 84134.4 Protect pragma directives............................................................................................................. 84334.5 Protect pragma keywords............................................................................................................. 845xvi Copyright 2009 IEEE. All rights reserved.

Part Three: Application Programming Interfaces35. Direct programming interface (DPI)...................................................................................................... 862

35.1 General......................................................................................................................................... 86235.2 Overview...................................................................................................................................... 86235.3 Two layers of the DPI .................................................................................................................. 86335.4 Global name space of imported and exported functions.............................................................. 86435.5 Imported tasks and functions ....................................................................................................... 86535.6 Calling imported functions .......................................................................................................... 87235.7 Exported functions ....................................................................................................................... 87435.8 Exported tasks.............................................................................................................................. 87535.9 Disabling DPI tasks and functions............................................................................................... 875

36. Programming language interface (PLI/VPI) overview.......................................................................... 87736.1 General......................................................................................................................................... 87736.2 PLI purpose and history ............................................................................................................... 87736.3 User-defined system task and system function names................................................................. 87836.4 User-defined system task and system function arguments .......................................................... 87936.5 User-defined system task and system function types .................................................................. 87936.6 User-supplied PLI applications.................................................................................................... 87936.7 PLI include files........................................................................................................................... 87936.8 VPI sizetf, compiletf and calltf routines ...................................................................................... 87936.9 PLI mechanism ............................................................................................................................ 88036.10 VPI access to SystemVerilog objects and simulation objects ..................................................... 88236.11 List of VPI routines by functional category................................................................................. 88336.12 VPI backwards compatibility features and limitations ................................................................ 885

37. VPI object model diagrams.................................................................................................................... 89137.1 General......................................................................................................................................... 89137.2 VPI Handles ................................................................................................................................. 89137.3 VPI object classifications............................................................................................................. 89237.4 Key to data model diagrams ........................................................................................................ 89837.5 Module ....................................................................................................................................... 90137.6 Interface .................................................................................................................................... 90237.7 Modport ...................................................................................................................................... 90237.8 Interface task or function declaration ......................................................................................... 90237.9 Program ..................................................................................................................................... 90337.10 Instance ....................................................................................................................................... 90437.11 Instance arrays ............................................................................................................................ 90637.12 Scope ........................................................................................................................................... 90737.13 IO declaration ............................................................................................................................. 90837.14 Ports ............................................................................................................................................ 90937.15 Reference objects ........................................................................................................................ 91037.16 Nets .............................................................................................................................................. 91337.17 Variables ..................................................................................................................................... 91737.18 Packed array variables ................................................................................................................ 92037.19 Variable select ............................................................................................................................. 92137.20 Memory........................................................................................................................................ 92237.21 Variable drivers and loads .......................................................................................................... 92237.22 Object Range................................................................................................................................ 92337.23 Typespec ..................................................................................................................................... 92437.24 Structures and unions................................................................................................................... 92637.25 Named events .............................................................................................................................. 92737.26 Parameter, spec param, def param, param assign ...................................................................... 92837.27 Class definition ........................................................................................................................... 929Copyright 2009 IEEE. All rights reserved. xvii

37.28 Class typespec ............................................................................................................................. 93037.29 Class variables and class objects ................................................................................................. 93237.30 Constraint, constraint ordering, distribution ............................................................................... 93437.31 Primitive, prim term..................................................................................................................... 93537.32 UDP ............................................................................................................................................. 93637.33 Intermodule path .......................................................................................................................... 93637.34 Constraint expression .................................................................................................................. 93737.35 Module path, path term ............................................................................................................... 93737.36 Timing check ............................................................................................................................... 93837.37 Task and function declaration ..................................................................................................... 93937.38 Task and function call ................................................................................................................. 94037.39 Frames ......................................................................................................................................... 94237.40 Threads ........................................................................................................................................ 94337.41 Delay terminals ............................................................................................................................ 94337.42 Net drivers and loads ................................................................................................................... 94437.43 Continuous assignment .............................................................................