IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I ...dchen.web.engr.illinois.edu/research/nFPGA-TCAS.pdfA programmable logic array (PLA)-based architecture, namely, nanoPLA, was presented

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 11, NOVEMBER 2007 2489

3-D nFPGA: A Reconfigurable Architecture for 3-DCMOS/Nanomaterial Hybrid Digital Circuits

Chen Dong, Deming Chen, Member, IEEE, Sansiri Haruehanroengra, and Wei Wang, Member, IEEE

Abstract—In this paper, we introduce a novel reconfigurablearchitecture, named 3-D field-programmable gate array (3-DnFPGA), which utilizes 3-D integration techniques and newnanoscale materials synergistically. The proposed architecture isbased on CMOS nanohybrid techniques that incorporate nanoma-terials such as carbon nanotube bundles and nanowire crossbarsinto CMOS fabrication process. This architecture also has built-infeatures for fault tolerance and heat alleviation. Using uniquefeatures of FPGAs and a novel 3-D stacking method enabledby the application of nanomaterials, 3-D nFPGA obtains a 4footprint reduction comparing to the traditional CMOS-based 2-DFPGAs. With a customized design automation flow, we evaluatethe performance and power of 3-D nFPGA driven by the 20largest MCNC benchmarks. Results demonstrate that 3-D nFPGAis able to provide a performance gain of 2.6 with a small poweroverhead comparing to the traditional 2-D FPGA architecture.

Index Terms—3-D integration, nanoelectronics, nanotube,nanowire, performance, reconfigurable logic.

I. INTRODUCTION

F IELD-PROGRAMMABLE gate array (FPGA) chipsoffer an attractive solution for significantly loweringthe amortized manufacturing cost per unit and dramaticallyimproving the design productivity through re-use of the samesilicon implementation for a wide range of applications. Moreimportantly, FPGA is programmable and can be reconfiguredfor yield improvement and defect tolerance. These featuresbecome absolutely necessary when CMOS technology scalesdown to nanometer scale because the yield of the fabrication ofcomponents will hardly ever approach 100%.

The major performance and power bottleneck of the FPGAis the programmable interconnects and routing elements insidethe FPGA, which have been found to account for up to 80% ofthe total delay [2] and up to 85% of the total power consump-tion [19] when both local and global interconnects are consid-ered. One promising way to improve FPGA interconnect per-formance is to incorporate 3-D integration [1], [4], [20], whichincreases the number of active layers and optimizes the intercon-nect network vertically. 3-D integrated circuit (IC) technology’s

Manuscript received January 13, 2007; revised June 1, 2007. This paper wasrecommended by Guest Editor C. Lau.

C. Dong and D. Chen are with the Department of Electrical and Computer En-gineering at University of Illinois, Urbana-Champaign, IL 61801 USA (e-mail:[email protected]; [email protected]).

S. Haruehanroengra and W. Wang are with the Department of Electrical andComputer Engineering at Indiana University-Purdue University at Indianapolis,IN 46202 USA (e-mail: [email protected]; [email protected]).

Digital Object Identifier 10.1109/TCSI.2007.907844

main advantage is that it significantly enhances interconnect re-sources. Used correctly, 3-D IC provides improved bandwidthand throughput, as well as reduced wire length. In the best sce-nario, if we ignore the inter-layer vias, the average wire lengthis expected to drop by a factor of [9]. Both wireresistance and capacitance would drop proportionately; that is,power would drop by a factor of and wire (RC)delay would drop by a factor of . Hence, for intercon-nect-dominated architectures such as FPGAs, we expect a sig-nificant reduction in chip delay and energy. However, a disad-vantage of the 3-D IC is its thermal penalty. The 3-D stacks willincrease heat density, leading to degraded performance if nothandled properly.

The application of the novel nanoelectronic materials (nano-materials) and devices to establish FPGAs sheds new lighton building future programmable devices. Carbon nanotubes(CNTs), nanowires, and other molecular electronic deviceshave shown strong promise in the literature. More importantly,some nanomaterials have a significant potential for buildingbetter interconnects. For example, single-wall CNT (SWCNT)bundles can outperform copper interconnect in terms of prop-agation delay for all the local, intermediate, and global wires[22], [31]. They also provide high current-carrying capability(more than 100 times higher than copper) [27] and high thermalconductivity (more than fifteen times higher than copper) [15].Also, nanowire crossbar is considered a promising structurefor memory and programmable elements in FPGA [11]. Thismotivates us to incorporate CNT bundles and nanowire cross-bars into 3-D FPGA. As a result, we can expect a significantimprovement in FPGA logic density, interconnect and powerperformance, and thermal behavior.

Motivated towards integrating the two aforementionedleading technologies, we present a 3-D FPGA structure,namely, 3-D nFPGA, in this paper. The novelty of this 3-DnFPGA lies at the combination of 3-D FPGA architecturedesign and nanotechnology, which will significantly advancefuture large-scale programmable devices. Furthermore, an effi-cient CMOS nanohybrid method is used, so that the advantagesof CMOS devices, nanotube interconnects/vias and nanowirecrossbar programmable elements are utilized.

This paper is organized as follows. Section II introducesrelated work. Section III introduces the advantages of CMOSnanohybrid techniques and motivates the design methodologybehind 3-D nFPGA. Section IV presents the details of 3-DnFPGA architecture. Section V provides interconnect anddevice characterization for 3-D nFPGA and an architectureevaluation CAD flow. Section VI presents a case study of using3-D nFPGA to implement a real circuit design, and Section VII

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2490 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 11, NOVEMBER 2007

provides detailed performance and power results using thelargest twenty MCNC benchmarks. We then draw some con-clusion and also discuss our future work in Section VIII.

II. RELATED WORK

Several CMOS-based 3-D FPGA structures have been pro-posed by stacking together a number of 2-D FPGA bare dies.The architecture in [8] implements intercluster routing in onelayer and clusters [logic blocks or configurable logic blocks(CLBs)] and intracluster routing in another layer. The archi-tecture in [26] spreads look-up tables (LUTs) into different ac-tive layers and routes through 3-D switch boxes. Recently, athree-layer 3-D FPGA is proposed in [20], which is a mono-lithically stacked CMOS-based 3-D FPGA. It follows the 2-DFPGA architecture and efficiently divides it into three layers forconfiguration memory, switching, and logic. The main advan-tage of such approach is that, in principle, it can achieve compa-rable vertical via density and scale at the same rate as the base-line CMOS technology. It shows a 1.7 performance gain onaverage compared to the 2-D FPGA. None of aforementionedworks considers nanomaterials or CMOS nanohybrid systems.

Recently, several 2-D FPGA structures built purely withnanomaterials have been proposed. An array architecture fornanoscale devices was suggested in [10]. This design is anisland style architecture in which clusters of nanoblocks andswitch blocks are interconnected in an array structure. Eachnanoblock is a grid of nanowires that can be configured to im-plement a three-bit input to three-bit output Boolean functionand its complement. There are routing channels existing be-tween the clusters to provide low-latency communication overlonger distances. A programmable logic array (PLA)-basedarchitecture, namely, nanoPLA, was presented in [11]. Thisarchitecture uses crossed sets of parallel semiconductingnanowires. Decoders address each individual nanowire whichis able to program nanowires crossbar array into OR planesby applying a voltage differential across a pair of crossednanowires. Nanowire field-effect transistor (FET) restoringunits are attached at the output of the programmable OR placeto restore the output signals. The restoring unit is able to invertits input so that the NOR plane can be provided. A CMOS-likelogic structure based on nanoscale FETs was proposed in[30]. The fundamental nanowire array consists of metallichorizontal wires and semiconducting vertical wires in bothn-type and p-type. AND-OR-INVERT functions can be achievedby connecting n-type and p-type mosaics through selectivelyconnected programmable switches array. However, this archi-tecture assume both n-type and p-type configurable crossbarFETs are available which is still a challenge.

There are some 2-D CMOS nano-FPGA architectures. Ref-erence [14] uses nanowires of different widths and materialsas interconnects and replaces pass transistor switches withprogrammable molecular switches. The clusters are still im-plemented with CMOS. It is shown that this new architecturecould reduce chip area by up to 70% compared to the traditionalCMOS FPGA architecture (scaled to 22 nm). Reference [24],on the contrary to [14], presents a nanowire-cluster basedFPGA, and the inter routing remains at CMOS scale. It shows

up to 75% area reduction (when ) with com-parable performance to traditional FPGA. In [32], a promisingcell-based architecture called ‘CMOL’ was proposed. It utilizesan interface scheme by using special doped silicon pins imple-mented on surface of substrate to provide the contacts betweennanowires and the CMOS layer. Therefore, logic functions areimplemented by CMOS inverter arrays and nanowire-molecularswitch based OR logics. Signals are routed through nanowiresand selectively configured crosspoints.

A generalized CMOL architecture, named field-pro-grammable nanowire interconnect (FPNI), was proposedin [37]. Different from CMOL’s inverter array architecture,logics of FPNI are implemented with logic gate arrays ( -inputNAND/AND together with buffers and flip-flops) in CMOSlayer, and nanowires are used for routing purpose only. Thisarchitecture allows simpler fabrication comparing with CMOLbecause it requires less alignment accuracy between the CMOSand nanowire layers, and offers greater flexibility for creatingnanodevices. Compared with traditional FPGA design, FPNIsignificantly reduces the chip area, but suffers from lower clockspeed. Note that all these nanoFPGA structures mainly usenanowire crossbars and molecular switches. Researchers alsoattempted to use CNT-based memories (i.e., NRAM [24]) to beembedded into FPGAs to store bit configuration data [33].

It is noted that none of these nanoFPGA works utilizes 3-Dintegration techniques. Only very recently, [12] has proposed a3-D programmable logic structure, purely based on nanowires.Compared with this work, the 3-D nFPGA introduced in thispaper utilizes both CMOS and nanotube/nanowire building ma-terials and takes advantages of both mature CMOS technologyand advanced nanotechnology.

III. CMOS NANOHYBRID TECHNIQUES

Instead of completely replacing the CMOS technology, webelieve the future chips for nanotechnology should be built as ahybrid using both CMOS (can be non-conventional CMOS suchas strained silicon) and nanomaterials (such as CNT bundleinterconnects and nanotube/nanowire crossbar memories), thustaking advantages of both mature CMOS technology and noveladvances in nanotechnology. Therefore, our proposed 3-DnFPGA architecture is based on CMOS nanohybrid techniques.

A. CNT Bundles for Interconnects/Vias

The resistivity of currently used copper (Cu) interconnectsincreases with downscaling dimensions due to electron surfacescattering and grain-boundary scattering. In the meantime, thedemand on current density becomes larger for future IC tech-nology [35]. These requirements motivate intensive studies onnew solutions for nanoscale interconnect materials and struc-tures.

A CNT bundle is typically a bundle of SWCNTs. A SWCNTis a rolled-up seamless cylinder of graphene sheet made of ben-zene-type hexagonal carbon rings [15]. The mean free path ofSWCNT is several micrometers. Within this length, ballistictransport is observed in SWCNT. Thus, its resistance is a con-stant without scattering effects. A rope or bundle of SWCNTsconduct current in parallel and significantly reduce the resis-tance value [21], [22], [31]. Thus, the SWCNT bundle with or

DONG et al.: 3-D nFPGA: RECONFIGURABLE ARCHITECTURE FOR HYBRID DIGITAL CIRCUITS 2491

Fig. 1. SWCNT bundle vias [38].

Fig. 2. Max. temperature rise for Cu and SWCNT bundle vias [31].

without perfect contact can outperform copper interconnect forpropagation delay [22].

In addition, SWCNT bundle vias (Fig. 1) offer high perfor-mance and high thermal conductivity (more than fifteen timeshigher than copper [17]). In nanoscale circuits, vias are prone tomaterial deterioration, such as void formation and subsequentbreakdown, caused by high current densities in small holes andcurrent crowding effects at the edges. SWCNT bundle would bemuch less susceptible to damage compared to metal due to itshigh current-carrying capability (more than 100 times of thatof copper). As shown in Fig. 2 [31], by integrating SWCNTbundle vias with copper interconnects, the temperature rise ofinterconnect layers is much lower. This thermal property ofSWCNT bundle is specifically useful for 3-D ICs to combatthermal penalty. Large bundles of SWCNTs can be used asthermal vias to directly connect to the heat sink and efficientlydissipate the excessive heat [16], [31].

A recent advancement for CNT bundle fabrication is the in-tegration of its fabrication into CMOS fabrication process. InNov. 2006, a CMOS-compatible process was announced by Fu-jitzu, Japan [28], [34], [36]. It is essentially a two-step processconsisting of a catalyst preparation step followed by the actualsynthesis of the nanotube. This CMOS-compatible process willenable the practical applications of CNT bundle-based intercon-nects/vias into CMOS ICs.

B. NRAM and Nanowire Crossbar for Memory/Routing

Recent progress of memory design in nanotechnologyleads to the implementation of CNT memory (NRAM) usingphotolithography. This nonvolatile nanotube random-accessmemory is faster and denser than DRAM. It has much lowerpower consumption than DRAM or flash and has similar speedto SRAM. Meanwhile, it is highly resistive to environmental

Fig. 3. Nanowire crossbar.

forces such as temperature and magnetism. We consider NRAMas a good candidate for block memory design in FPGA [33].

Another radical post-silicon memory structure is basedon nanowire crossbar structure without using transistors. Inthe crossbar structure, the active components are hystereticresistors formed at the points where two nanowire arrays crosseach other. Memory can be configured in the crossbar by pro-gramming these crosspoints. The small size and high densityof these structures make them favorable candidates for futurehigh density memory devices. This crossbar scheme offersinherent defect tolerant capability. Furthermore, the simpletwo-terminal layout of the crossbar structure makes it suitablefor aggressive scaling. As shown in Fig. 3, HP and several otherresearch groups [7] have fabricated and tested crossbar mem-ories using metal nanowires and organic molecular switches.Using nanoimprint lithography, parallel 2-D nanowires of 5-nmwidth and 14-nm pitch have been fabricated [3].

These tight nanowire crossbar arrays can be carved up andcontrolled from the lithographic scale to realize nanoscalememory or programmable elements. Thus, we can use thesecrossbars as both memories and signal routing elements, whichare expected to provide significant advantages comparing totraditional SRAMs and routing structures.

IV. 3-D nFPGA ARCHITECTURE

Using the CMOS nanohybrid approach, we now investigate3-D nFPGA design to provide dramatic density/interconnectimprovement over the baseline 2-D FPGA.

A. Baseline 2-D FPGA

Fig. 4 shows a traditional 2-D FPGA architecture (baseline).It consists of a number of tiles and each tile consists of oneswitch block, two connect blocks and one CLB. Each CLBor cluster (Fig. 5 [5]) contains some local routing structuresto route input signals to several basic logic elements (BLEs)and also connect BLEs together. In this figure, represents thenumber of inputs the CLB has, and represents the numberof BLEs the CLB contains. We use to represent the size of aBLE. Each BLE consists of one -input lookup table ( -LUT)and one flip-flop. A -LUT can implement any logic functionswith up to variables.

The CLBs connect to the routing channels through connec-tion blocks (CB). The global routing structure consists of 2-Dsegmented interconnect channels connected by programmableswitch blocks (SB). Typical designs of CB and SB are shown inFig. 6. Fig. 6(a) shows two different ways of connecting routing


Fig. 4. Schematic of a baseline 2-D FPGA.

Fig. 5. Schematic of a logic cluster or CLB.

Fig. 6. (a) Two designs of CB connections. (b) One design of SB connections.

wires to the CLB: one is through pass transistor and one isthrough multiplexer. Fig. 6(b) shows that wires from four direc-tions (each wire represents one track in the horizontal or verticalrouting channels) are connected through bi-directional tri-statebuffers. Each wire can potentially drive three other wires. Thenumber of routing tracks that a CLB input can connect to is con-trolled by an architectural parameter called (Fig. 5) [5] .

B. 3-D nFPGA

As shown in Fig. 7, the large 2-D footprint of the FPGA is effi-ciently distributed into three layers of 3-D nFPGA. 3-D nFPGAconsists of a 3 1/2-layer structure, which can integrate theCMOS-based logic devices, nanowire-based memory/routingelements, post-silicon block memories and CNT-based viasin three dimensions. 1) Layer 1—The CMOS-based enhancedclusters of BLEs. 2) Crossbar Layer—Integration of CLB local

Fig. 7. (a) 2-D baseline FPGA becomes (b) 3 1/2 layer 3-D nFPGA.

routing, connection blocks, and distributed memory blocksbuilt by crossbar (this layer has no substrate and is consideredas a half layer). 3) Layer 2—CMOS-based enhanced switchblocks and local interconnects. 4) Layer 3— NRAM-basedblock memories and local interconnects [Fig. 7(a) does notshow the block memories of the baseline FPGA]. Layers 1and 2 are bonded face-to-face with the crossbar layer in themiddle. Layers 3 and 2 are bonded in a face-to-back manner.The communications between different layers are all based onCNT bundle via network. The following items summarize theunique features of this architecture:

• a novel combination of logic, crossbar, and switch layerdesigns;

• Layers 1 and 2 are face-to-face for efficient via communi-cation;

• crossbar layer is a novel incorporation of connectionblocks, CLB local routing, and distributed memories;

• dramatic reduction of interconnects and FPGA footprint;• vertical communication and thermal alleviation through

CNT bundles;• combination of both distributed memories and block mem-

ories to satisfy specific memory needs for control-intensiveand data-intensive FPGA applications;

• 3 1/2-layer structure or the bottom 2 1/2-layer structure canbe stacked multiple times on top of one another, enablingmulti-stack 3-D nFPGAs

Layer 1—Reduced Logic Block (RLB): A standard CLB com-prises buffers, local wires, multiplexers (MUXs) and BLEs. Theinputs of a CLB are routed to different BLEs through localrouting elements such as MUXs. If the routing is fully connectedor fully populated, that is, any BLE inputs can be connectedto any CLB inputs, the local routing area is significant (for ex-ample, 65% of a CLB). This motivates us to replace the CMOS-based routing elements with nanowire-molecular crossbars. Byprogramming the molecular switches on/off at the crosspointsof a nanowire array, a CLB input can be routed to any BLE. Weimplement this crossbar in the Crossbar Layer. As a result, theCLB footprint in Layer 1 can be significantly reduced.

As shown in Fig. 8, Layer 1 consists of tightly packed BLEsfrom the original CLBs and the programming and addressingunit (PAU). The PAU is used for addressing the crossbar-basedBLE routing in the Crossbar Layer. One Layer 1 tile (namedRLB) is corresponding to the logic contained in the originalCLB. Note that we use size-4 CLB (each CLB contains four


Fig. 8. Layer 1, crossbar layer, and layer 2.

BLEs) and four-input BLEs in this section simply for illustra-tion purpose. Our architecture can handle any reasonable CLBand BLE sizes for this transformation. Fig. 8 shows four tilesfor Layer 1 as an example.

Layer 2—Reduced Switch Block (RSB): In baseline FPGA,the global routing consists of connection blocks and switchblocks, which together take up a significant amount of thebaseline FPGA footprint. For instance, if CLB size is 10 andBLE size is 4 (popular parameters for commercial FPGAproducts), the global routing area is 57.4%, and the total CLBarea is 42.6% in the baseline FPGA [2]. Global routing area isthus very critical for FPGA footprint reduction for our 3-D chip.We apply two techniques to aggressively reduce the routingarea. First, the majority of connection blocks are moved to theCrossbar Layer because they are multiplexer-based designslike the case in CLB local routing. Second, we move all theprogramming SRAM cells of the switch blocks to the CrossbarLayer as well and implement them by the nanowire crossbarmemories. Therefore, one Layer 2 tile (named RSB) is a switchblock without SRAM cells plus the driving buffers whichconnect to the wire tracks and drive the routing part (MUX in2-D, but replaced with nanowire crossbar in 3-D nFPGA) ofthe connection blocks.

Taking a CLB size and a BLE size with aas an example, the routing

area of one tile can be partitioned as shown in Fig. 9, where47.8% area (SRAM cells area) of switch block can be moveddown and efficiently implemented at the crossbar layer. Onlybuffers driving the routing of the connection block remain in theswitch layer, which takes only 17.5% of the connection blockarea. Combining the global routing area percentage with de-tailed routing area partition, we can draw the conclusion that bybalancing routing resource into switch layer and crossbar layer,a tile footprint which is only 22.4% of the 2-D baseline footprintcan be achieved—a more than 4 circuit area reduction.

Crossbar Layer (Layer 1 1/2)—Hybrid CommunicationBlock (HCB): One Crossbar Layer tile [named hybrid com-munication block (HCB)] consists of one BLE routing block,two connection blocks, SRAMs for one RSB and a distributed

Fig. 9. Global routing area partition.

Fig. 10. Detailed diagrams of BLE routing and PAU.

crossbar memory (Fig. 8). All these functionalities can berealized because the crossbar layer is built by high densitynanowire T/cm , much higher than the correspondingCMOS implementation ( T/cm [35]). The connectionblocks connect to the RSBs using up-vias. They also connectto the BLE routing blocks on the same layer. The BLE routingblocks connect to the BLEs on Layer 1 using the down-vias.

In Fig. 10, we show how BLE routing block works throughan example. BLE routing block receives inputs from adjacentconnection blocks (Fig. 8) and routes them to the correspondingBLEs in Layer 1 using CNT short vias. Note that these same in-puts can be routed to multiple BLEs. In this example, the inputsignal A from CB1 is routed to BLEs along dot line throughdown-vias (we use vias to represent that it is a group of vias toconnect to individual inputs). The black dots at crosspoints in-dicate the molecular switches which have been programmed asON state. The outputs of BLEs indicated by dash line can eitherfeed back to the crossbar to connect to the inputs of other BLEsor output to adjacent connection blocks. In order to apply a pro-gramming voltage to an individual nanowire in the HCB, thePAU is required, consisting of address controllers and voltageterminals. This unit is included in Layer 1 because these tran-sistors can be efficiently implemented using CMOS. The darkblue bar in the left side of Fig. 10 represents voltage sources forprogramming, which are about two times higher than the op-eration voltage. To control wires, p-type transistorsare required. These p-type transistors can address each nanowireand set the molecular switch at a crosspoint as either ON or OFFstate. Crossbar layer is an efficient interface between Layers 1


and 2. The CNT short vias have metal contacts, which can es-tablish reliable connection to the local interconnects of Layers1 and 2.

Layer 3—Block Memory Layer: We use NRAM in Layer 3 asblock memories for our architecture. They are able to store largeamount of data suitable for data-intensive applications such asDSP and multimedia applications. In order to connect Layer 3(facing down) with Layer 2, a face-to-back 3-D IC bonding isapplied and special vias called through-vias are used to makethe connections [Fig. 7(b)]. Because the through-vias penetratethe substrate of Layer 2, the density of these vias is ten timessparser than that of CNT short vias. This density is sufficient forbuses and communication channels to serve the block memory.In order to obtain better via performance and thermal effect, thethrough-vias are made with CNT bundles.

Hybrid Horizontal Interconnects: In the proposed structure,local horizontal interconnects are required inside Layers 1, 2,and 3. We prefer CNT over copper as interconnect. However,vertical CNT bundles are difficult to connect to horizontal CNTbundles. To overcome this difficulty, copper contacts and shortcopper horizontal interconnects can be used to set up the con-nection between vertical and horizontal CNT bundles. This hy-brid approach considers both fabrication capability and perfor-mance optimization. We apply the mixture of copper and CNTinterconnects for horizontal connections. For example, in Layer2, there can be short interconnects (e.g., single lines or doublelines) that connect adjacent or neighboring RSBs and long in-terconnects (e.g., HEX lines) that connect far away RSBs. Thismixture of interconnects of different lengths is a common prac-tice in modern FPGAs. We can use copper for short intercon-nects and CNT bundles for HEX lines (or similar longer lines)to reduce interconnect delay. Note that our horizontal intercon-nect is much shorter than that in the baseline FPGA because ofthe dramatic footprint reduction in 3-D nFPGA.

3-D Stacks: The 3 1/2-layer architecture or the bottom 21/2-layer architecture (without the NRAM layer) can be stacked,enabling multi-stack 3-D nFPGAs. We now show an exampleusing 2 1/2-layer stacking, which provides an excellent stackingarchitecture. The 2 1/2-layer architecture is ideal for control-in-tensive applications. The distributed memories available on thecrossbar layer can provide fine-grained register-file capabilities.As shown in Fig. 11, we put two RSB layers back-to-back. TheRSBs on the two layers communicate using CNT through-vias,which enable short and high-speed connections. In 2-D FPGA,connecting far away cells can be very expensive in terms ofdelay and power. In 3-D nFPGA, by utilizing the vertical di-mension, the RSBs on the bottom stack not only can connect toother RSBs on the same layer but also can directly connect tothose on the layer above. This provides much more efficient in-terconnecting network and significant performance and powerimprovements.

The 3 1/2-layer architecture can also be stacked. Note, for 31/2, the RSBs of the two stacks can not be stacked directly. In-stead, it will require longer through-vias penetrating the blockmemory layer. When the stack number increases, the perfor-mance difference between multi-2 1/2-stack and multi-3 1/2-stack diminishes because multi-2 1/2-stack will incur longerthrough-vias as well, starting from the third stack.

Fig. 11. 2-stack (each stack is 2 1/2 layers) 3-D nFPGA.

C. Thermal Vias and Defect Tolerance

The additional features of 3-D nFPGA include its emphasison thermal optimization and defect tolerance. A major concernof the 3-D IC is its thermal penalty. The 3-D stacks will in-crease heat density, leading to degraded performance. It hasbeen demonstrated in [9] that doubling the heat density withoutany improvement in cooling capacity will lead to more than 30%degradation in performance. CNT bundle short vias in our struc-ture are thermal-efficient. In addition, we use large CNT bundlesas thermal vias [Fig. 7(b) and Fig. 11]. The thermal conductivityof CNT bundles can be up to 5800 W/mK [15]. In addition, thisconduction is in the direction along the length of nanotubes be-cause thermal conductivity in CNT bundles is anisotropic [15].Therefore, CNT bundle vias will serve as more effective heatconductors compared to copper vias and can reduce the tem-perature gradient dramatically. As a result, the whole chip cancool down quickly. We can further optimize the size and thedensity of these thermal vias taking into account of other archi-tectural parameters such as stack number, BLE size, short viaand through-via density, and so forth.

The proposed 3-D nFPGA has excellent fault tolerance ca-pabilities. The BLE and switching layers are based on CMOStechnology, which offers very low defect rates. However, nano-electronic circuits, such as the crossbar structure, always have asmall percentage of defective components due to the statisticalnature of the self-assembly fabrication process [10], [11]. Errorsand faults in a system could be either permanent (hard errors) ortransient (soft errors). Reconfiguration, done either statisticallyor dynamically, is an effective solution to fix the hard errors,which is an intrinsic advantage of FPGA chips. For static re-configuration, off-line self-test and self-diagnosis will be suffi-cient. To support dynamic reconfiguration, the design must haveon-line self-test and diagnosis capabilities to detect and iden-tify failures when a system is operating. We can use some ex-isting techniques to support these crucial features, such as prob-abilistic model checking and self-checking circuit design [14].In addition, we can add redundancy into our Crossbar Layerwith redundant rows and columns [30]. We will also have redun-dant vias and redundant molecular switches. The right amountof redundancy has to be modeled and studied.


Fig. 12. 3-D nFPGA evaluation framework.

V. 3-D nFPGA CHARACTERIZATION AND EVALUATION

In this study, we evaluate performance and power of a 3-DnFPGA architecture compared to the baseline 2-D FPGAarchitecture. In order to have accurate evaluation, we need tohave detailed delay and power characterization for both inter-connects and devices. The interconnect characterization will befor copper wires used in the baseline FPGA and CNT-bundlewires used in the 3-D nFPGA. The device characterizationis for CMOS-based MUXs used in the baseline case andnanowire-based crossbars used in the 3-D nFPGA case. Wealso need a CAD flow that is able to use a set of well acceptedbenchmarks and go through various design stages to report thefinal delay after circuit layout. The CAD flow for baseline 2-DFPGAs is well studied [5]. We will adopt this flow and make itworkable for our 3-D nFPGA architecture. In the following, wewill first present our CAD flow and then introduce our delayand power characterization methods and related results.

A. CAD Flow

We use a timing-driven CAD flow shown in Fig. 12. Eachbenchmark circuit goes through technology independentlogic optimization using SIS [29] and is technology-mappedto -LUTs using DAOmap [6], which is a popular perfor-mance-driven mapper working on area minimization as well.The mapped netlist then feeds into T-VPACK and VPR-LP,which perform timing-driven packing (i.e., clustering LUTsinto the CLBs), placement and routing [5] and further generateBC-netlist for power simulator fpgaEva_LP2 [19]. Afterwards,we can obtain the critical path delay of the design and powerconsumption. This CAD flow is flexible. We can choose variousparameters for LUT size , CLB size , routing architectures,and interconnect buffer sizes, etc. In our study, we set ,

and route channel width 100. In FPGAs, intercon-nects are segmented and driven by buffers. It is shown that a

TABLE IINTERCONNECT DELAY CHARACTERIZATION

mixture of interconnects with different lengths provide betterperformance [5]. In our experiments, we will use a mixtureof length-4 and length-8 wire segments (wires crossing eitherfour CLBs or eight CLBs in the baseline FPGA) of equalamount to route the signals, which is reported as one of the bestcombinations [5]. All these parameters can be supplied throughthe architecture specification file.

B. Interconnect Characterization

The interconnect length scaling due to 3-D stacking is themain reason for system performance and system dynamic powerenhancement. To better understand the impact of 3-D, we esti-mate the delay of length-4 and length-8 wire segments for bothbaseline FPGA and 3-D nFPGA using HSPICE simulation. Toobtain the actual lengths of these interconnects, we first needto estimate the tile area based on the area model presented inSection IV. We consider the baseline and the 3-D cases sepa-rately.

When we estimate the lengths of wire segments for the base-line architecture, we need to consider both the CLB area and therouting area. Wire segmentation crosses a baseline tile with anarea of 1561.5 m . Therefore, length-1 interconnect for base-line would have a physical dimension of 39.52 m.

Next, we will examine the wire length for 3-D nFPGA.Because 3-D nFPGA distributes the switch blocks, connectionblocks and CLBs into three different layers, the situation isdramatically changed. A routing wire segment only spansRSBs now (Fig. 8). RSB area is the area of baseline switchblock excluding SRAM cells (Section IV). The RSB area isestimated as 350.25 m . Therefore, length-1 interconnect for3-D would have a dimension of 18.71 m, which represents a52.64% length reduction compared to the baseline case. Table Ishows detailed comparison data of the wire segments for boththe baseline and the 3-D nFPGA.

In Table I, and represent wire length, wire resis-tance, wire capacitance, and wire delay respectively. The cal-culation of and values of copper is well known. CNTscan be considered as quantum wires. Thus, CNT bundles willneed to consider additional quantum resistance, quantum ca-pacitance and kinetic inductance [21], [23], [27], [28], [31].We will briefly mention the models we use to derive the re-sistance and capacitance of CNT bundles. We assume that aCNT-bundle interconnect is composed of hexagonally packed


identical metallic single-walled CNTs [31]. The CNT-bundleresistance is given by

(1)

where is the resistance of a single CNT wire and isthe total number of CNTs forming the bundle. We consider theintrinsic capacitance and quantum capacitance of CNT bundles.The effective capacitance of a CNT bundle is a seriescombination of quantum and intrinsic capacitance given by

(2)

where and are the intrinsic capacitance and the quantumcapacitance of a CNT bundle.

Using these parameters, RC wire delay is then obtainedthrough HSPICE. We can observe that CNT bundle wireprovides the best performance among the three cases we ex-amine—copper wire used in baseline 2-D FPGA, copper wireused in 3-D nFPGA (a fictitious case to show how copperinterconnects in 3-D nFPGA can help in terms of wire lengthand delay reduction), and CNT bundle wire used in 3-D nFPGA(the architecture proposed in this work). Note that this sectiononly models interconnect delay in the routing architecture. Thenext section will model circuit path delay, including vias andnanowire-based devices. The capacitance of different lengthsegmentation is also used for power estimation.

C. RC-Equivalent Circuits Extraction for Device Delay

Replacing the CMOS-based MUXs with nanowire crossbarsnot only significantly reduces the footprint of the chip but alsoenhances circuit performance. In our experiment, we set routingchannel width for all the benchmarks. This is oftenused in academia to imitate the real FPGA routing architecturesince modern FPGA chips usually provide sufficient routing re-sources, and a single FPGA device will have a fixed channelwidth. We set , which is also commonly used and pro-vides connections between the CLB input and half of the routingtracks in the channel. We set the number of inputs as 22 for theCLB [2]. For baseline architecture, this implies that thirty-two50:1 MUXs (the MUXs marked with in Fig. 5) will berequired in the connection block. In addition, another ten 32:1local routing MUXs (22 CLB inputs plus 10 feedback wiresfrom the 10 BLE outputs—the MUXs marked with inFig. 5) are also necessary to route the cluster inputs and feed-back wires to individual BLEs.

As explained in Section IV, MUX can be easily and effi-ciently implemented by nanowire crossbar. A 50:1 MUX can beconstructed as 50 vertical wires crossed by one horizontal wire.A second MUX is simply one additional horizontal wire. A 5032 crossbar array can serve the same functionality as the connec-tion block in the baseline FPGA. These crossbars are especiallysuitable for defect tolerant designs. Considering the defects; re-dundant wires can be used, requiring a larger crossbar. Eventhis larger crossbar is efficient due to the high-density property

Fig. 13. Extracted equivalent circuits of 3-D nFPGA.

of the nanowires crossbar. For example, a square crossbar arraywith 50 50 nanowires only requires a m m di-mensional array at 32-nm technology.

The CAD flow shown in Fig. 12 is ideal for the baselineFPGA. To make it work for the 3-D nFPGA, we need to buildvarious circuit models to capture the specific characteristics of3-D nFPGA architecture. In the architecture specification file ofVPR, we need to supply delay values for various combinationalcircuit paths to enable accurate timing analysis. For example,in Fig. 5, there are paths , , and , etc.We need to have corresponding equivalent circuits to implementthese paths in 3-D nFPGA. The difference now is that part ofthe path may go through a CNT bundle via or a nanodevice andmay also go vertically instead of horizontally compared to thebaseline case. We extract these different paths for 3-D nFPGAand perform HSPICE simulation to compute their delays respec-tively.

As shown in Fig. 5, the wire track to CLB input pathof baseline FPGA consists of a buffer and a MUX in a connec-tion block. For 3-D nFPGA, the corresponding path consists ofa CNT via between Switch Layer and Crossbar Layer, nanowiresegments, and a programmable switch. This path is representedby resistors and capacitors in an equivalent circuit, illustrated inFig. 13. Another example in Fig. 13 shows the equivalent cir-cuit of local feedback path in nFPGA. It can be mod-eled as up-via to BLE routing box (Fig. 10), nanowire crossbarand down-via to destination BLE. Other paths are illustrated inFig. 13 as well.

In our study, NiSi nanowire and molecular programmableswitches are used. The cross section of nanowire is assumed assquare; the distance between adjacent nanowires is assumed tobe equal to the wire width. The insulation material around thenanowires is set to have a dielectric constant of 3.9. Applying


TABLE IIPERFORMANCE COMPARISON OF BASELINE AND 3-D nFPGA

the above configurations, we have the following equations fornanowire:

(3)

(4)

where is the nanowire length, is the thickness of the in-sulator. Resistivity is obtained based on the work of[13]. A unit resistance m and a unit capacitance

aF m is derived. Programmable switch has an ONresistance plus a contact resistance (to nanowire) below 1 k .CNT vias are extracted by using the same models of CNT inter-connects assuming an interconnect length of 0.02 m. Basedon these parameters, the equivalent circuits are simulated inHSPICE. The performance comparisons are listed in Table II: a44.79% performance enhancement is achieved on average. The

delay in baseline FPGA is better than that in 3-DnFPGA. The reason is as follows. models the delayfrom BLE output to the output of CLB. It consists of one tri-statebuffer (size 10 ) to drive output wires in the routing channel.Besides the output buffer, 3-D nFPGA has an additional viadelay which occurs during the signal propagation from the BLElayer to the switch layer. This contributes extra delay for the 3-DnFPGA case.

D. Macro Power Models

The gate-level FPGA power estimator fpgaEva_LP2 [19] re-quires both switch level models and macro models for powerestimation. The switch level model uses extracted capacitanceto model the power consumed during signal transition. A macromodel predefines a circuit component using HSPICE simula-tion. Both dynamic and static power of size-4 LUT and var-ious sized buffers based on BSIM 32-nm model were studied.Randomly generated input vectors with equal occurrence prob-ability are used to obtain the average power consumption peraccess to the LUT. In this paper, only size-4 LUT was studied.However, it is easy to extend to other LUT architectures bylisting power data into user defined library of fpgaEva_LP2.

To correctly model the crossbar based BLE routing; ananowire crossbar array was also simulated with HSPICE.Shown in Fig. 9, comparing to MUX based 2-D baselinedesign, CLB input capacitance of nFPGA now is replaced withcapacitance of electrically connected nanowires (A to inFig. 10) plus crosspoint switch capacitances and necessaryvia capacitances. 2-D intra local feedback capacitance whichwas molded as Length-1 wire segment capacitance plus bufferinput capacitance is replaced by nanowire capacitance and via

TABLE IIICAPACITANCE EXTRACTED FROM VPR-LP (UNIT: fF)

Fig. 14. Equivalent circuit for nanowire crossbar leakage power simulation.

capacitance in 3-D as well. Consider and ,Table III lists some of the extracted capacitance values ofdifferent architectures. Leakage power of crossbar array iscaptured by modeling each crosspoint as a diode with an ON orOFF resistance. The equivalent circuit is shown in Fig. 14 [32].For and architecture, crossbar of one tile hasa leakage power 1.53E-06 W.

VI. CASE STUDY

In this section, we will present a detailed case study takinga 4-bit carry-ripple adder as an example. The 3-D nFPGA im-plementation of this design will be discussed. First, the graph-ical visualization of the 4-bit adder implementation in the base-line FPGA is illustrated in Fig. 15, which is captured throughVPR’s graphical interface. This circuit consists of eight 3-LUTspacked into three size-4 CLBs. To make the case simple, therouting contains a mixture of length-1 and length-2 wires andthe routing channel width is 6. For clarity, only one input netand one output net are highlighted.

The corresponding routing of 3-D nFPGA with the samelogic, I/O pads positions, and wire segments is shown inFig. 16. The net driven by is colored red in Fig. 16. Input

from input pad connects to wire segment in the routingchannel via connection block 1 and two vertical interconnects.Programmable switches in connection block allow to beconnected with one or more wire segments incident to the RSB.In the RSB, net is routed to two different tiles for sum andcarry calculation which are marked 2 3 and 2 4. Paths 35 and 4 6 indicate the two BLE input routings. As explainedbefore, the crossbar array in BLE routing box is responsible forrouting signals to destination BLEs. In this particular example,the input comes from the input pad and travels up and downbetween different layers. In general, the inputs of a tile are mostlikely coming from other tiles through routing channels.

One output net Cout is also illustrated in Fig. 16 in blue color.The output of BLE is connected to BLE routing through up-via


Fig. 15. Placement and routing of a 4-bit adder.

Fig. 16. 4-bit adder 3-D nFPGA implementation.

(path 7 8) and further propagates to output pad through an ad-jacent connection block. Please note that in this simple adder ex-ample, the output shown here is routed to output pad. However,in other applications, the output of BLE can be routed flexiblythrough local routing to other BLE’s input or through routingtrack to other clusters.

VII. EXPERIMENTAL RESULTS

In this section, we quantify the overall performance improve-ment of the 3-D nFPGA over the baseline counterpart. The per-formance improvement is achieved from a combination of 3-Darchitecture, CNT bundle interconnects, and nanowire- basedcrossbar array. The experiment is based on 32-nm technologyplatform. Twenty largest MCNC benchmarks are mapped andfit to both baseline and 3-D nFPGA using the CAD flow and thedetailed delay characterization data presented in Section V.

Fig. 17 shows the view graph of different critical path de-lays for each benchmark collected for three different architec-tures—the baseline FPGA, 3-D nFPGA with copper intercon-

Fig. 17. Critical path delay comparison for three architectures.

TABLE IVCRITICAL PATH DELAY AND COMPARISON

nect for routing (a fictitious case to show how copper inter-connects for 3-D nFPGA perform in terms of delay), and real3-D nFPGA. Table IV shows the detailed delay values for thesame three architectures and also shows the comparison results.On average, 3-D nFPGA with copper interconnects provides a2.05 performance gain (in terms of Fmax) comparing to thebaseline, and real 3-D nFPGA provides a 2.65 gain comparingto the baseline. We would like to stress that the only differ-ence between 3-D nFPGA with copper interconnects and thereal 3-D nFPGA is that real 3-D nFPGA uses CNT bundles forthe routing interconnects and vias. Overall, we observe that, byusing nanowire-based crossbar to shrink the MUX area and by


Fig. 18. Power consumption comparison for three architectures.

TABLE VPOWER CONSUMPTION AND COMPARISON

3-D stacking, the performance gain of 3-D nFPGA is very sig-nificant. On top of that, CNT bundle wires can offer an addi-tional 0.6 for overall performance improvement.

Power consumptions of different architectures are shown inFig. 18. Table V lists and compares the detailed power consump-tion. At 32-nm node, the static power is dominant and both 3-DnFPGA designs have slightly higher total power consumptiondue to larger static power from the crossbar array. Results inTable VI show that with a smaller footprint, the dynamic powerof nFPGA is reduced because of shorter wire length. However,this reduction margin is reduced by a relatively larger dynamicpower from the larger CLB input and BLE output capacitancewhich is introduced by crossbar array (Table III). Comparedwith 3-D nFPGA with copper interconnects, 3-D nFPGA withCNT bundle interconnects can provide better performance butconsume 17.5% more dynamic power mainly because of highcapacitance values of CNT bundles.

We carry out a comparison study between 3-D nFPGA andFPNI [37]. FPNI is a 2-D hybrid FPGA architecture. We believewe can have a fair comparison between FPNI and 3-D nFPGA

TABLE VIDYNAMIC POWER REDUCTION OF nFPGA ARCHITECTURE

because both works offer experimental results using the same setof benchmarks, comparing to the baseline 2-D FPGAs (30-nmCMOS-based FPGA for FPNI and 32-nm CMOS-based FPGAfor 3-D nFPGA). 3-D nFPGA is 2.65 faster than the baselinearchitecture, and FPNI is 30% slower than the baseline. Thisindicates that nFPGA can out perform FPNI by 3.8 in termsof execution frequency. In terms of area, FPNI could achieve a7.5 footprint reduction, and nFPGA on the other hand has a4.5 reduction. The main reason behind this is that FPNI re-places all the routing elements with nanowire crossbars, whichsignificantly reduces the routing area. However, large crossbararrays will degrade the system performance as well. FPNI alsoconsiders power consumption, but it only reports the dynamicpower consumed by nanowire arrays. The switching activity isassumed to be 0.1 for simplicity. There is no consideration ofclock power and glitch power.1 In addition, the clock frequencyconsidered in FPNI is 3.8 slower than 3-D nFPGA. After nor-malization with all above factors, 3-D nFPGA consumes aboutthe same amount of dynamic power compared to FPNI on av-erage. However, we believe the static power of 3-D nFPGA canbe much less compared to FPNI because FPNI uses a largeamount of crossbar arrays, which introduce a large amount ofleakage power due to leaky crosspoints.

VIII. CONCLUSION AND FUTURE WORK

In this paper, we introduced a novel 3-D nFPGA architecturethat utilizes 3-D integration techniques and new nanoscale mate-rials. The combination of these two leading technologies showsa great potential for innovation and technology breakthrough.The proposed architecture is based on CMOS nanohybrid tech-niques that incorporate nanomaterials such as CNT bundles andnanowire crossbars into CMOS fabrication process. This archi-tecture provides a practical platform that utilizes the advantagesof both CMOS technology and nanotechnology.

Using a customized design automation flow, we evaluatedthe performance and power of 3-D nFPGA with the largest 20MCNC benchmarks (the Toronto 20 benchmark set). The eval-uation result demonstrates that the proposed 3-D nFPGA is ableto provide a 2.65 Fmax advantage over the traditional CMOSbaseline 2-D FPGAs with a small power overhead.

These first results of 3-D nFPGA are very encouraging andfurther exploration of the 3-D nFPGA is our next goal. The cur-rent area and delay analysis is for one stack of 3-D nFPGA, andwill be extended to multi-stack structures in the future, thus re-quiring an efficient circuit partitioning tool honoring inter-stackvia density constraints. Detailed thermal analysis also needs tobe carried out so thermal via density can be determined. In addi-tion, the defect models of CNT bundles and nanowires crossbars

1It is reported that clock power can take 20% of the total power, and glitchpower can be 33% of the dynamic power on average in FPGA circuits [18], [19].


will be derived, which can be used to analyze the defect toler-ance capability of 3-D nFPGA. We will also pursue the fabrica-tion and integration of 3-D nFPGA sample chips to verify theperformance analysis results and demonstrate the viability of theproposed architecture.

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Chen Dong received the B.S. degree in electricalengineering from Xi’an Jiaotong University, Xi’an,China, and the M.S. degree in electrical and com-puter engineering from Indiana University-PurdueUniversity Indianapolis, Indianapolis, IN, in 2004and 2006, respectively. Since 2006, he has beenworking toward the Ph.D. degree in electrical andcomputer engineering at the University of IllinoisUrbana-Champaign.

His research interests lie in nanocircuit design, re-configurable high-performance and low-power com-

puting.


Deming Chen received the B.S. degree in computerscience from University of Pittsburgh, PA, in 1995and worked for several years before he joined thePh.D. program of UCLA in 1999. During his Ph.D.,he worked as a software engineer at Aplus DesignTechnologies, Inc (now part of Magma DesignAutomation, Inc.) for more than a year. He joinedthe ECE department of UIUC as a faculty member in2005. He has been actively publishing in high-leveland logic synthesis, low power design, and FPGAdesign and synthesis in various leading CAD con-

ferences and journals. Some of his FPGA research results are state-of-the-artsynthesis algorithms, such as DAOmap, PLAmap, SMAC, GlitchMap, andDDBDD. Some of his research ideas have already been incorporated incommercial software (e.g., Altera and Magma). His current research interestsinclude FPGA design with nanotechnology, FPGA synthesis, behavioraland logic synthesis, and microprocessor architecture and SoC design underprocess variation. He is a technical committee member for FPGA’06-07,ASPDAC’07-08, ISCAS’07, and ICCD’07. He is a session chair for ICCD’05and ASPDAC’07.

Sansiri Haruehanroengra received the B.Eng.degree in electrical engineering (with honors) fromKing Mongkut’s Institute of Technology NorthBangkok, Bangkok, Thailand, and the M.S. degreein electrical and computer engineering from IndianaUniversity-Purdue University, Indianapolis, in 2004and 2007, respectively. He is currently workingtoward the Ph.D. degree at Purdue University.

His research interests include design, modeling,simulation and synthesis of novel nanoelectronicdevices and carbon nanotubes for nanoelectronic

applications as well as 3-D integration for high-performance integrated circuits.

Wei Wang received the Ph.D. degree in electrical and computer engineeringdegree from Concordia University, Montreal, QC, Canada, in 2002.

From 2000 to 2002, he served as an ASIC and FPGA Design engineer atEMS Technologies, Montreal, QC, Canada. From 2002 to 2004, he was a Fac-ulty Member in the Department of Electrical and Computer Engineering, theUniversity of Western Ontario, London, ON, Canada. From 2004, he joined theDepartment of Electrical and Computer Engineering, Indiana University-PurdueUniversity, Indianapolis, IN. His main research interests are VLSI, nanoelec-tronics, digital signal processing, cryptography, digital design, ASIC, and FPGAdesign, and computer arithmetic. He has over 60 journal and conference publi-cations in these areas.

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