Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 11 Reduced Instruction Set Computing

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Chapter 11Chapter 11Reduced Instruction Set Reduced Instruction Set

ComputingComputing


Chapter OutlineChapter Outline

• RISC RationaleRISC Rationale

• Instruction SetsInstruction Sets

• Instruction PipelinesInstruction Pipelines

• Register WindowsRegister Windows

• Instruction Pipeline ConflictsInstruction Pipeline Conflicts

• RISC vs. CISCRISC vs. CISC

• Itanium MicroprocessorItanium Microprocessor


Speeding Up Typical CodeSpeeding Up Typical Code

• 100% of instructions @ 20 ns100% of instructions @ 20 ns




• 98% of instructions @ 18 ns and 2% of 98% of instructions @ 18 ns and 2% of instructions at 3 * 18 nsinstructions at 3 * 18 ns





• 100%(20c) P. 98%(18c) + 2% (54c)100%(20c) P. 98%(18c) + 2% (54c)





• 100%(20c) P. 98%(18c) + 2% (54c)100%(20c) P. 98%(18c) + 2% (54c)

• 20c vs. 17.64c + 1.08c20c vs. 17.64c + 1.08c





• 100%(20c) P. 98%(18c) + 2% (54c)100%(20c) P. 98%(18c) + 2% (54c)

• 20c vs. 17.64c + 1.08c20c vs. 17.64c + 1.08c

• 20 20 18.72 18.72


RISC CharacteristicsRISC Characteristics

• Fixed-length instructionsFixed-length instructions




• Limited loading and storing instructionsLimited loading and storing instructions





• Fewer addressing modesFewer addressing modes






• Instruction pipelineInstruction pipeline






• Instruction pipelineInstruction pipeline

• Large number of registersLarge number of registers



• Hardwired control unitHardwired control unit




• Delayed loads and branchesDelayed loads and branches





• Speculative execution of instructionsSpeculative execution of instructions






• Optimizing compilersOptimizing compilers






• Optimizing compilersOptimizing compilers

• Separate instruction and data streamsSeparate instruction and data streams


RISC Instruction SetsRISC Instruction Sets

• Fewer instructionsFewer instructions




• Executed in one clock cycleExecuted in one clock cycle




• Executed in one clock cycleExecuted in one clock cycle

• Orthogonal, but not too orthogonalOrthogonal, but not too orthogonal– A OR B = NOT((NOT A) AND (NOT B))A OR B = NOT((NOT A) AND (NOT B))– A XOR B = (A AND (NOT B)) OR ((NOT A) A XOR B = (A AND (NOT B)) OR ((NOT A)

AND B)AND B)


MIPS 4000 Instruction TypesMIPS 4000 Instruction Types


SPARC Instruction FormatsSPARC Instruction Formats


Instruction PipelinesInstruction Pipelines












Instruction Pipeline Instruction Pipeline AdvantagesAdvantages

• Reduced hardwareReduced hardware

• Reduced clock periodReduced clock period

• Reduced complexity of memory Reduced complexity of memory interfaceinterface


Pipeline Clock RatePipeline Clock Rate

• Limited by slowest stageLimited by slowest stage

• Speedup:Speedup:

• Example: Example:


Register WindowingRegister Windowing

• Global RegistersGlobal Registers

• Windowed RegistersWindowed Registers

• Window Data RegisterWindow Data Register

• Window Pointer RegisterWindow Pointer Register










Register RenamingRegister Renaming

• Arbitrary registers instead of fixed Arbitrary registers instead of fixed windowswindows

• More flexible, but harder to controlMore flexible, but harder to control


Instruction Pipeline ConflictsInstruction Pipeline Conflicts

• Data conflictsData conflicts

• Branch conflictsBranch conflicts


Data ConflictsData Conflicts


Data ConflictsData Conflicts


No-op InsertionNo-op Insertion




Instruction ReorderingInstruction Reordering





• Not always possibleNot always possible


Stall InsertionStall Insertion


Stall InsertionStall Insertion


Data ForwardingData Forwarding






Branch ConflictsBranch Conflicts


Branch ConflictsBranch Conflicts










Conditional BranchesConditional Branches





• Ignoring the data conflict:Ignoring the data conflict:







• Not always possible to reorder Not always possible to reorder instructions - sometimes must resort to instructions - sometimes must resort to no-op insertionno-op insertion


AnnullingAnnulling


AnnullingAnnulling


Branch PredictionBranch Prediction


RISC AdvantagesRISC Advantages

• Simpler control unitsSimpler control units




• Can run at higher clock frequenciesCan run at higher clock frequencies





• More chip space for registersMore chip space for registers






• Easier to incorporate parallelismEasier to incorporate parallelism






• Easier to incorporate parallelismEasier to incorporate parallelism

• Simpler compilersSimpler compilers


CISC AdvantagesCISC Advantages

• Complexity doesnComplexity doesn’’t always increase t always increase costcost

• Can incorporate previous designsCan incorporate previous designs

• Backward compatibilityBackward compatibility


Itanium MicroprocessorItanium Microprocessor


Itanium MicroprocessorItanium Microprocessor

• IA-64 ISAIA-64 ISA

• Explicitly Parallel Instruction ComputingExplicitly Parallel Instruction Computing

• PredicationPredication

• Speculative ExecutionSpeculative Execution


PredicationPredication


PredicationPredication


Speculative ExecutionSpeculative Execution


Speculative ExecutionSpeculative Execution


SummarySummary

• RISC RationaleRISC Rationale

• Instruction SetsInstruction Sets

• Instruction PipelinesInstruction Pipelines

• Register WindowsRegister Windows

• Instruction Pipeline ConflictsInstruction Pipeline Conflicts

• RISC vs. CISCRISC vs. CISC

• Itanium MicroprocessorItanium Microprocessor

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 11 Reduced Instruction Set Computing