Implication Graphs and Logic Testing

3/30/05 Agrawal: Implication Graphs 1

Implication Graphs and Logic Testing

Vishwani D. AgrawalJames J. Danaher Professor

Dept. of ECE, Auburn UniversityAuburn, AL 36849

[email protected]/~vagrawal

Joint research with: M. L. Bushnell, Rutgers University, Piscataway, NJ K. K. Dave, ATI Research, Yardley, PA


Implication Graph

An implication graph (IG) represents the implication relations between pairs of Boolean variables.

a

a b

b an implication

contrapositiveimplication


Implication Graph of a Logic Gate

ab

c c = ab

Boolean false function: ab c = 0

ac + bc + abc = 0

•Chakradhar et al. -- IEEE-D&T, 1990

a b c

cba


Global Implications and Transitive Closure

a

bc

a b c

cba

Transitive closure edge

c ≡ 0


Transitive Closure Transitive closure (TC) of a directed graph

contains the same set of nodes as the original graph.

If there is a directed path from node a to b, then the transitive closure contains an edge from a to b.

A graph

b

cd

a b

cd

a

A Graph Transitive Closure

a b c d a 0 1 0 0 b 0 0 1 0 c 0 0 0 1 d 0 0 0 0

a b c d a 0 1 1 1 b 0 0 1 1 c 0 0 0 1 d 0 0 0 0


Transitive Closure: Warshall’s Algorithm procedure Warshall (var A : array[1…n, 1…n] of boolean;

C : array[1…n, 1…n] of boolean); { Warshall makes A the transitive closure of C } var

i, j, k : integer; begin

for i := 1 to n do for j := 1 to n do

A[i, j] := C[i, j];

for k := 1 to n do O(n3) for i := 1 to n do

for j := 1 to n do if A[i, j] = false then

A[i, j] := A[i, k] and A[k, j] end; { Warshall }

S. Warshall, “A Theorem on Boolean Matrices,” J. ACM, vol. 9, no. 1, pp. 11-12, 1962.A. V. Aho, J. E. Hopcroft and J. D. Ullman, Data Structures and Algorithms, Reading,Massachusetts: Addison-Wesley, 1983, p. 213.


Transitive Closure: Update Algorithm

Start constructing transitive closure (TC) by placing all nodes and no edges. This edge-less graph is its own TC.

Add edges to TC in any arbitrary order For each edge i → j find

P : set of parent nodes of i C : set of child nodes of j

Add edges {P, i } → {C, j }K. Dave, “Using Contrapositive Rule to Enhance the Implication Graphs of LogicCircuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, New Jersey,May 2004.


Update Algorithm

i

j

p2p1

c1

{P, i }

{C, j }

Edges beforei→ j isadded

Edges afteri→ j isadded


Update Algorithm Example

b

cd

a b

cd

a

b

cd

ab

cd

ab

cd

a

b

cd

a

A directed graph

Transitive closure


Logic Testing: Stuck-at Fault A type of fault, which causes a line to hold a

constant logic value, irrespective of change of state at previous stages.

There are two types of stuck-at-faults: Stuck-at-1 Stuck-at-0

Detection of a fault requires the fault to be activated and its effect observed at a primary output (PO).

Fault a s-a-1 is detectable, if following conditions are simultaneously satisfied:

a = 0 fault is activated Oa = 1 “observability” is true


Observability Variables

Observability variable of a signal represents whether or not that signal is observable at a PO. It can be true or false.

OcOa + bOa + OcbOa = 0

OCb Oa = 0

a

bc

Ob

Oa Oc= 1

(PO) b

Oa

Oc

Agrawal, Bushnell and Lin, “Redundancy Identification usingTransitive Closure,” Proc. Asian Test Symp., 1996, pp. 5-9.


Redundant Faults A fault that has no test is called an untestable fault. Any untestable fault in a combinational circuit is a

redundant fault because it does not cause any change in the input/output logic function of the circuit.

Identification of redundant faults is useful because they can be removed

from testing consideration, or from hardware

Fault a stuck-at-1 is redundant if either a ≡ 1 no controllability or Oa ≡ 0 no observability or a = 0 → Oa = 0 no drivability or Oa → a no drivability


Limitation of Implication Graph

a

b

c

d

e

s-a-0

s-a-0

Implication graph (some nodesand edges not shown)

Circuit with tworedundant faults

a b cd

OcOd

Implication graph shows no implications of c and d on their observabilities.


Adding Partial Implications

ab

c c = ab

Boolean false function: ab c = 0

ac + bc + abc = 0

a b c

cba

Λ

V

Henftling and Wittmann, AEÜ, 1995 (Λ node)

Λ and V nodes represent partial implications

Dave, Master’s Thesis, 2004 (V node)


Using Partial Implications

a

b

c

d

e

s-a-0

s-a-0

Implication graph (some nodesand edges not shown)

Circuit with tworedundant faults

ImplicationPartial implication

a b cd

OcOd

Transitive closure edge


Another Example

V1

a b c

cba

Λ1Λ2

d

d

V2

ab

c

d e

e

eΛ4

Λ3

s-a-0s-a-0s-a-1

s-a-0s-a-1

Contrapositive of đ → ē

e ≡ 0


Results on ISCAS Circuits

CircuitTotal faults

Redundant faults identified and run time

TRAN

Chakradhar

et al.

FIRE

Iyer and Abramovici

Imp. graph

Mehta et al.

Enhanced

Imp. Graph

Dave et al.

Red. faults

CPU

sa

Red. Faults

CPU

sb

Red. Faults

CPU

sa

Red. Faults

CPU

sa

c1908 1879 7 13.0 6 1.8 2 3.2 5 5.7

c2670 2747 115 95.2 29 1.5 59 4.0 69 6.0

c7552 7550 131 308.0 30 4.7 51 11.5 65 17.7

s1238c 1355 69 17.4 6 1.9 20 2.6 51 5.4

aSun SPARC5 CPU Sec. bSun SPARC2 CPU Sec.


Referenced Methods TRAN – ATPG

S. T. Chakradhar, V. D. Agrawal and S. G. Rothweiler, “A Transitive Closure Algorithm for Test Generation,” IEEE Trans. CAD, vol. 12, no. 7, pp. 1015-1028, July 1993.

FIRE – Implication analysis M. A. Iyer and M. Abramovici, “FIRE: A Fault-Independent

Combinational Redundancy Identification Algorithm,” IEEE Trans. VLSI Systems, vol. 4, no. 2, pp. 295-301, June 1996.

Implication Graph V. J. Mehta, “Redundancy Identification in Logic Circuits using

Extended Implication Graph and Stem Unobservability Theorems,” Master’s Thesis, Rutgers University, Dept. of ECE, New Brunswick, NJ, May 2003.

K. K. Dave, “Using Contrapositive Rule to Enhance the Implication Graphs of Logic Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, New Brunswick, NJ, May 2004.


C1908: Unidentified Redundancies

979887

74

952

953

949

926

Redundant faults (s-a-1)

0

0

0/1

Total redundant faults = 7; identified = 5


C5315: Unidentified Redundancy

1

0/1

0/1

1

1

1

1

1

0/1

PI

PI

PO

0 0

0 0

0/1

0

1

1

1

Redundant fault (s-a-1)

Total redundant faults = 59; identified = 58


C5315: Continued . . .

1

0/1

0/1

1

0

0

0

1

0/1

PI

PI

PO

1 1

1 0/1

0

1

0

Redundant fault (s-a-1)

1

1


Conclusion Partial implications improve fault-independent redundancy

identification – present results are the best known. Transitive closure computation run times are empirically

linear in the number of nodes for benchmark circuits -- the known worst-case complexity is O(N3) for N nodes.

Update algorithm can efficiently compute transitive closure when implication graph has sparse connectivity.

Weakness of implication method: Observability of fanout stems. Recent work has shown that some unobservable fanout stems can be identified from transitive closure analysis.

Reconvergent gate

Dominatora

b

c d

Observability of a has no direct relation to observabilities of b and c, but can be related to that of d


Our Students

Srimat Chakradhar, NECQing Lin, Sun MicrosystemsPhilip Stanley-Marbell, CMU Graduate

ProgramVivek Gaur, SynopsysVishal Mehta, UCSB PhD ProgramKunal Dave, ATI

Documents

Implication Graphs and Logic Testing