Indium Phosphide Bipolar Integrated Circuits: 40 GHz and beyond

Mark Rodwell

University of California, Santa Barbara

rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax

ISSCC 2003 Special Topic Session: Circuits in Emerging Technologies, February 9, San Francisco

Applications of InP HBTs

Optical Fiber Transceivers

40 Gb/s:InP and SiGe HBT both feasible ICs now available; market has vanished

80 & 160 Gb/s may come in timewithin feasibility for scaled InP HBTworld may not need capacity for some timeWDM might be better use of fiber bandwidth

mmWave Transmission

65-80 GHz, 120-160 GHz, 220-300 GHz LinksLow atmospheric attenuation (weather permitting).High antenna gains (short wavelengths).10 Gb/s transmission over 500 meters with 20 cm antennas needs 4 mW transmitter power

59-64 GHz LANs: short range, wideband, broadcast

Mixed-Signal ICs for Military Radar/Comms

direct digital frequency synthesis, ADCs, DACshigh resolution at very high bandwidths sought

Motivation for InP HBTsParameter InP/InGaAs Si/SiGe benefit (simplified) collector electron velocity 3E7 cm/s 1E7 cm/s lower c , higher Jbase electron diffusivity 40 cm2/s ~2-4 cm2/s lower b

base sheet resistivity 500 Ohm 5000 Ohm lower Rbb

comparable breakdown fields

Consequences, if comparable scaling & parasitic reduction: ~3:1 higher bandwidth at a given scaling generation~3:1 higher breakdown at a given bandwidth

Problem for InP: SiGe has much better scaling & parasitic reduction

Technology comparison today:Production SiGe and InP have comparable speedSiGe has much higher integration scalesProduction 1 m InP: low NRE, fast design cycle for SSI/MSI ICs to ~90 GHz

(cost includes design time as well as $/mm2

Present efforts in InP research community Development of low-parasitic, highly-scaled, high-yield fabrication processes

InP HBT fabrication processes today

Mesa processes with self-aligned base contacts: Research labs Moderately low yield → 1000 HBTs/IC300 GHz f, 400 GHz fmax , 7 V BVCEO, 100 GHz clock~ 0.5 m emitter width

Mesa processes with non-self-aligned base contacts: Production in GaAs HBT foundries (cell phone power amps) Somewhat better yield → 3000 HBTs/IC (?)150 GHz f, 180 GHz fmax , 7 V BVCEO, 70-90 GHz clock 0.8 m emitter width, 1.0 $/mm2

Exotic research processes for reduced Ccb: 1) transferred-substrate, 2) strongly undercut collector mesatechnology demonstrations, not IC technologies

Present research processes in InP community: early development phasescombine InP materials advantages with SiGe-like processesjunction regrowth, dielectric sidewalls, trenches, pedestal implants… …more detail in later slides

Scaling

key device parameter required change

collector depletion layer thickness decrease 2:1

base thickness decrease 0.707:1

emitter junction width decrease 4:1

collector junction width decrease 4:1

emitter resistance per unit emitter area decrease 4:1

current density increase 4:1

base contact resistivity

(if contacts lie above collector junction)

decrease 4:1

base contact resistivity

(if contacts do not lie above collector junction)

unchanged

Required transistor design changes required to double transistor bandwidth

…easily derived by basic geometric calculations

WE

WBC

WEB

x

L E

base

emitter

base

collector

WC

(C ’s, ’s, I/C ’s all reduced 2:1)

Parasitic Reduction

SiO2 SiO2

P base

N+ subcollector

N-

thick extrinsic base : low resistancethin intrinsic base: low transit time

wide emitter contact: low resistancenarrow emitter junction: scaling (low Rbb/Ae)

wide base contacts: low resistancenarrow collector junction: low capacitance

At a given scaling generation, intelligent choice of device geometry reduces extrinsic parasitics

Much more fully developed in Si…

Optical Transmitters / Receivers are Mixed-Signal ICs

TIA: small-signal

aa

routebuffer

SwitchWideband Optical Transceiver

clockPLL

AD

DMUX

O/E, E/O interfaces

MUX

AD

AD

IQ

I

Q

DMUX

DMUX

mm-wave interfaces

I

Q

DA

DA

IQ

electronicor optical

Wideband mm-Wave Transceiver

Electronics for GigaHertz Communication

poweramplifier

MUX

addressdetect

PLL

Switches:network protocols,digital control, fast ICs,optical, electronic switches

Rf

Rc

Q1

Q2

I1

I2

Rf

Rc

Q1

Q2

I1

I2

  LIA: often limiting MUX/CMU & DMUX/CDR:mostly digital

Small-signal cutoff frequencies (f, fmax) are ~ predictive of analog speedLimiting and digital speed much more strongly determined by (I/C) ratios

InP HBT has been well-optimized for f & fmax, less well for digital speed

How do we improve gate delay ?

clock clock clock clock

inin

out

out

cexLOGIC

LOGIC

Ccb

becb

becbC

LOGIC

IRq

kTV

V

IR

CCR

CCI

V

6

leastat bemust swing logic The

resistance base the through

charge stored

collector base Supplying

resistance base the through

charging ecapacitancDepletion

swing logic the through

charging ecapacitancDepletion

:by DeterminedDelay Gate

bb

depletion,bb

depletion,

max

logic

emitter

collector

min,

depl,

& not speed,clock for design toneed

:SiGen faster thabarely logic InP

high at lowfor low very bemust

22

objective.design HBTkey a is /High

total.of 80%-60% is

. with correlated not wellDelay

ff

JVR

v

T

A

A

V

V

I

VC

CI

CCIV

f

eex

effective

C

CE

LOGIC

C

LOGICcb

cbC

becbCLOGIC

Why isn't base+collector transit time so important ?

1:10~ is which ,/

of ratioby reduced

ecapacitancdiffusion signal-Large

)(

)(Q

:Operation Signal-LargeUnder

swing. voltage/over only ...active

/

)(

)(

)(Q

:ecapacitancDiffusion

base

base

qkT

V

VV

I

I

qkT

VqkT

I

VdV

dI

I

LOGIC

LOGICLOGIC

dccb

Ccb

beCcb

bebe

Ccb

Ccb

Depletion capacitances present over full voltage swing, no large-signal reduction

Vin

Vout

Vin(t)

t

t

Vout(t)

diffusion+ depletioncapacitance

only depletioncapacitance

Scaling Laws, Collector Current Density, Ccb charging time

base

emitter

collector

subcollector

base

emitter

collector

subcollector

Collector Field Collapse (Kirk Effect)

Collector Depletion Layer Collapse

)2/)(/( 2 cdsatcb TqNvJV

)2/)(( 2min, cTqNV dcb

2min,max /)2(2 ccbcbsat TVVvJ

Collector capacitance charging time is reduced by thinning the collector while increasing current

sat

C

CECE

LOGICCLOGICcCLOGICcb v

T

A

A

VV

VIVTAIVC

2/

emitter

collector

min,collector

cecbbe VVV )( hence , that Note

Challenges with Scaling:

Collector-base scaling Mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer length → sets minimum size for collector Solution: reduce base contact resistivity → narrower base contacts allowedSolution: decouple base & collector dimensions

e.g. buried SiO2 in junction (SiGe)

Emitter Ohmic Resistivity: must improve in proportion to square of speed improvements

Current Density: self-heating, current-induced dopant migration, dark-line defect formation

Loss of breakdownavalanche Vbr never less than collector bandgap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power

Yield submicron InP processes have progressively decreasing yield

Technology Roadmaps for 40 / 80 / 160 Gb/s

Parameter Mesa HBT Generation 1

Mesa HBT Generation 2

Mesa HBT Generation 3

Simulated MS-DFF speed (no interconnects)

62 GHz 125 GHz 237 GHz

Emitter Junction Width 1 m 0.8 m 0.2 m Parasitic Resistivity 50 -m2 20 -m2 5 -m2

Base Thickness 400Å 300Å 250Å Doping 5 1019 /cm2 7 1019 /cm2 1020 /cm2 Sheet resistance 750 700 700 Contact resistance 150 -m2 20 -m2 10 -m2

Collector Width 3 m 1.6 m m Collector Thickness 3000 Å 2000 Å 1000 Å Current Density 1 mA/m2 2.3 mA/m2 9.3 mA/m2 Acollector/Aemitter 4.55 2.6 2.6

f 170 260 500

maxf 170 440 700

ccb IC / 1.7 ps/V 0.63 ps/V 0.31 ps/V

ccb IVC /logic 0.5 ps 0.19 ps 0.093 ps

)//( logic cbb IVR 0.8 0.65 0.52

)/( logic Cje IVC 1.7 ps 0.72 ps 0.18 ps

)//( logic cex IVR 0.1 0.15 0.15

InP-collector DHBTs: Self-Aligned Mesa Structure

M Dahlstrom (UCSB/ONR), Amy Liu (IQE)

200 nm InP collector, 30 nm InGaAs base8(1019) /cm3 base doping

1 m base contacts, 0.5 m x 7.5 m emitter junction0.7 m emitter contact

Vce=1.7 V J=3.7E5 A/cm2

0

5

10

15

20

25

30

1010 1011 1012

Ga

ins

(dB

)

Frequency (Hz)

ft=282 GHz

fmax

>400 GHz

U

H21

0

1

2

3

4

5

0 0.5 1 1.5 2 2.5 3

I C (

mA

)

VCE

(V)

emitter junction area: 0.44 m x 7.4 mIB step = 50 uA

0

0.5

1

1.5

2

2.5

3

0 1 2 3 4 5 6 7 8

Vbr,ceo=7 V

Collector / Emitter Ratio: 2.0 um / 0.5 um, 1.2 um / 0.5 um

0.7 um base contact width 0.3 um base contact width

Submicron InAlAs/InGaAs HBTs: High power gains at very high frequencies

Gains are high at 220 GHz, but fmax can’t be extrapolated

UCSB/ONR: Miguel Urteaga

0

10

20

30

40

1010 1011 1012

Gai

ns, d

B

Frequency, Hz

U

h21

MSG

unbounded U

Vce

= 1.1 V, Ic=5 mA

0.3 m x 18 m emitter,0.7 m x 18.6 m collector

transferred-substrate device

freq (6.000GHz to 40.00GHz)

freq (75.00GHz to 110.0GHz)freq (140.0GHz to 220.0GHz)

S11

S22

S21S12*25

-4 -2 0 2 4-6 6

freq (6.000GHz to 40.00GHz)

freq (75.00GHz to 110.0GHz)freq (140.0GHz to 220.0GHz)

6-40, 75-110, 140-220 GHz

0

10

20

30

40

1 10 100 1000

Gai

ns (

dB)

Frequency (GHz)

U

h21 462

395

343

139

0

1

2

0 2 4 6 8

I C (

mA

)

VCE

(V)

Ib step = 20 A fmax = 460 GHz

ft = 139 GHz

InP-Collector Double Heterojunction Bipolar Transistors

0.5 m x 8 m emitter (mask)0.4 m x 7.5 m emitter (junction)1.0 m x 8.75 m collector3000 Å collector drift region

VBR,CEO = 8 V @ JE =5*104 A/cm2

UCSB/ONR: S. Lee

transferred-substrate process

Large-Area (High Current) DHBTs for mm-Wave Power

8-finger device: 1 x 16 m emitter, 2 x 20 m collector

UCSB/ARO: Y. Wei

VBR,CBO> 7V

Key challenges with high-current HBTs: - thermal stability (ballasting)- minimal base feed metal parasitic resistance- reliable electromagnetic models of feed networks

InP/InGaAs/InP Metamorphic DHBTs on GaAs substrates

UCSB/ONR: Young-Min Kim

0

2

4

6

8

10

12

14

0

1 105

2 105

3 105

4 105

0 1 2 3 4 5 6

J (A/cm

2 )I C (

mA

)

VCE

(V)

0

5

10

15

20

25

30

35

1 10 100 1000

Ga

ins

(dB

)

Frequency (GHz)

h21

U

ft, f

max = 200 GHz

Comparable performanceto lattice-matched of similar design.

Potential for SSI/MSI InP HBTsin cheap GaAs HBT foundry processes.

174 GHz, 6.3 dB, Single-Transistor Amplifier

-20

-15

-10

-5

0

5

10

140 150 160 170 180 190 200 210 220

S21S11S22

dB

Freq. (GHz)

0.2pF

50 301.2ps

50

300.2ps

801.2ps

0.6ps

801.2ps

50

IN

OUT

UCSB/ONR: Miguel Urteaga

0.3 um transferred-substrate HBT

Multi-Stage 140-220 GHz Amplifiers

Three-stage amplifier designs:

12.0 dB gain at 170 GHz

8.5 dB gain at 195 GHz

Cascaded 50 stages with interstage blocking capacitors

Cell Dimensions: 1.6 mm x 0.59 mm0.3 um transferred-substrate HBT

-30

-20

-10

0

10

20

140 150 160 170 180 190 200 210 220

S21S11S22

dB

frequency (GHz)

UCSB/ONR: Miguel Urteaga

75 GHz, 80 mW Power Amplifier

2.6 pS17

0.31 pS17

0.15 pS42

2.3 pS42

0.38 pS50

0.38 pS50 0.58 pS

37

0.58 pS37

CSiN=92fF

CSiN=92fF

CSiN=44fF

CSiN=44fF

CSiN=15fF

CSiN=15fF

0.4 0.9 mm die, AE = 16 x (1m x 16 m) = 256 m2

transferred-substrate process

Bias: Ic=130 mA, Vce=4.5 V

0

5

10

15

20

0

2

4

6

8

10

-5 0 5 10 15

Pou

t (dB

m) G

ain (dB)

PA

E (%

)

Pin (dBm)

Gain

PAE

Pout

UCSB/ARO: Y. Wei

250-500 mW is feasible; UCSB designs are constrained by yield difficulties with large # of fingers

87 GHz HBT static frequency divider

InAlAs /InGaAs/InP MESA DHBT

400 Å base, 2000 Å collector,

9 V BVCEO

200 GHz ft, 180 GHz fmax

2.5 x 105 A/cm2 operation

UCSB/ONR: PK Sundararajan

-0.2

-0.18

-0.16

-0.14

-0.12

-0.1

-0.08

-0.06

22 22.02 22.04 22.06 22.08 22.1 22.12 22.14

87 GHz input, 43.5 GHz output

Vo

ut (

Vol

ts)

time (nsec)

InPhi slides

InPhi slides

OC-768 Linear Components

Frequency (GHz)

Tra

nsi

mp

ed

an

ce (

dB

oh

ms)

(s

ing

le-e

nd

ed

) Transimpedance Amplifier 26 dB Limiting Amplifier

43 Gb/s

Design Challenges: Gain flatnessPeaking due to interconnect inductance,gm element phase shift, Ccb variation, photodiode parasitics, single-ended / differential converter.

Jaganathan & PullelaVetury, Pullela, Rodwelll

curves with, withoutPIN parasitics

-7.8 dBm sensitivity @ 10-12 BER (231-1) PRBS

DINP

DINN

DOUTP

DOUTN

Vcc

Vcc

Vxpp

Vxpn

cell-1 cell-n cell-10

TISDA

TAS TAS

OC-768 Modulator Driver

30 dB gain, 40 GHz bandwidth, >10 dB S11 & S22

8 ps rise/fall (20-80%) , ~0.9 ps RMS jitter 3 Vpp single ended output, 6 V differential

Design Issues: Gain flatnessDistributed line losses, current handling & loaded Z0

Complexity of transmission-line layoutAssociated low-frequency droopEmitter follower negative resistance → peakingEfficacy of bypass capacitancesCommon-mode traveling-wave instability

K. Krishnamurti et al

OC-768 Digital Components

4:1MUX

PFD VCO

LockDetect

TimingControl

FF

DI0

DI3

DO

DCKI

ClkOut

PFDO

LockDet

Vcon

Buf

Disable

Amp4:1

MUX

PFDPFD VCOVCO

LockDetectLock

Detect

TimingControl

FFFF

DI0

DI3

DO

DCKI

ClkOut

PFDO

LockDet

Vcon

Buf

Disable

Amp

4:1 Multiplexer / CMU

47 Gb/s

Limiting amplifier

DP

DN

AGND

50

10 Gb/sDifferentialData outputs

Timing

2:4DEMUX

OFFSET SENSE Output

4 x 10 Gb/s

1:2DEMUX+P.D

VCO

PFD

Sel

LockDetect

622Mhz

Ref Clk inputs (622MHz)

Lock Detect

DifferentialData Inputs

Limiting amplifier

DP

DN

AGND

50

10 Gb/sDifferentialData outputs

TimingControl

2:4DEMUX

OFFSET SENSE Output

4 x 10 Gb/s

5 GHz clock

1:2DEMUX+P.D

VCO

PFD

Sel

LockDetect

622Mhz

Ref Clk inputs (622MHz)

Lock Detect

PIFilter

DifferentialData Inputs

VEE

VEEA

Lock_Ref

C1

Limiting amplifier

DP

DN

AGND

50

10 Gb/sDifferentialData outputs

Timing

2:4DEMUX

OFFSET SENSE Output

4 x 10 Gb/s

1:2DEMUX+P.D

VCO

PFD

Sel

LockDetect

622Mhz

Ref Clk inputs (622MHz)

Lock Detect

DifferentialData Inputs

Limiting amplifier

DP

DN

AGND

50

10 Gb/sDifferentialData outputs

TimingControl

2:4DEMUX

OFFSET SENSE Output

4 x 10 Gb/s

5 GHz clock

1:2DEMUX+P.D

VCO

PFD

Sel

LockDetect

622Mhz

Ref Clk inputs (622MHz)

Lock Detect

PIFilter

DifferentialData Inputs

VEE

VEEA

Lock_Ref

C1

1:4 Demultiplexer / CDR (recovered 10 Gb/s data)

High current density 10 mA/m2

T-shaped polysilicon emitter 0.25 m junction wide contact low resistance, high yield

Thin intrinsic base: low b

Thick extrinsic base: low Rbb

Low Ccb collector junction collector pedestal CVD/CMP SiO2 planarization regrown poly extrinsic base

High-yield, planar processing high levels of integration LSI and VLSI capabilities

SiGe clock rates up to 65 GHzMuch more complex ICs than feasible in InP HBTInP HBT must reach higher integration scales or will cease to compete

Very strong features of SiGe-bipolar transistors

Submicron InP HBT Development: Research

Objective: speed extrinsic parasitic reductiondeep submicron scaling

Objective: yieldplanar processeliminate liftoffeliminate undercut etches

Target Applications: High speed (>100 GHz) digital& mixed signal. 160 Gb/s optical fiber transmission

Similar research effortsRockwell/GCS/UCSBVitesse. Lucent. TRW. HRL Labs.

N- collector

N+ subcollector

S.I. substrate

Si3

N4

intrinsic base*

regrownextrinsic base*

base contact

Si3

N4

regrown emitter *emitter contact

collector contact

implant ortrench isolation-eliminates mesas

N- collector

N+ subcollector

S.I. substrate

emitter-base separationby dielectric sidewall

base contact widthdefined by dielecricsidewall

sputter & dry-etchedW emitter contact,dry-etched emitter

near-planarbase mesa etchedonly to collector

Double-poly (SiGe-like) HBT

Planar HBT: Dielectric Sidewall Process

InP HBTs

InP has better electron transport than SiGe → faster if comparable-quality fabrication processes are employed.

Adaptation of 1-m GaAs (cell phone) HBT foundry process to InP → Inexpensive, low NRE, low mask cost, fast design cycle Good process for SSI/MSI optical fiber and mm-wave ICs Not good for larger-scale digital / mixed-signal ICs

Conventional but more highly scaled InP HBT processes → millimeter-wave power to 200 GHz, perhaps beyond. Future markets ?

Present efforts in InP research community low-parasitic, highly-scaled, high-yield fabrication processes → 3:1 higher bandwidth at a given scaling generation → 3:1 higher breakdown at a given bandwidth Substantial risk of failure, substantial benefit if successful.