Information technology

Department of Information Technology Introduction The Department of Information Technology started its journey in 2000. It is one of the youngest departments of this 150 years old University. The department has produced excellent IT engineers who are serving in different reputed organizations and pursuing higher studies at Institutes of excellence. The department provides state of the art computational facilities for the students. The strength of the department has been in its diverse areas of research in which it has a remarkable contribution.

Academic Programmes

a. Undergraduate Level B.E. in Information Technology: The B.E. program is a four-year course oriented undergraduate program. The course work is spread across all the semesters. The courses include a set of core courses offered by the department, a set of departmental electives and some free electives. Apart from this, a student must complete three courses in his or her minor area. The minor area must be different from Information Technology. Besides, a student must also complete a project in the eighth semester towards the fulfillment of the degree requirements.

b. Postgraduate Level

M.E. in Information and Communication Engineering: The M.E. program is a two-year course oriented graduate program. The student has to take a set of core courses and a set of electives. The course work is spread across the first two semesters with an option of taking one elective in the third semester. This is followed by a project in the third and fourth semester in which the student can take up a project of his or her interest, supervised by a faculty member.

c. Doctoral Level

PhD in Information Technology: The PhD. programs are postgraduate research oriented programs. The scholar works in an area of his/her interest under the supervision of a faculty member. The scholar has to obtain a minimum number of credits by taking courses. The highlight of the program is the independent research work taken by scholar, leading to a dissertation at the end of the program. The average duration of a PhD. program is between four to five years

Student’s intake

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U.G P.G Ph.D

Sanctioned students’ intake 60 18 11- Registered

1- Awarded

1- Thesis submitted Additional intake through lateral entry/ QIP 6 -

Ph.D Activities PhD. Awarded during 2009-2010 session 1. Tuhina Samanta : Non-Manhattan Interconnects: Studies and Design of Algorithms.

PhD. Submitted during 2009-2010 session

2. Chandrama Shaw : Theory and Applications of Cellular Automata in Data Compression.

PhD. Registered/Enrolled

1. Prasun Ghosal, Thesis area: Study and Design of Algorithms on 3D VLSI Layout

Design.

2. Indrajit Banerjee. Thesis topic: Application of Cellular Automata for Sensor Network

Management

3. Somsubhra Talapatra, Thesis area: VLSI Architectures for Galois Field Operations in the

context of Communications and Cryptography.

4. Debasis Mitra. Thesis area: Testing of Biochips.

5. Pranab Roy. Thesis area: Physical Design of Biochips

6. Dipak K. Kole. Thesis topic: Synthesis and Testing of Reversible Circuits. 7. Amit Phadikar, Thesis area: Data Hiding for Access Control, Error Concealment and

Right Management.

8. Goutam Kr. Maity,, Thesis Area: Studies on Development of All Optical Information

Processing Circuits using Non-linear material based Switches

9. Sumanta Hati, Design and Analysis of Multicarrier Code Division Multiple Access: Scope of Soft computing

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Faculty position

Nos. Sanctioned faculty post 9 Professor 1 Asst. Professor 2 Lecturer 6 Vacant post

Faculty Profile

Faculty Name Desig nation

Highest Qualification Specialization/ Research Area Contact No. / Mail Id

Dr. Hafizur Rahaman Professor Ph.D o Design & Testing VLSI Circuits o Network-On-Chip o SOC Testing o Design & Testing of Cryptographic Hardware o Design & Testing of Micro fludic Bio Chip

[email protected] Extn. no.260/848

Dr.Santi Prasad Maity Asst.Professor Ph.D o Digital Image Watermarking o Wavelets for image de-noising, watermarking, Access

control and Error concealment o Optimized spread Spectrum watermarking o VLSI for watermarking o PAPR reduction in multicarrier communication o Wireless Channel Estimation o Multiuser Detection in MC-CDMA o Optical Computing

[email protected] Extn. no.846

Mr. Arindam Biswas Asst.Professor M.Tech o Digital Geometry o Image Processing and Pattern Recognition


Mr.Indrajit Banerjee Lecturer M.Tech o Wireless ad-hoc Sensor Network [email protected] Extn. no.860

Mr. Prasun Ghosal Lecturer M.Tech o 3D Integration of VLSI Physical Design o Network-On-Chip o Design of Embedded Systems


Dr. Sukanta Das Lecturer Ph.D o Cellular Automata o Distributed Computing


Miss.Tuhina Samanta Lecturer M.Tech o Design of algorithms for VLSI inter connect design o Developing of algorithm for Physucal design of Digital

Micro-fluidic Biochip


Dr. Chandan Giri Lecturer Ph.D o VLSI digital Circuit Testing o System-On-Chip Testing o Network-On-Chip Testing


Mr.Surajit kr. Roy Lecturer M.Tech o SOC Testing [email protected] Extn. no.861

Awards and Laurels: Awards Dr. Hafizur Rahaman INSA Royal Society Fellowship Award Year: 2006-2007

Royal Society International Fellowship Award Year: 2008-2009 Dr. Santi Prasad Maity Post-Doctoral Fellowship, Laboratoire Des Signaux et Systems,

Supelec, CNRS, Universite Paris SUD11, France. Jan09-July09. Research area:

Below we mention selected areas of research contributions made by the department.

A. Systems Architecture and Design Computer Architecture, Design, Testing, Verification, Algorithms and VLSI CAD

B. Theory and Applications of Cellular Automata in

Distributed Computing, Pattern Recognition, Traffic Modeling and VLSI design & Test

C. Digital Image Watermarking and Signal Processing

LBM and Additive watermarking using signal processing tools High Payload Spread Spectrum watermarking using Wavelets

QIM watermarking for Access control and Error Concealment Optimized Spread Spectrum watermarking VLSI architecture for watermarking

D. Digital Geometry and Image Analysis Shape Analysis 3D Image Analysis Face Recognition Document Image Analysis E. Wireless and Mobile Communication, Sensor Network

PAPR reduction in Multicarrier System Multiuser Detection in MC-CDMA Channel estimation Optimized system design Efficient Routing protocol Energy efficient WSN Management

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Research facilities:

i) Computing Facilities

Model Specification No. A. MAIL SERVER & FILE SERVER

X Series 236 @ server (IBM ) Intel Single Xeon DP Processor @ 3.2 GHz EM

64T 2

B. SUN SERVER SUN FIRE V215 SERVER PROCESSOR 2X ULTRA SPARC 111 1

C. ORACLE SERVER

Single or Dual Intel® Xeon® 3.0 GHz processors or Single or Dual Intel® Xeon® 3.2

GHz processors (dependent on model)

1

D.HP XW 4600Workstation Intel Dual Core 3 GHZ 2

E. HP COMPAQ DX 7200 MICROTOWER & DELL OPTIPLEX 780 Desktop

INTEL P-IV HT 3 GHZ & CORE DUO 2.80 GHZ

2GB DDR2 RAM

180 F. HP Compaq dx7400 MICROTOWER

INTEL CORE 2 DUO 1.60 GHZ 1 GB DDR2 RAM

G. HP COMPAQ DX 7200 MICROTOWER

INTEL P-IV HT 3 GHZ

ii) Software

• Windows 98(SE) • Red Hat Linux 703 professional • Norton systems works • Personal oracle 8015 (Win 98 compatible) • Visual studio .Net professional (Single user) • MS office XP (Prof) • Macromedia flash • ADOBE Photoshop CS2 version 9 educational paper license • ADOBE Photoshop CS2 version 9 Edu media kit on CD • Windows 2000 (OEM Pack) • Win 2000 server plus (Academic editions) Client license • Oracle 10G database std-I edition on linux • McAfee Active Virus Scan P:1 Gold(101 user)

8

• Adobe Acrobat Professional 9 • Matlab R2008a (Client Server) (30 user) • Simulink (5 user) • Signal Processing Toolbox(5 user) • ATS for oracle std-I for 1 year • Media for oracle in CD • Internet developer suite on windows XP OS • Sound forge (latest version) Edu full box on CD • Rational Rose • Microsoft windows XP prof. Upgrade OLP NL-AE • Microsoft office 2003 prof. OLP NL-AE • Microsoft studio 8 Edu paper license • Microsoft windows XP prof. Media kit on CD • Microsoft office 2003 prof. Media kit on CD • Microsoft studio 8 Edu media kit on CD • 1SE Design Suite Foundation 8.1i,9.1i,10.1i,11.1i • Chip scope Pro • Embedded Development kit • Plan Ahead • System Generator • Accel DSP • Model XE Simulator

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iii) Electronics Equipment Sl. No. Name of the Item

Qty

1 Microcontroller Kit SDA 51. 12 2 P-N Sequence generator. 04 3 Test ROM for NIFC- 27. 01 4 26 pin I/O connector. 15 5 PMS DSP 320C 30Trainer KIT. 06 6 Parallel Port Cable for DSP C-30. 06 7 Input /Output Cable. 06 8 Power Supply for SDA –51. 12 9 8085 Microprocessor Trainer kit. 18 10 8086 Microprocessor Trainer kit. 06 11 Traffic Light simulator Interface Kit (ALS -NIFC-11). 06 12 DAC for ADC Temperature Sensor Dual slope ADC interface for

µP trainers(ALS-NIFC-10). 04

13 Interface to study A/D and D/A converter(NIFC-27). 02 14 JP6 of Interface card to Trainer Kit Connector. 02 15 Test ROM for NIFC- 01and NIFC-11. 01 16 CROSS COMPILER FOR DSP 01 17 DIGITAL STORAGE OSCILLOSCOPE 01 18 SPECTRUM ANALYZER 01 19 Vector Signal Generator 01 20 Spartan-3 AN FPGA Development Board 05 21 Spartan-3 FPGA Development Board 01 22 Virtex-5 FPGA Development Board 02

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Support staff position

Technical staff profile

.

Staff Name Designation Highest Qualification Contact No E-mail Id

Soma Sardar Technical Assistant MCA ,M.Tech(Pursuing) 9433487298

[email protected]

Samaresh Hazra Technical Assistant

D.C.S.T, M.Sc in Computer Science 9231596396 [email protected]

Snehashis Saha Technical Assistant

M.Sc in Mathematics, P.G.D.C.A 9830573478 [email protected]

Subhajit Biswas Technical Assistant Diploma in C.S.T 9830146357 [email protected]

Soumen Gope Technical Assistant

B.Tech(CSE),M.Tech in IT(Pursuing) 9433985637 [email protected]

Amiya Ratan Rout Technical Assistant

B.Sc in Mathematics, M.Sc in CS(Pursuing) 9232606401 [email protected]

Pradip Mistry Technical Assistant

Diploma in E.T.C, A.M.I.E(Pursuing) 9432269081 [email protected]

Souvik Patra Technical Assistant B.Tech(CSE) 9433730433

[email protected]

Bishnupada Choudhury

Technical Assistant B.Sc ,MCA(Pursuing) 9432926952

[email protected]

Ashis Mondal (Contractual)

Technical Assistant

DCST, A.M.I.E(ECE), M.Tech in CSE (Pursuing) 9883683310 [email protected]

Suhrid Bakshi (Contractual)

Technical Assistant

MCA, M.Tech in IT (Pursuing) 9432094054 [email protected]

Sanchayita Dhara (Contractual)

Technical Assistant

Diploma in E.T.C, A.M.I.E(Pursuing) 9433957440 [email protected]

Suman Chakraborty (Contractual)

Technical Assistant

B.Tech(IT),M.Tech in IT(Pursuing) 9231978218 [email protected]

Office Staff Malay Kr. Dhir Office

Assistant B.Com 9831365531 [email protected]

Mosiur Rahman Office Assistant M.Com 9874975705 [email protected]

om Suman Sarkar Group D Madhyamik 9007612086

[email protected]

Dinabandhu Sadhukhan Group D Madhyamik 8013144160

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Sponsored Research:

Sl. No Title Source of Funding Total Cost Date of

Sanction Duration

1

High Power and Spectral Efficiency Multi-User System

for Broadband Wireless

Communication

Ministry of Communication and

Information Technology, Govt. of

India

51.16 Lacs 31.03.2008 2 years

2

Development Of FPGA Based

Embedded System for Network On

Chip (NOC) Application

AICTE (All India Council for Technical Education ),New Delhi

6.5 Lacs March,2008 2 years

3 Digitization of

Academy Banan Abhidhan

(SNLTR) Society for Natural Language

Technology Research1,00,338 Sept, 2008 Complete

4

Web Hosting of Rabindra

Rachanbali in Unicode Format

(SNLTR) Society for Natural Language

Technology Research

10,46,500

Sept, 2008

1 year

Publications summary (year 2009)

Published Remarks

Journal 23+ 1 (Communicated)

-

Conference 56

-

Books / Monograms 3+ 1 Copyright

-

12

Detailed Publication Year – 2009

1) Somsubhra Talapatra and Hafizur Rahaman, “Low Complexity Digit Serial Systolic Montgomery

Multipliers for Special Class of GF(2m)”, IEEE Transactions on VLSI Systems.

2) Hafizur Rahaman, Jimson Mathew and Dhiraj K. Pradhan, “Test Generation in Systolic Architecture for Multiplication over GF(2m)”, IEEE Transactions on VLSI Systems.

3) J. Mathew, H. Rahaman, and D. K. Pradhan, “A Galois Field Based Logic Synthesis Approach with Testability”, IET Computers & Digital Techniques.

4) Hafizur Rahaman, Asish Bera, Jimson Mathew and D. K. Pradhan, “Error Tolerant Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m),” International Journal of Electronic Science and Technology, Vol. 7, no. 4, China, July 2009,Pp.336-342

5) H. Rahaman, J. Mathew, and D. K. Pradhan, “Secure Testable S-box Architecture for Cryptographic Hardware Implementation”, The Computer Journal, OXFORD University Press.

6) J. Mathew, H. Rahaman, and D. K. Pradhan, “On the Synthesis of Bit-Parallel Galois Field Multipliers with On-line SEC and DED”, International Journal of Electronics.

7) H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Testable Design of AND-EXOR Logic Networks with Universal Tests for Detecting Stuck-at and Bridging Faults,” International Journal of Computers and Electrical Engineering (Elsevier), vol.35,pp. 644-658.

8) J. Mathew, H. Rahaman, A. Jabir and D. K. Pradhan, “Single Error Correctable Bit Parallel Multipliers Over GF(2^m)”, IET Computer and Digital Techniques, vol.3(3), pp.281-288, 2009.

9) Santi P. Maity, Malay K. Kundu and Seba Maity “Dual purpose FWT domain spread spectrumimage watermarking in real-time”, Special issues: circuits & systems for realtime security & copyright protection of multimedia, Computers & Electrical Engg., Elsevier , Vol. 35, No. 2, PP. 415-433, March 2009.

10) Santi P. Maity and Malay K. Kundu, Genetic Algorithm for Optimality of Data Hiding in Digital Images, Special issue on Bio-Inspired Information Hiding, Soft Computing, Springer Verlag, Vol. 13, No. 4, Feb. 2009, pp. 361-373.

11) Santi P. Maity and Seba Maity, “ Multistage Spread Spectrum Watermark Detection Technique using Fuzzy Logic” IEEE Signal Processing Letters, vol. 16, no. 4, pp.245-248, April 2009.

12) Amit Phadikar and Santi P. Maity, Quality access control of compressed color image, International Journal of Electronics and Communication Engg., Elsevier (Accepted)

13) Amit Phadikar and Santi P. Maity, ROI Based Quality Access Control of Compressed Color Image using DWT via Lifting, Electronic Letters on Computer Vision and Image Analysis (ELCVIA) , vol. 8, no. 2, pp.51-67, 2009. .

14) Santi P. Maity, Seba Maity and Jaya Sil, Spread spectrum watermark embedder optimization using Genetic

Algorithms, 7th international conferences on Advances in Pattern Recognition, Indian Statistical Institute,

Kolkata, 4-6 February, 2009 , IEEE Computer Society Press, pp. 29-32.

15) Amit Phadikar , Santi P. Maity and Hafizur Rahaman, Region Specific Spatial Domain Image Watermarking Scheme, 2009 IEEE International Advanced Computing, Patiala, India, March 6-7, 2009 , pp. 2160-2165.

16) Amit Phadikar, Santi P. Maity and Malay K. Kundu, An Optimized Image Database Watermarking Scheme using Genetic Algorithms and Lifting, 2009 IEEE International Advanced Computing (IACC 2009, Patiala, India, March 6-7, 2009, pp. 2151-2155.

17) Santi P. Maity and Mithun Mukherjee, A high capacity CI/MC-CDMA system for reduction in PAPR, 7Tth Annual Conference on Communication Networks & Services Research (CNSR 2009), Canada, pp. 297-304.

18) Santi P. Maity and Mithun Mukherjee, S.Z . Haque, Subcarrier PIC scheme for high capacity CI/MC-CDMA System with Variable Data Rates, IEEE Mobeile WiMAX’09, July 9-10,Napa Valley, California, 2009 (Accepted).

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19) S. Pal, I. Banerjee, “gsahda CABCy: Cellular Automata based Block Cipher for Sensor Network”, NCCNS 1st Conference On Cryptography and Network Security, Feb. 18-19 2009 Vellor, India.

20) Sukanta Das, Meghnath Saha and Biplab k Sikdar: Cellular Automata Model For Traffic In Crowded Cities. International Conference on Traffic and Granular Flow 2009 (TFG09), 22-24 June, 09, Shanghai, China

21) Tuhina Samanta, Prasun Ghosal, H. Rahaman, Partha Sarathi Dasgupta, “A method for the Multi-net Multi-pin Routing Problem with Layer Assignment”, In proceedings of 22nd International Conference on VLSI Design(VLSI Design – 09) , pages: 387 – 392.

22) Hafizur Rahaman, Asish Bera, Jimson Mathew and D. K. Pradhan, “Error Tolerant Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m), 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis (ICTD 2009), China, April 2009.

23) S. Ghosh, P. Ray, S. P. Maity and H. Rahaman, “Spread Spectrum Image Watermarking with Digital Design”, IEEE In terna t iona l Advance Compu t ing Con ference ( IACC’09) , March 6 -7 , 2009 , Ind ia , pp . 2118-2123 .

24) N. Das, P. Roy, D. K. Das and H. Rahaman, “Design of Run Time FPGA Router using JBits 3.0”, IEEE VLSI Design and Test Symposium, 2009 (Accepted).

25) Santi P. Maity, Seba Maity and Jaya Sil, Diversity Assisted GCIC for Spread Spectrum Watermark Detection using Genetic Algorithms, IEEE Conference on Image Processing, 2009 (Accepted).

26) Amit Phadikar , Santi P. Maity and Hafizur Rahaman, Quality access control of digital images by encryption and data hiding, IASTED VIIP 2009, UK (Accepted).

27) Amit Phadikar and Santi P. Maity, Image error concealment based on data hiding using dual-tree complex wavelets, 4th Indian International conference on Artificial Intelligence, Dec. 16-18, 2009, Bangalore, India, Proceedings to be published by LNCS (Accepted).

28) Amit Phadikar and Santi P. Maity, Claude Delpha, Image error concealment and quality access control based on data hiding and cryptography, 2009 International conference on Multimedia Information Networking and security, 18-20th November, 2009, China , pp. 583-587.

29) Santi P. Maity, Clude Delpha and Amit Phadikar, Spread Spectrum watermarking: From zero rate embedding to high payload system, Special session 4: Watermarking and Steganography, 2009 International conference on Multimedia Information Networking and security, 18-20th November, 2009, China, pp. 525-529 .

30) A. Biswas, P. Bhowmick and B. B. Bhattacharya. Construction of Isothetic Covers of a Digital Object: A Combinatorial Approach, Journal of Visual Communication and Image Represenation, Elsevier, (Accepted), July 2009.

31) Amit Phadikar, Santi P. Maity and Claude Delpha, Image error concealment and quality access control based on data hiding and cryptography, special issue of Telecommunication Systems journal, Springer Verlag (Accepted)

32) Santi P. Maity, Claude DELPHA, Sofiane BRACI and Rémy BOYER, Hidden QIM watermarking on compressed data using channel coding and lifting, Third International Conference on Pattern Recognition and Machine Intelligence (PReMI'09), December 16-20,2009, Indian Institute of Technology, Delhi, India,2009 vol. 5909, pp.414-419

33) Amit Phadikar and Santi P. Maity, Quality access control of digital images by encryption and data hiding, International Conference on Methods and Models in Computer Science (ICM2CS09), New Delhi, India (Accepted).

34) Amit Phadikar, Santi P. Maity and Mrinal K. Mandal, QIM data hiding for tamper detection and correction in digital images using wavelet transform, ICASSP 2010, USA (Communicated).

35) Amit Phadikar and Santi P. Maity, M-ary QIM data hiding for error concealment of digital image in JPEG pipeline, Proc. Of INT. Conf. On Advances in Computing, Control and Telecommunication Technologies, Kerala, India, December, 2009 (Accepted).

36) Amit Phadikar and Santi p. maity, ‘Image Error concealment based on data hiding using M-ary QIM’ Third International Conference on Imaging for Crime Detection and Prevention (ICDP-09), December 3,London, United Kingdom (Accepted).

37) Amit Phadikar and Santi P. Maity, Quality Access Control of Foregrounds of an Image using QIM Data Hiding’ 2nd IEEE Int. Conference on Intelligent Human Computer Interaction, January 16-18,2010 (Accepted).

38) Amit Phadikar and Santi P. Maity, ROI Based Error Concealment of Object Based Image Using Data hiding in JPEG 2000 Coding Pipeline, IEEE INDICON 2009 (Accepted)

39) Santi P. Maity and Claude DELPHA, Optimization in digital watermarking techniques, Chapter in Edited volume, Advanced Techniques in Multimedia watermarking: Image, video and Audio applications, IGI Global Publication, USA (Accepted).

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40) Santi P. Maity, Seba Maity and Jaya Sil, Estimation of Fading Attack on High Payload Spread Spectrum Watermarking with Variable Embedding Rate using Genetic Algorithms, Third International Conference on Imaging for Crime Detection and Prevention (ICDP-09), December 3, London, United Kingdom (Accepted)

41) Santi P. Maity, Spread Spectrum watermarking: Implementation in FPGA, Chapter in Edited volume, Advanced Techniques in Multimedia watermarking: Image, video and audio applications, IGI Global Publication, USA (Accepted)

42) Goutam K. Maity, Tanay Chattopadhyay, Dilip K. Gayen, Chinmoy Traphdar, Anup Kumar Maity, Santi P. Maity and and Jitendra N. Ray,All-optical binary flip-flop with the help of TerahertzOptical asymmetric demultiplexer, Natural Computing Journal, Springer Verlag (Accepted).

43) Goutam K. Maity, Santi P. Maity, Tanay Chattopadhyay and Jitendra Nath Roy, Mach-Zehnder Interferometer based all-optical Fredkin Gate, First International Conference on Trends in Optics and Photonics, Department of Applied Optics and Photonics, University of Calcutta, India, March 1-4, 2009 (Accepted)

44) Goutam K. Maity, Tanay Chattopadhyay, Jitendra Nath Roy and Santi P. Maity, “All-optical reversible multiplexer, 4th International conference on Computers and Devices for Communication, (CODEC-09), 14-16 December, 2009 (Accepted).

45) Santi P. Maity and Mithun Mukherjee, On Optimization of CI/MC-CDMA System, 20 th Commemorative IEEE Personal, Indoor and Mobile Radio Communications Symposium (PIMRC’09), Japan, 13-16th September, 2009 (Accepted).

46) Santi P. Maity and Mithun Mukherjee, Combined Phase and Code Optimization for PAPR Reduction in M-ary CI/MC-CDMA system, First UK-India International Workshop on Cognitive Wireless System (UKIWCWS 2009), Indian Institute of Technology, Delhi, India, Dec.11-12, 2009 (Accepted).

47) Santi P. Maity and Malay K. Kundu Performance improvement in Spread Spectrum image watermarking using wavelets, International Journal of Wavelets, Multiresolution and Information Processing, World Scientific Publishing Company (Accepted). pp 1-35.

48) Santi P. Maity and Malay Kundu, Santi P. Maity and Malay K. Kundu, DHT domain digital watermarking with low loss in image information, International Journal of Electronics and

Communication Engg., Elsevier ( Article in Press) pp. 1-15 49) Chandan Giri, B. Mallikarjuna Rao and Santanu Chattopadhyay, “Split Variable-Length Input Huffman Code

(SVIHC) With Improved Application to Test Data Compression for Embedded Cores in SOCs”, Accepted for Publication Journal of Electronics, 2009

50) Prasun Ghosal, Malabika Biswas, Manish Biswas: "A Fast, Efficient and Compact FPGA Implementation of Triple-DES Encryption and Decryption Algorithm with IP Core Generation and On-Chip Verification". Accepted for publication in conference proceedings journal of World Academy of Science, Engineering and Technology (WASET) International Conference on Information Technology (ICIT) 2009

51) Tuhina Samanta, Sudipta Maity, Hafizur Rahaman, Partha Sarathi Dasgupta, Near-optimal Y-routed Delay Trees in Nanometric Interconnect Design, Communicated to IETCDT in August, 2009.

52) Tuhina Samanta, Sudipta Maity, Hafizur Rahaman, Partha Sarathi Dasgupta, “Sub-optimal Y-routed Delay Trees with Multiple Sources”, In proceedings of International Conference on Information Technology (ICIT- 09), pages: 35-41. 53) Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta: “An Experimental Study of Interconnection Length in 3D and 2D VLSI”. Accepted for publication in Proceedings of the IEEE Latin American Symposium on Circuits and Systems (LASCAS) 2010

54) Avisek Chakraborty, Rohit Maloo, Prasun Ghosal: “SCRABLER: A Novel Game Programming in GNU/LINUX”. Accepted for publication in Proceedings of the International Conference on Computer Games,Multimedia and Allied Technology (CGAT) 2010 55) Prasun Ghosal, Malabika Biswas, Manish Biswas: “A compact FPGA Implementation of Triple-DES Encrypton System with IP Core Generation and On-Chip Verification”. In Proceedings of the International Conference on Industrial Engineering and Operations management (IIEOM) 2010

56) Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta: “Uniform Thermal Distributions in Placement of Standard Cells and Gate Arrays: Algorithms and Results”. In Proceedings of IEEE VLSI Design and Test Symposium (VDAT) 2009: pp.69-78

57) Prasun Ghosal, Manish Biswas, Malabika Biswas: “A fast FPGA Implementation of the 8b/10b encoder and Decoder with IP core generation and On-chip verification”. In Proceedings of Conference cum Workshop on Information Security and Networks (ISAN) 2009: pp. 103-106

58) N. Das, P. Roy, D. K. Das and H. Rahaman, “Feedback Bridging Fault Detection in Cluster Based FPGA by Using Muller-C Element”, IEEE ICFCC 2009.

59 ) H. Rahaman, J. Mathew, and D. K. Pradhan, “C-testable S-box Implementation for Secure Advanced Encryption Standard”, 15th IEEE International On-Line Testing Symposium, 2009 (IOLTS 2009), pp.210 –

15

s211. 60) N. Das, P. Roy, and H. Rahaman, “Design of Run Time FPGA Router using JBits 3.0”, IEEE VLSI Design and Test Symposium, 2009, pp.114-123.

61) P. Ghosal, T. Samanta, H. Rahaman, and P. S. DasGupta, “Uniform Thermal Distributions in Placement of Standard Cells and Gate Arrays: Algorithms and Results”, IEEE VLSI Design and Test Symposium, 2009 pp.69-78. 62) M. Chanda, A. Dandapat, H. Rahaman, “Ultra Low-Power Sequential Circuit Implementation by a Quasi- Static Single Phase Adiabatic Dynamic Logic (SPADL)”, TENCON2009. 63) T. Samanta, H. Rahaman, and P. S. DasGupta, “Sub-optimal Y-routed Delay Trees with Multiple Sources”, Proceedings of ICIT 2009, pp.35-44. 64) Dipak K. Kole, H. Rahaman, D. K. Das, and B. B. Bhattacharya, “A Constructive Algorithm for Synthesis of Reversible Logic Circuits”, Proceedings of ICIT 2009, pp.23-28. 65) J. Mathew, H. Rahaman, and D. K. Pradhan, ‘De-Bruijn Graph Based Energy Efficient Routing in Multi- layered Architecture for Wireless Sensor Networks,’ ”, Proceedings of ICIT 2009, pp.295-302. 66) M.Chanda, A.Dandapat and H. Rahaman, “Implementation of Ultra Low-Power Sequential Circuit by a

Quasi-Static Single Phase Adiabatic Dynamic Logic (SPADL)”, CODEC 2009. 67) J. Mathew, A. Jabir, H. Rahaman and D. K. Pradhan, ‘A Performance Comparison of Different Concurrent EDC Schemes for S-box and GF(P),’ ISQED 2010. 68) Chandan Giri, Surajit Ray and H. Rahaman, “Scan Chain Design Targeting Dual Power and Delay Optimization for 3D Integrated Circuit”, ACT December 2009. 69) S. Pal, P. Bhowmick, A. Biswas and B.B.Bhattacharya. Understanding Digital Documents Using Gestalt

Properties of Isothetic Components. International Journal of Digital Library Systems (accepted), 2009. 70) A.Biswas, P. Bhowmick, Moumita Sarkar and B.B. Bhattacharya. A Linear-time Combinatorial Algorithm to

Find the Orthogonal Hull of an Object on the Digital Plane.(revision), December 2009. 71) A. Biswas, S. Pal, P. Bhowmick and B.B. Bhattacharya Geometric Analysis and Efficient Indexing of Digital

Documents. (revision), 2009. 72) S. Pal, P. Bhowmick, A. Biswas, and B.B.Bhattacharya. GOAL: Towards understanding of Graphic Objects from Architectural to Line drawings. In Proc. Eighth International Workshop on Graphics Recognition (GREC 2009), City University of La Rochelle, France, pages 71-82, 2009. 73) A.Biswas, Mousumi Dutt, P. Bhowmick and B.B. Bhattacharya. On Finding the Orthogonal Convex Skull of a Digital Object. In Proc. 13th International Workshop on Combinatorial Image Analysis: IWCIA’09, Research Publishing Services, Singapore, pages 25-36, 2009. 74) Sukanta Das, Biplab K Sikdar: A Scalable Test Structure For Multi-Core Chip. IEEE Transactions on CAD, Vol 29, No 1, pp 127-137, January 2010 75) Kalyan Mahata, Sukanta Das: Coordinator Selection in Distributed Systems: Cellular Automata Model Based Approach. World Congress on Nature and Biologically Inspired Computing (NaBIC'09), December 09-11, 2009, Coimbatore, India 76) Sukanta Das, Sukanya Mukherjee, Nazma Naskar, Biplab K Sikdar: Modeling Single Length Cycle Nonlinear Cellular Automata For Pattern Recognition. World Congress on Nature and Biologically Inspired Computing (NaBIC'09), December 09-11, 2009, Coimbatore, India 77) Sukanta Das, Biplab K Sikdar: CA Based Built-In Self-Test Structure for SoC. The 2009 IEEE Asian Test Symposium (ATS'09), Nov 23-26, 2009, Taichung, Taiwan. 78) Sukanta Das, Sukanya Mukherjee, Nazma Naskar, Biplab K Sikdar: Characterization of Single Cycle CA and Its Application in Pattern Classification. AUTOMATA 2009: 15th International Workshop on Cellular Automata and Discrete Complex Systems, Oct 10-12, São José dos Campos, SP, Brazil 79) Sukanta Das, Biplab K Sikdar: Characterization of 1-d Periodic Boundary Reversible CA. AUTOMATA 2009: 15th International Workshop on Cellular Automata and Discrete Complex Systems, Oct 10-12, São José dos Campos, SP, Brazil 80) Sukanta Das, Meghnath Saha and Biplab k Sikdar: A Cellular Automata Based Model for Traffic in Congested City. The 2009 IEEE International Conference on Systems, Man, and Cybernetics (SMC2009), Oct 11-14, 2009, Texas, USA.

81) Kalyan Mahata, Meghnath Saha, Sukanta Das: Cellular Automata Based Coordinator Selection Scheme in Distributed System. CSC 2009: 304-310

82) Sukanta Das, Nazma Naskar, Sukanya Mukherjee, Biplab K. Sikdar: CA Rules Identification for Efficient Design of Pattern Classifier. CSC 2009: 336-341

16

Seminar / Workshops / Conferences / Training programme organized by the department (2009)

Open Source Work Shop:- 3 days workshop July27-29, 2009 Organized by: Department of Information Technology, Bengal Engineering and Science University, Shibpur and Institute for Open Technology and Application (IOTA), a society under Dept. of IT, Govt. of West Bengal. Sponsored by: Institute for Open Technology and Application (IOTA), a society under Dept. of IT, Govt. of West Bengal.

Technology Developed/ Innovations

Patents: 1. T. Acharya, B. B. Bhattacharya, P. Bhowmick, A. Bishnu, A. Biswas, M. K. Kundu, C. A.

Murthy, S. Das, and S. C. Nandy. Minutia matching using scoring techniques. United States Patent No. 7,359, 532, issued on April 15, 2008.

2. Santi P. Maity, Malay K. Kundu, Bhargab B. Bhattacharya, C. A. Murthy and Tinku Acharya,

Robust digital image watermarking utilizing a Walsh transform algorithm, US Patent application filed on 11th December 2003, application no. 10/734,691, Attorney Docket No. 42P14995.

3. H. Rahaman, J. Mathew, and D. K. Pradhan, “Secure Testable S-box Architecture for

Cryptographic Hardware Implementation”, UK Patent application filed on 6th May 2009, reference number GB0907728.0

Copyrights: 1. Name: A software package titled “A Software Package for Thermal-aware Placement Routing for Standard Cells” Authors: Parthasarathi Dasgupta, Prasun Ghosal,Debashis Saha Applied to Ministry of HRD, Govt of India through DIT, Govt of India Date: Oct 21, 2009

Others Placements: 2009

Company Name WIPRO Tech

Mahindra ITC Infotec IBM Metalogic

Systems Eastern

speeding Mills

UG students 17 04 02 07 05 01 PG students 03 - - - 01 -

Students’ activities: Students organized Techfest “INSTRUO 09” during 2009.