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© 2005 Cabot Microelectronics Corporation
1
Innovation in ILD Polishing:Ultra-Low Defects andReduced CoO
June 2005
© 2005 Cabot Microelectronics Corporation
2
Discussion Topics
• Dielectrics Polishing Needs – Why Ceria?• General Polish Mechanisms• Factors Contributing to Cost of Consumables• Polishing Results
– Defects– Planarization
• Summary
© 2005 Cabot Microelectronics Corporation
3
Dielectrics Polishing Needs:iDiel™6600 Solution Development
• Market Needs (ILD)– Low Cost of Consumable per wafer
– Ultra-Low defectivity
– Similar Performance to Traditional Silica Based Slurries in Other Areas
– Stable, Predictable Performance
© 2005 Cabot Microelectronics Corporation
4
Ceria: The Misunderstood Abrasive
© 2005 Cabot Microelectronics Corporation
5
Ceria is not really a “hard” particle
Si
Si3N4
SiO2
Initial Wafer Surface
MohsHardness
6.5 – 7.0
9.0
ceria 6.0
© 2005 Cabot Microelectronics Corporation
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Ceria Is A Much More Efficient AbrasiveSilica System Ceria System
© 2005 Cabot Microelectronics Corporation
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Ceria vs. Silica Polishing Mechanisms
• Conventional Dielectric Polishing Mechanism– Silica Based Slurry
– Ceria Based Slurry
• New Chemistry Mechanisms on Dielectric Polishing for iDiel™6600– Rate Acceleration Mechanism
– Morphology of Ceria on Defectivity
© 2005 Cabot Microelectronics Corporation
8
Dielectric CMP Mechanism of Silica Based Slurry
Mechanical Abrasion Oriented• Fumed/Colloidal Silica Based Slurry:
– High abrasive concentration– Limited chemical contribution from high pH (dissolution)
Silica Surface
Si
-O
Si
O
Si
O
Si
OSi
Si
O
Si
O
HO
Si Si
Si
O
Si
OSi
Si
O
Si
O
OSi
OSi
HHHO
Si
HOH-
O --
---
- --
--
- ---
-
© 2005 Cabot Microelectronics Corporation
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+ +
+ ++ Ceria
Silica Surface
Si
-O
Si
O
Si
O
Si
OSi
Si
O
Si
O
HO
Si Si
Si
O
Si
OSi
Si
O
Si
O
OSi
OSi
HHHO
Si
HOH-
O
oxoanion
Particle Has Strong Chemical Interaction with Surface
Ceria Polishing Mechanism
© 2005 Cabot Microelectronics Corporation
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High Efficiency Rate Acceleration ChemistryCeria Rate Control Chemistry
0
500
1000
1500
2000
2500
3000
3500
Ceria Particle Ceria Particle with Rate ControlChemistry
PETE
OS
Rem
oval
Rat
e (A
/min
)
Higher Oxide Removal Rate with a Host of Rate Acceleration Molecules in Ceria SlurryMost Consistent Removal Rate with Chemistry Oriented Slurry
© 2005 Cabot Microelectronics Corporation
11
Impact of Abrasive Morphology on Defectivity
To Lower Defect CountRounded Edge and CornerNarrow Particle Size Distribution
Ceria A
Scale = 50 nmSmall, uniform particles
with rounded edges
Ceria B
Scale = 50 nmLarge, uncontrolled particles
with sharp edges
145
363
470
187
1
42
0
100
200
300
400
500
Ceria A Ceria B Ceria CD
efec
t Cou
nts,
patt
ern
waf
ers
0
40
80
120
160
200 Scratch Num
ber, pattern wafers
AIT Counts
Scratch Number
© 2005 Cabot Microelectronics Corporation
12
Semi-Sperse® 25E iDiel™6600
Abrasive Type
Chemistry
Particle Concentration(POU)
Ceria
High Purity (no KOH)Rate Control Additives
< 0.50%
pH ~ 11KOH
12.5%
Fumed Silica
MechanismBalanced Chemical
& MechanicalPrimarily
mechanical
Method of UseSingle Component
2X Concentrate Single Component
6X Concentrate
iDiel™ 6600 Comparison to Fumed Silica
© 2005 Cabot Microelectronics Corporation
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iDiel™ 6600 Comparison to Fumed Silica
Semi-Sperse® 25E iDiel™6600
Downforce
TEOS pattern RR
3 psi
6000 Å/min4700 Å/min
4 psi
BPSG/PSG defects (norm.) 0.2X (80% reduction)1X
TEOS defects (norm.) 1X 0.6X (40% reduction)
TEOS: SiN Selectivity 5:1 >50:1
© 2005 Cabot Microelectronics Corporation
14
iDiel™6600 Low Cost of Consumable
Semi-Sperse® 25E iDiel™6600
Dilution
Typical Flowrate
6X
125 mL/min150 mL/min
2X
Polish Time (8K step) <100 sec125 sec
$ for Transportation / Logistics + 33% Reduction inSlurry Usage per Wafer = CoC
© 2005 Cabot Microelectronics Corporation
15
Flow RateTime to
Planarize Slurry Usage
1 11
85%78%
66%
0%10%
20%30%
40%
50%
60%
70%
80%
90%
100%
iDiel 6600 TM Slurry Usage EfficiencyReduction in Slurry Usage per Wafer Pass measured on SKW 7 Wafers
iDiel 6600Fumed Silica Product
Nor
mal
ized
to F
umed
Sili
ca
~33% Reductionin Slurry Usage
iDiel™6600 Low Cost of Consumable
© 2005 Cabot Microelectronics Corporation
16
Defectivity Reduction with iDiel™6600
Ref ILD6X141
Defectivity Comparison (SP1 total counts)(PSG Blanket Wafers, Post HF)
01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Wafer Number
Def
ect C
ount
per
waf
er
DCODCN
Fumed Silica Slurry iDiel™6600 (Ceria)
© 2005 Cabot Microelectronics Corporation
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Example of Defect Classification by SEMVisonClass#25 : general micro-scratch
© 2005 Cabot Microelectronics Corporation
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Customer Validation of Microscratch Reduction
~ 50%Reductionon TEOS~ 80%
Reductionon PSG
Microscratch Count Comparison
0
Silica Based iDiel™6600Slurry Type
Mic
rosc
ratc
h C
ount
Per
Waf
er
PSGTEOS
© 2005 Cabot Microelectronics Corporation
19
Planarization Efficiency of iDiel™6600 vs. SS25E®
on MIT PatternOxide Thickness at 50% Pattern vs. 10% Field LossMirra, 2-platen process, IC1000/Suba-IV3/3/3.5/100/118
0
5000
10000
15000
20000
25000
0 1000 2000 3000 4000 5000 6000
10% Field Loss(Å)
Thic
knes
s at
50%
Site
(Å)
SS25EiDiel 6600
Equivalent Planarization Efficiency
© 2005 Cabot Microelectronics Corporation
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iDiel™6600 Removal Rate On MIT PatterniDielTM6600: Thickness of "UP AREA" vs Time
Mirra, 2-platen process, IC1000/Suba-IV3/3/3.5/100/118
0
5000
10000
15000
20000
25000
0 20 40 60 80 100 120 140 160
Time (sec)
Thic
knes
s (A
) at 5
0% S
ite
SS25EiDiel 6600
~ 25% Reduction in Polish Time
© 2005 Cabot Microelectronics Corporation
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Summary
• Innovation Can Drive CoC Reduction• Unique Ceria Abrasive Properties Key To Achieving
Metrics– High Efficiency Abrasive– Chemically Enhanced Mechanism– Low Defects– Low CoC