Institutionen för systemteknikDepartment of Electrical Engineering

Examensarbete

Design of an Input Multiplexer for VideoApplications

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan i Linköping

av

Pavel Angelov

LiTH-ISY-EX--10/4411--SE

Linköping 2010

Department of Electrical Engineering Linköpings tekniska högskolaLinköpings universitet Linköpings universitetSE-581 83 Linköping, Sweden 581 83 Linköping

Design of an Input Multiplexer for VideoApplications

Examensarbete utfört i Elektroniksystemvid Tekniska högskolan i Linköping

av

Pavel Angelov

LiTH-ISY-EX--10/4411--SE

Handledare: J Jacob Wiknerisy, Linköpings universitet

Examinator: J Jacob Wiknerisy, Linköpings universitet

Linköping, 11 June, 2010

Avdelning, InstitutionDivision, Department

Division of Electronics SystemsDepartment of Electrical EngineeringLinköpings universitetSE-581 83 Linköping, Sweden

DatumDate

2010-06-11

SpråkLanguage

Svenska/Swedish

Engelska/English

RapporttypReport category

Licentiatavhandling

Examensarbete

C-uppsats

D-uppsats

Övrig rapport

URL för elektronisk version

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-65530

ISBN

—

ISRN

LiTH-ISY-EX--10/4411--SE

Serietitel och serienummerTitle of series, numbering

ISSN

—

TitelTitle

Konstruktion av en Ingångsmultiplexer för VideotillämpningarDesign of an Input Multiplexer for Video Applications

FörfattareAuthor

Pavel Angelov

SammanfattningAbstract

In modern home entertainment video systems the digital interconnection betweenthe different components is becoming increasingly common. However, analog sig-nal sources are still in widespread use and must be supported by new devices.In order to keep costs down, the digital and the analog receiver chains are imple-mented on a single die to form a system-on-chip (SoC). For such integrated circuits,it is beneficial to reduce the number of power supply domains to a minimum andpreferably use the core voltage to power the analog circuits.

An eight-to-one input multiplexer, targeted for video digitizer applications,is presented. Together with the multiplexer, a simple current-mode DC restora-tion circuit is provided. The goal has been to design the circuits for a standard,single-well, 65 nm CMOS process, entirely using low-voltage core transistors anda single 1.1 V supply domain, while allowing the input signal voltages to extendbeyond the supply rails.

To fulfill the requirements, a bootstrap technique has been proposed for theimplementation of the multiplexer switches. Bootstrapping a CMOS switch allowshigh linearity, as well as wide bandwidth and dynamic range, to be achieved witha very low supply voltage. The simulated performance is: 3-dB bandwidth of536 MHz with a 1.5 pF load at the output of the multiplexer and a SFDR of65 dBc at 20 MHz and 1 Vp-p input signal. It has been verified that no transistoris stressed by high voltages, therefore, the circuit reliability is guaranteed. TheDC restoration circuit utilizes the main video ADC, for measuring the DC level,and is capable of setting it with an accuracy of 60 µV within the range of 100 mVto 500 mV.

NyckelordKeywords analog video, AFE, bootstrap, analog multiplexer, analog switch, leakage current,

DC restoration, DC clamp, sub-micron CMOS

AbstractIn modern home entertainment video systems the digital interconnection betweenthe different components is becoming increasingly common. However, analog sig-nal sources are still in widespread use and must be supported by new devices.In order to keep costs down, the digital and the analog receiver chains are imple-mented on a single die to form a system-on-chip (SoC). For such integrated circuits,it is beneficial to reduce the number of power supply domains to a minimum andpreferably use the core voltage to power the analog circuits.

An eight-to-one input multiplexer, targeted for video digitizer applications,is presented. Together with the multiplexer, a simple current-mode DC restora-tion circuit is provided. The goal has been to design the circuits for a standard,single-well, 65 nm CMOS process, entirely using low-voltage core transistors anda single 1.1 V supply domain, while allowing the input signal voltages to extendbeyond the supply rails.

To fulfill the requirements, a bootstrap technique has been proposed for theimplementation of the multiplexer switches. Bootstrapping a CMOS switch allowshigh linearity, as well as wide bandwidth and dynamic range, to be achieved witha very low supply voltage. The simulated performance is: 3-dB bandwidth of536 MHz with a 1.5 pF load at the output of the multiplexer and a SFDR of65 dBc at 20 MHz and 1 Vp-p input signal. It has been verified that no transistoris stressed by high voltages, therefore, the circuit reliability is guaranteed. TheDC restoration circuit utilizes the main video ADC, for measuring the DC level,and is capable of setting it with an accuracy of 60 µV within the range of 100 mVto 500 mV.

v

Acknowledgments

The person who deserves most gratitude for the completion of this thesis workis my supervisor and examiner Dr. J Jacob Wikner, he has provided me withthe opportunity to prepare my thesis work in the division of Electronics Systems.Work and discussions with him have always been inspiring and highly motivat-ing. Dr. Wikner, you have guided me through the thesis work in a superb fash-ion. Thanks!

I am also thankful to Joakim Alvbrant for the help with the tools, and to every-body who worked in the mixed-signal thesis group, for the general discussions andsupport. Thanks also go to Yasir Ali Shah for opposing at the thesis presentationand providing valuable feedback for this report.

I am thankful to my friend Martin Tapankov for suggesting many correctionsand improvements to the text and formating of this report, as well as for thenumerous technical discussions.

I thank my girlfriend and life partner Valentina for the support and for thelove, she also helped reviewing and proof-reading the final text of this report.

I owe never-ending gratitude to my parents who have always supported meunconditionally and for loving me. Without you none of this would have beenpossible. Thank you!

vii

Contents

1 Introduction 31.1 Purpose and goals . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Project scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.3 Target CMOS process description and features . . . . . . . . . . . 41.4 Video digitizer overview . . . . . . . . . . . . . . . . . . . . . . . . 41.5 Analog video signals . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.5.1 Monochrome video . . . . . . . . . . . . . . . . . . . . . . . 61.5.2 Color video . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.5.3 Voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . 91.5.4 Signal coupling and termination . . . . . . . . . . . . . . . 10

2 Analog Multiplexers and Switches 132.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 The MOS transistor as a switch . . . . . . . . . . . . . . . . . . . . 14

2.2.1 Transmission gate . . . . . . . . . . . . . . . . . . . . . . . 152.2.2 Bootstrapping techniques . . . . . . . . . . . . . . . . . . . 17

2.3 The implemented analog switch . . . . . . . . . . . . . . . . . . . . 182.3.1 Bootstrapped switch—principle of operation . . . . . . . . . 18

3 DC restore block 213.1 The need for DC restoration . . . . . . . . . . . . . . . . . . . . . . 213.2 Voltage-mode DC clamp . . . . . . . . . . . . . . . . . . . . . . . . 233.3 Current-mode DC clamp with current sources . . . . . . . . . . . . 243.4 Current-mode DC clamp without current sources . . . . . . . . . . 25

3.4.1 The implemented DC clamp . . . . . . . . . . . . . . . . . . 26

4 Analog Multiplexer - performance metrics 294.1 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.2 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.3 Inter-channel isolation . . . . . . . . . . . . . . . . . . . . . . . . . 314.4 Clamp circuit performance metrics . . . . . . . . . . . . . . . . . . 314.5 Leakage and lower cut-off frequency . . . . . . . . . . . . . . . . . 32

ix

x Contents

5 Design Details 355.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355.2 Bootstrapped switch . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.2.1 Special design considerations . . . . . . . . . . . . . . . . . 365.2.2 Switch linearity and bandwidth . . . . . . . . . . . . . . . . 395.2.3 Bootstrap charge retention . . . . . . . . . . . . . . . . . . 415.2.4 OFF-state resistance and isolation . . . . . . . . . . . . . . 43

5.3 DC restoration circuit . . . . . . . . . . . . . . . . . . . . . . . . . 445.3.1 Control signals and actual implementation . . . . . . . . . . 48

5.4 Multiplexer topology and top-level design . . . . . . . . . . . . . . 485.4.1 Design considerations and transistor sizing . . . . . . . . . 49

6 Test bench and simulation results 516.1 Test bench design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516.2 Simulated performance parameters and results . . . . . . . . . . . 53

6.2.1 Internal voltage levels . . . . . . . . . . . . . . . . . . . . . 53

7 Conclusion 57

8 Future work 59

Bibliography 61

A VerilogA code of the binary-to-thermomenter encoder 63

B VerilogA code of the video signal generator 65

List of Figures1.1 Block diagram of the video analog-front-end integrated circuit. . . 61.2 Electron beam scanning on a CRT screen. . . . . . . . . . . . . . . 71.3 Analog video signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.4 AC coupling of an analog video signal. . . . . . . . . . . . . . . . . 10

2.1 Functional diagram of an analog multiplexer. . . . . . . . . . . . . 132.2 Model of a real closed switch with parasitic elements. . . . . . . . . 142.3 A single transistor analog switch. . . . . . . . . . . . . . . . . . . . 152.4 Transmission gate realization of an analog switch. . . . . . . . . . . 162.5 Transmission gate on-resistance . . . . . . . . . . . . . . . . . . . . 162.6 Conceptual schematic of a bootstrapped switch. . . . . . . . . . . . 172.7 Detailed schematic of the bootstrapped switch presented in [2] . . 192.8 Topological diagram of the bootstrapped switch . . . . . . . . . . . 202.9 Bootstrapped switch clocks . . . . . . . . . . . . . . . . . . . . . . 20

3.1 AC coupling signal effects . . . . . . . . . . . . . . . . . . . . . . . 223.2 AC coupling with DC restoration. . . . . . . . . . . . . . . . . . . 223.3 Voltage-mode DC restoration. . . . . . . . . . . . . . . . . . . . . . 233.4 Current-mode DC restoration. . . . . . . . . . . . . . . . . . . . . . 243.5 Current-mode clamp closed-loop . . . . . . . . . . . . . . . . . . . 253.6 Realization of the controlable current source. . . . . . . . . . . . . 25

4.1 Effect of bandwidth limitation of the video signal. . . . . . . . . . 304.2 Effect of non-linear distortion of the video signal. . . . . . . . . . . 314.3 Effect of unstable DC clamp. The brightness is varied by 5%. . . . 324.4 Effect of leakage current through the input capacitor. . . . . . . . 32

5.1 Bootstrapped switch—original schematic . . . . . . . . . . . . . . . 365.2 Bootstrapped switch—Harmful input current . . . . . . . . . . . . 385.3 Bootstrapped switch—final schematic . . . . . . . . . . . . . . . . 395.4 Bootstrapped switch—non-linear capacitances . . . . . . . . . . . . 405.5 Bootstrap leakage currents . . . . . . . . . . . . . . . . . . . . . . 425.6 T-switch arrangement . . . . . . . . . . . . . . . . . . . . . . . . . 435.7 5-bit charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . 445.8 The DC restore circuit as a digital control loop . . . . . . . . . . . 455.9 Clamp charge pump transfer characteristic . . . . . . . . . . . . . . 475.10 Multiplexer switch final . . . . . . . . . . . . . . . . . . . . . . . . 495.11 Multiplexer—final architecture . . . . . . . . . . . . . . . . . . . . 50

6.1 Complete Multiplexer test bench . . . . . . . . . . . . . . . . . . . 52

2 Contents

List of Tables1.1 Available CMOS transistors . . . . . . . . . . . . . . . . . . . . . . 51.2 Video voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1 Simulated performance parameters . . . . . . . . . . . . . . . . . . 546.2 Simulated stress results . . . . . . . . . . . . . . . . . . . . . . . . 55

Chapter 1

Introduction

The objective of this thesis is to design an input analog multiplexer to be used invideo digitizer applications and in a video analog-front-end integrated circuit (AFEIC) designed at the division of Electronics Systems, Linköping University. Thedesign must be implemented in a low-voltage, “digital” CMOS process with asmany components as possible brought down to layout level.

The multiplexer, designed in this thesis work, is an 8-to-1 multiplexer incor-porating a DC restoration circuit (clamp) for setting the DC level of the incom-ing video signal. The key performance measures are high linearity (more than60 dB at 20 MHz), high bandwidth (more than 500 MHz) and low crosstalk (lessthan -70 dBc).

With the development of digital electronics, “digital” video formats, like DVI,HDMI and even video-over-USB, are becoming increasingly widespread. However,due to their historical usage, the analog video signaling formats are supprotedby virtually all video devices in use today. Many digital devices, like personalcomputers, home entertainment video systems, TV sets, and even some photocameras and MP3 players, support only analog video signaling. This means thatin new devices analog video support must be availabe in parallel with the digitalformats. In today’s highly integrated systems it is absolutely necessary to havethe functionality for both analog and digital video formats on the same chip.Therefore, to take advantage of the modern CMOS processes, the analog partsmust be designed using unconventional techniques, thus avoiding the problemsintroduced by the deep sub-micron CMOS technologies.

1.1 Purpose and goalsThe following goals and tasks were set as guidelines for the project execution:

• Design and verify a multiplexer together with a DC restoration circuit, aswell as an analog filter for limiting the bandwidth of the low-resolution videoformats. Cover the performance requirements defined in the project designspecifications.

3

4 Introduction

• Aim the design towards applications with low supply voltage and low powerconsumption, possibly operated from a battery.

• Use digital circuit techniques as much as possible in order to facilitate scal-ability with future CMOS technologies and to make the realization in sub-micron CMOS processes feasible.

• Design the components such that as many as possible analog video formatsare supported in the final digitizer integrated circuit.

1.2 Project scopeEven though the project is aimed at designing a fully functional video multiplexerit is not concerned with the implementation of the accompanying digital controlblocks. The intention is to provide those parts of the multiplexer that directlyinteract with the analog signals, but leave the control strategy open for furtherdevelopment. However, some of the interfacing digital logic is provided, but itshould not be considered optimal.

The project implementation is limited by the constraints that the video AFEhas, in terms of IC manufacturing process, available power supply, supportedvideo formats and design specifications and goals. The actual specifications willbe discussed later in the appropriate chapters.

1.3 Target CMOS process description and fea-tures

The semiconductor process, that the video AFE is designed in, is a state-of-the-art65 nm, n-well process with seven metal and one poly layers.

The process provides a multitude of devices. There are two major transistortypes—high-voltage, thick-oxide MOS transistors for a nominal supply voltage of2.5 V, and low-voltage, thin oxide MOS transistors for a nominal supply voltageof 1.1 V. The two transistor types have two flavors each—general purpose (gp),and low power (lp). The low power transistors have thicker gate oxides to providelow gate leakage currents for non-speed critical circuit parts. The transistorshave three threshold voltage options - high, standard and low Vt. The availabletransistors with their main features are summarized in table 1.1.

As the design of the chip is targeted towards low power supply voltages andlow power consumption only low voltage devices are used. This also lowers thecost since separate manufacturing steps are required for the high and low voltagedevices.

1.4 Video digitizer overviewThe designed multiplexer is a part of a large integrated circuit, a video digitiz-ing device, where it is used to select the active analog input. Since the digitizer

1.5 Analog video signals 5

Transistordesignation

Description Gate leakage Drain-Sourceleakage

hvtlp high-Vt,low power

low low

svtlp standard-Vt,low power

low medium

lvtlp low-Vt,low power

low high

hvtgp high-Vt,general purpose

high low

svtgp standard-Vt,general purpose

high medium

lvtlgp low-Vt,general purpose

high high

Table 1.1: Transistor types available from the target CMOS technology

stands at the boundary of the analog and digital domains it is also termed analog-front-end (AFE). The architecture of the video AFE is shown in figure 1.1 and isseparated in two major blocks. The digitizing channel consists of an input mul-tiplexer together with a DC restoration circuit, a low-pass filter, a programablegain amplifier (PGA) and an analog-to-digital converter (ADC) which digitizesthe video signal. This is followed by a digital post-processing block which per-forms gain and error correction. In order to cover all supported video formats fivedigitizing channels are used in parallel.

The timing block processes the synchronization information in the video signal(either embedded sync pulses or separate synchronization signal) and extracts thetiming information needed to control the digitizing channel. The input signal isfed to a multiplexer, which selects the source of the synchronization signal, thento a phase-locked-loop (PLL) which aligns its output to the input synchronizationsignal, but at a higher frequency corresponding to the pixel rate. The delay-locked-loop (DLL) is used to time-shift the rising edge of the clock produced bythe PLL so that the position at which the video signal is sampled can be preciselycontrolled and selected, thus allowing under-sampling to be utilized.

The AFE also incorporates a digital control block, which programs the op-eration of the different parts: video input and sync input selection, PGA gain,PLL multiplication factor and DLL phase. The video multiplexer, in particular,receives control signals for input selection, clamp activation and clamp voltage.

1.5 Analog video signalsOriginally analog video was designed for the monochrome broadcast TV. Thecathode-ray-tube (CRT) was the only device available for video output in theearly TV sets, so the video signal format was, naturally, meant for display on

6 Introduction

Clamp

Filter

Designed blocks

PGA

Bias ADC ReferenceGenerator

Digital signalprocessingGain correctionOffset correctionSagcompensation/Clamp

5 x DIGITIZING CHANNEL

Control

DLL

DLL

PLL

DLL

Slicer

Slicer27-MHz Oscillator(RC type)

Power-on reset (POR)

Digital signalprocessingSync detectionClock dividersRegisters

Bandgap reference

Current and volatge reference

Mult

iple

xer

2 x TIME/REFCHANNEL

MainVideoADC

Mult

iple

xer

Figure 1.1: Block diagram of the video analog-front-end integrated circuit.

a CRT screen. This largely determines what “features” the analog video signalincorporates.

1.5.1 Monochrome videoThe image on a CRT is formed by sweeping an electron beam over the back surfaceof the screen [1], starting from the top-left corner and continuing, line by line, tothe botom end. After drawing a complete line, the electron beam is “swept” backto the left to start drawing the next line. After a whole frame has been drawn thebeam is swept to the top-left corner and the display of the next frame begins. Thisprocess is shown in figure 1.2. The sweeping of the beam to the left and to the topis called horizontal and vertical retrace, respectively. Actually, to save bandwidth,in the TV formats the image is not displayed progressively, line-by-line, but isinstead scanned odd lines first and then, on the next vertical retrace—even lines,this is called interlaced video.

1.5 Analog video signals 7

The tracing motion of the electron beam is controlled by the video signal. Aportion of a signal representing one line of video is shown in figure 1.3. The hor-izontal scan starts slightly outside the visible area of the screen, this correspondsto the part of the video signal, called back porch, where the signal is kept at a level

Back Porch Front Porch

Active Video

Horizontal retrace pathVertical retrace path

Scan lines

Act

ive V

ideo

Figure 1.2: Electron beam scanning on a CRT screen.

Syncpulse

Back porch Front porch

Blankingpulse

0%

25%

50%

100%

Next line

Time

Am

plit

ud

e

75%

High detailregion

Figure 1.3: Analog video signal representing one line of a monochrome video frame.

8 Introduction

corresponding to the color black. After that the actual image line is displayed, thisportion of the signal is called active video. The voltage of the active video portionof the signal carries the color and brightness information of the pixel correspondingto the position of the beam at the particular instant of time. At the end of theline the signal is again blanked (brought to a level corresponding to black) andthe beam is brought out of the visible screen area. This part of the video signal iscalled front porch. The horizontal retrace is controlled by a very important part ofthe video signal, following the front porch—the horizontal synchronization (hsync)pulse. During the hsync pulse the beam is brought back to its initial position, atthe left of the screen and then released to display the next line. The length of thehsync pulse is long enough so as to allow the CRT control circuitry to settle. Thevoltage level of the sync pulse corresponds to a blacker-than-black color, so thatthe retrace period is not visible on the screen.

After the whole image is displayed, a pulse similar to the hsync pulse, calledvertical synchronization, or vsync pulse occurs in the video signal and the beamis returned to the top left corner of the screen.

1.5.2 Color video

So far, we have only discussed the case where just a singel color is to be displayed.In order to represent color video three separate signals are required—one for red,one for green and one for blue, or RGB. These three base colors are combinedon the screen to form the original colors of the image. Despite of that, the basicprinciple of drawing the image on the screen remains the same.

The need of three separate colors means that three times the number of cables,or three times the bandwidth, of the monochrome signal are required to transmitcolor video. To solve this problem several signaling (RGB, Y PbPr, composite) andencoding (PAL, SECAM and NTSC) techniques were developed to represent thecolors so that less cables/bandwidth are needed. However, any operation on theoriginal RGB video signal deteriorates the image quality.

The first step in limiting the bandwidth is the color difference representation ofthe original RGB signal. This is merely a transformed color space called Y PbPr.It is again formed by three signals, the luma Y carries the brightness (the meanvalue of the red, green, and blue), PB is the difference between the original blueand luma, and PR is the difference between the original red and luma. The greencolor can then be derived from the recovered blue and red and the original lumasignals. The Y PbPr still requires three cables to send the video, but due to theproperties of the human eye, which is more sensitive to variations in brightnessthan to variations in color, the color signals can be filtered to half the bandwidthof the luma signal. The synchronization and blanking information is overlaid ontop of the luma signal.

To limit the required number of wires, the color difference signals are usedto modulate a color subcarrier, the resulting signal is called chrominance. Thisreduces the required number of wires to just two: one for luma and one for chromi-nance. This type of video signaling is called S-Video. The luma and chroma signalscan be combined into just one signal to form a signal called composite video, which

1.5 Analog video signals 9

Video format Active video Sync Peak amplitudeRGB 700 mV – 700 mV

RGB sync–on–green 700 mV -300 mV 1 VY PbPr

(PAL)luma 700 mV -300 mV 1 Vchroma 700 mV – 700 mV

Y PbPr

(NTSC)luma 714 mV -286 mV 1 Vchroma 1009 mV – 1.009 V

S-video(PAL)

luma 700 mV -300 mV 1 Vchroma 885.1 mV – 885.1 V

S-video(NTSC)

luma 714 mV -286 mV 1 Vchroma 835 mV – 0.835 V

Composite video (PAL) 933.85 mV -300 mV 1.234 VComposite video (NTSC) 934.15 mV -286 mV 1.220 V

Table 1.2: Voltage levels for the different video formats. Blanking level is assumedto be 0 V in all cases.

is used in terrestrial television broadcast and in home video entertainment systems.The more the original RGB signal is processed the more quality and resolution

is lost. This is the reason why different video systems stop processing the signalat different stages. Computer graphics and some high quality home entertainmentsystems directly use the RGB or Y PbPr (also called component) video signals.S-video and component video are used in TV sets, DVD players, set-top boxes,etc.

1.5.3 Voltage levels

The information in the analog video is carried both in the value and in the time/-position of the signal. For PC graphics systems, using RGB signaling, the peak-to-peak voltage level is defined to be either 0.7 Vp-p, when the sync is a separatesignal, or 1 Vp-p when the sync is embedded in the green signal (termed sync-on-green). Since the input multiplexer is only required to preserve the signal, thedetails of the voltage levels of the different parts of the video signal for the othervideo formats and encoding techniques are not of a particular interest for the de-sign of the video multiplexer. What is important are the maximum peak-to-peakvoltages that occur and the video blanking level. Table 1.2 lists these parametersfor the different video signaling and encoding formats.

As the video AFE is targeted towards low-voltage design, the power supplyvoltage available for the input multiplexer is specified to be only 1.1 V, meaningthat the signal levels that are to be switched are actually higher than the supplyvoltage. It is a major challenge to handle signals larger than the supply voltagein CMOS circuits and proved to be the main problem in designing the videomultiplexer circuitry.

10 Introduction

1.5.4 Signal coupling and termination

Video signals can be both DC or AC coupled between devices. DC couplingmeans that the input DC level of the receiving device is defined by the output ofthe previous device. This means that the two devices must be designed to operatewith the same common-mode level and that the ground reference be kept at thesame potential at both ends. The existence of DC path means that dangerous DCcurrents may flow between devices powered by different power supplies. This isthe case, for example, in a home entertainment system where the TV set and theset-top box are powered separately. DC coupling is usually utilized within one andthe same system where the common-mode levels are well defined.

Systems, designed to accept signals from different sources, must be AC coupledso that the common-mode level of the receiving end is well defined. To stop theDC component, a capacitor is placed in series with the signal path, as illustratedby figure 1.4. Thus, in order to achieve optimal performance, the two devices canset their own common-mode level at both sides of the input capacitor.

−

+

DCClamp

On-chip

Receiving device

Sending device

Figure 1.4: AC coupling of an analog video signal.

AC coupling introduces some problems as well. The receiving end must providethe means of setting the DC level at its input, leading to an increase of the requireddie area due to the additional circuitry. Since the video signal bandwidth extendsto very low frequencies (the vsync frequency is at the order of 60 Hz), hence,in order to preserve the integrity of the signal, the coupling must not introducesignificant attenuation. If the input resistance seen at the receiving device, afterthe input capacitor, is too low, the voltage on the capacitor will tend to trackthe mean level of the video signal. This effect (termed sag) causes variations ofthe brightness level at different parts of the picture. Circuits used for setting theDC level are called DC restoration, or DC clamp circuits. The clamp is, usually,activated only during the sync pulses or part of the back porch, so that the changein signal level is not visible on the screen.

Video signals are usually sent over 75–Ω cables, which are terminated at bothends to avoid reflections. To save board space, some low-cost manufacturers donot provide the termination at the receiving end, this causes the voltage levels,

1.5 Analog video signals 11

seen at the input, to double. A non-mandatory design requirement, to supportdouble input levels, has been put for the input multiplexer, so this also has beeninvestigated during the design process.

Chapter 2

Analog Multiplexers andSwitches

2.1 Introduction

The main objective of this thesis is to design an analog multiplexer—a device usedto select one-out-of-n inputs. Analog here refers to the continuous nature of theinput signals that are to be switched/processed, not to the actual implementationof the internal schematics of the multiplexer.

Vout

Vin1

Vin2

Vin3

S1

S2

S3

VinNSn

Figure 2.1: Functional diagram of an analog multiplexer.

The functional diagram of an analog multiplexer is shown on figure 2.1. It iscomposed of n switches with one of their terminals connected together and servingas an output of the multiplexer, while the other terminal—serving as an input. Atany instant of time only one of the switches Si is closed, while the rest are open.The output voltage is, thus, equal to the voltage at the input corresponding tothe closed switch, while the signals on the inputs with their switches open, ideally

13

14 Analog Multiplexers and Switches

have no effect on the output signal.Obviously, the main building block of an analog multiplexer is the analog

switch, thus its performance largely determines the performance of the multi-plexer as a whole. Ideally, when closed (on-state), the switch should present ashort-circuit and when open—infinite impedance. In practice, however, this is notthe case and the switches present (small) resistance when on and a small currentflows through the switches that are open (off-state). Furthermore, there existscapacitance present between the two terminals of the switch (shunt capacitance)and between each terminal and ground, this is shown on figure 2.2. The outputcapacitance, combined with the finite on-state resistance, limits the bandwidth ofthe switch, while the shunt capacitance deteriorates the off-state isolation at highfrequencies.

S1

Vout

Ron

CoutCin

Vin

Cshunt

Real Switch

Figure 2.2: Model of a real closed switch with parasitic elements.

Due to the analog nature of the video signals, it is of primary importance thatthe multiplexer does not introduce non-linear distortion. This is especially true foranalog video where the color and brightness information are stored in the signalamplitude. In a practical CMOS implementation of a multiplexer, the main sourceof non-linearity is the dependence of the on-state resistance on the input voltage.Therefore; most of the multiplexer design time was devoted in achieving linear(enough) behavior of the switches.

It must also be noted that the switching speed between the different inputsdoes not need to be done with high speed, nor is the switching required to beglitch-free.

2.2 The MOS transistor as a switchThere are several approaches to implement analog switching behavior in a CMOScircuit. It is possible, for example, to turn off the bias current of an amplifier, effec-tively stopping the propagation of the input signal to the output. This approachis, however, considered too analog and was not investigated further.

The simplest electronic switch, that can be implemented in CMOS technology,is a single MOS transistor, with the drain and source terminals acting as the two

2.2 The MOS transistor as a switch 15

terminals of the switch and the gate as the control input. This arrangement isshown on figure 2.3, where an NMOS transistor has been chosen. From basic

Vin

Vout

Vin

Vcontrol

Vout

Figure 2.3: A single transistor analog switch.

device physics, it is known that the first order approximation of the drain currentof a NMOS transistor, operating in linear region with VDS < (VGS − VTH), is:

ID ≈ µnCoxW

L(VGS − VTH)VDS (2.1)

That is, if the gate voltage is kept constant, the drain current varies linearlywith the source (input) voltage. This represents a non-linear resistance seen inthe signal path, and hence causes significant distortion. Furthermore, if the inputvoltage becomes higher than VG − VTH the transistor cuts off and the outputwaveform is clipped. This limits the available input signal range and makes thecircuit particularly unsuitable for low-voltage CMOS technology implementation.For our design case the gate can be kept at the supply voltage of 1.1 V and sincethe threshold voltage of the transistors is about 250 mV the usefull signal range islimited to about 750 mV. A rather small value, only suitable for the low voltageswing signals like RGB .

2.2.1 Transmission gate

A significant improvement over the single transistor switch can be achieved by con-necting two transistors with different conductivity (NMOS and PMOS) in parallel,this is shown on figure 2.4. The dependace of the on-state resistance of the twotransistors on the input voltage is approximately the same, but with an oppositesign. That is, when the input voltage increases the NMOS resistance increaseswhile the PMOS resistance decreases and vice versa. Also, when one of the tran-sistors enters the cut-off region the other one continues to conduct, significantlyextending the useful signal range of the circuit. The variation of the resistance forboth transistors as well as the combined resistance of the parallel connection as afunction of the input voltage is illustrated in figure 2.5. It is seen that the totalresistance of the switches remains approximately constant.

16 Analog Multiplexers and Switches

Vin

Vout

Vin

Vout

Vcontrol

Figure 2.4: Transmission gate realization of an analog switch.

Signal Voltage

RON

NMOSPMOS

Resistanceof the parallelcombination

- +

Figure 2.5: Dependence of the on-resistance of MOS transistors and their parallelcombination on the applied gate-source voltage.

2.2 The MOS transistor as a switch 17

The smallest resistance variation is achieved when the PMOS transistor is sizedsuch that the electrical size of the two transistors is approximately the same. Suchmatching, however, is difficult to achieve in sub-micron CMOS technologies, whichare characterized with significant device variations, hence large non-linear distor-tions would occur across process corners. Furthermore device matching techniquesare considered to be too “analog” and therefore do not fit well within the “digital”design philosophy adopted for this project.

2.2.2 Bootstrapping techniques

We have seen that the main source of non-linearity of the transistor switches comesfrom the variation of the on-resistance caused by the variation of the gate-sourcevoltage. Bootstrapping is a technique with which the gate-source voltage is keptapproximately constant throughout the voltage range of the input signal. Thisis achieved by connecting a pre-charged capacitor (termed bootstrap capacitor)between the gate and source terminals of the pass transistor. The bootstrap capac-itor is pre-charged to the supply voltage during the off-state and then connectedto the pass transistor through a separate set of switches. With this arrangementthe gate voltage follows the source voltage with a DC offset equal to the capacitorvoltage. Figure 2.6 shows the concept of the bootstrapping technique. The switchis turned off by simply connecting the gate of the main switch to ground.

Vin

Vout

Vboot

Cboot PassTransistor

Figure 2.6: Conceptual schematic of a bootstrapped switch.

Bootstrapping the gate of the switch transistor largely eliminates the variationof the on-resistance due to variation of the gate-source voltage. However, due tothe body effect the on-resistance still depends on the source voltage. This effect canbe compensated by bootstrapping the bulk of the pass-through transistor as well.However, for a typical CMOS process, the bulk terminals of NMOS transistors arenot separately accessible, therefore, PMOS devices must be used instead. Circuitsthat compensate for the body effect by bootstrapping the bulk have been proposedin [3] and [4].

Since the gate potential of the bootstrapped switch in the on-state is equal tothe sum of the input and the supply voltages, special attention must be payed to

18 Analog Multiplexers and Switches

the devices connected to that node so that circuit reliability is not compromised.The constant G-S voltage achieved by the bootstrapping technique means that

the on-resistance is almost independent of the ratio between the supply and theinput voltages, allowing the bootstrapped switch to be used for signal voltagesthat go beyond the supply rails. This makes the bootstrapped switch the perfect(if not the only) candidate for implementation of the video multiplexer, thus ithas been selected for realization.

2.3 The implemented analog switch

Several circuits, proposed in [2], [3] and [4], have been considered for the implemen-tation of the bootstrapped switch. The circuits described in [3], despite promissinggood performance, were excluded from consideration for implementation due tothe fact that they are protected by patents.

The bootstrapped circuit suggested by Waltari et al. in [4] compensates forthe harmful body-effect and can be implemented in a standard, single-well CMOStechnology. This is made possible by the use of a PMOS device with a boot-strapped bulk as the main switch. Special arrangement of the auxiliary switchesis necessary in that case in order to accommodate the large negative voltages thatoccur at the bootstrapped nodes. Due to the supposed high performance thiscircuit has been selected for realization and further assessment.

Another circuit implementing the bootstrapping technique which utilizes aNMOS as the pass-transistor is suggested by Lillebrekke et al. in [2]. This circuitis significantly simpler than the one from [4] and despite the supposedly poorerperformance due to the body effect has also been considered for implementation.

The two selected circuits have been implemented in the target CMOS processand their behavior has be simulated. It was discovered that for comparable siz-ing, and despite the improved variation of the on-resistance, the circuit utilizing aPMOS switch showed much worse performance in terms linearity and bandwidth.This can be explained by the inherently higher on-resistance of the PMOS tran-sistor which limits the bandwidth and linearity of the switch as whole. It shouldbe noted that in the case of the multiplexer the capacitance seen at the outputnode is significant (at the order of 2 pF), therefore, high on-resistance cannot betolerated. Also, the output capacitance has a largely non-linear behavior causedby the junction capacitance introduced by the switches in the off-state.

Due to the above reasons the bootstrapped switch in [2] has been selected forthe actual implementation and for detailed analysis. The complete circuit of theswitch, as originally presented in [2], is shown in figure 2.7.

2.3.1 Bootstrapped switch—principle of operation

The topological diagram of the circuit from figure 2.7 is shown in figure 2.8. Theoperation is based on two non-overlapping clock/control signals, shown in figure2.9. When clk1 is high and clk2 is low the gate of the pass transistor is groundedthrough S5 and the switch is in the off-state, also S3 and S4 are closed and the

2.3 The implemented analog switch 19

bootstrap capacitor Cboot is charged to the supply voltage difference. In the on-state the bootstrap capacitor is connected through S1 and S2 to the source andgate terminals of the pass transistor turning it on. The non-overlapping nature ofthe clocks prevents the bootstrap capacitor from discharging during the transitionbetween the on and off states. In the on-state the potential between the gateand the source is approximately constant and equal to the capacitor pre-chargevoltage.

The circuit in figure 2.7 is a direct implementation of the discussed topology.Transistors N3 and P4 implement S3 and S4 respectively, while transistors N1 andP2 – S1 and S2. When the current through the pass transistor changes directionthe role of its terminals swaps, this requires the use of N8 which compensates forthis effect and allows node A to more precisely track the potential of the terminalacting as the source. For high input voltage levels the potential at node B maybecome higher than Vdd which requires the transistors connected to that node tobe of PMOS type so that they can conduct reliably. It is not possible to turn ontransistor P2 by simply connecting its gate to ground as voltages exceeding thegate oxide breakdown limit may appear between its gate (ground) and source (nodeB). Therefore, in order to to turn on P2 the voltage of the bootstrap capacitor isused, this is achieved by transistors N6 and NS6. The dummy transistor PD isused to compensate for the charge injection due to P7 at node E. Transistors N5and NS5 implement S5. When the voltage at the gate of the main switch reachesapproximately the supply voltage, transistor NS5 cuts off and limits the voltageat node Q to a safe level.

VddswOFF

NS5 N5

Vout

SWG

DS

Vin

ChrgHI

A

N3

N8 N1 N6

NS6

ChrgLO

P2

B

P4

P7

Vdd

Cbootstrap

ChrgLO

ChrgLOND

Figure 2.7: Detailed schematic of the bootstrapped switch presented in [2]

20 Analog Multiplexers and Switches

Vout

Vin

Vss Vdd

CLK1

CLK2

Cboot

S1 S2

S3 S4

S5

A B

Vss

CLK2

CLK2

CLK1

SW

Figure 2.8: Topological diagram of the bootstrapped switch

clk1

clk2

Figure 2.9: Non-overlapping control signals used with the bootstrapped switch

Chapter 3

DC restore block

As discussed before, in most analog video systems the external input signals areAC coupled in order to provide protection against dangerous DC currents andto allow each device to set its own common mode level. By specification theexternal connections of the designed video AFE are AC coupled as well and thefirst block in the signal path, the input multiplexer, must provide the means toset the DC level. In this chapter we discuss the different implementations of theDC restoration block, their advantages and disadvantages and the reasons why aparticular implementation is suitable for the video AFE or not.

3.1 The need for DC restoration

A typical AC coupling of a video signal into a processing device is shown in figure3.1, where Rin represents the input impedance of the device. For this arrangement,the coupling capacitor stores the average value of the input signal, as well as thedifference in the DC level of the signal source and the device input bias level. Forsystems that process zero-mean signals, such as audio, this is not a problem as thebias level is well defined. However, the video signal average level is strongly depen-dent on the image content, this causes the DC level after the coupling capacitor tovary. Figure 3.1 shows this behavior for two video signal cases, one representing apicture with high brightness and the other—with low, shown also, is a zero-meansinewave signal for which the DC level does not change. The variation in DC levelwould cause the brightness of the image to change in response to changes in theaverage brightness. To prevent this effect a DC restoration, or clamp, circuit isneeded to fix the level of the video signal to a known reference level.

The simplest form of a DC clamp circuit is shown in figure 3.2. The switchS1 can be activated during the hsync pulse, thus, “clamping” the tip of the hsyncpulse to ground level, this is called sync tip clamping. It is, also, possible toactivate the switch during the blanking level of the back porch, fixing the blacklevel to 0V, this is called black level clamping. Since the sync pulse voltage isusually not well defined and, also, may not be very stable from line to line, the

21

22 DC restore block

Vin Ccouple

Rin

Ileakage

Video precessing device

0V 0V

Figure 3.1: Effects on the signal levels due to AC coupling.

Vin Ccouple

Video precessing device

0V

0V

0V

Clamp

Synch tip clamp

Black Level clamp

S1

Figure 3.2: AC coupling with DC restoration.

3.2 Voltage-mode DC clamp 23

black level clamping provides much better DC stability than the sync tip clamping.

3.2 Voltage-mode DC clamp

The switch in figure 3.2 does not necessarily have to be connected to ground—itcan be connected to any other DC reference (figure 3.3) so that the clamp level canbe chosen arbitrary. This allows a propper bias level to be defined for the followingcircuitry by simply changing the reference voltage. This arrangement for whichthe DC level is directly forced to a known reference voltage is called voltage-modeclamping. In fact, the specification for the DC restoration for this thesis requiresthat the DC level should be possible to be set anywhere in the range from 100 mVto 500 mV—a voltage that should only be reproduced, not generated, by the clampcircuitry.

Vin Ccouple

Video precessing device

Clamp

S1

-+Vref

Figure 3.3: Voltage-mode DC restoration.

The purpose of the operational amplifier in figure 3.3. is to buffer the referencevoltage Vref and provide a low-impedance source for charging and dischargingof the coupling capacitor in a reasonable time. However, the precision and thespeed of the operational amplifier limit the performance of this circuit. Due to thepoor properties of the transistors in sub-micron CMOS technologies, the designof amplifiers with reasonable gain and offset is a challenging task. Due to thisreason and the preference for a more “digital” design the voltage-mode clamp isnot considered to be an appropriate candidate for implementation in the designedmultiplexer.

24 DC restore block

3.3 Current-mode DC clamp with current sourcesThe buffer of the voltage-mode clamp can be substituted by two much simplercurrent sources, as shown in figure 3.4 When the DC level needs to be increased thecurrent source connected to the input node with its positive terminal is activatedand the right plate of the input capacitor is charged to the positive supply voltage.When the DC level needs to be decreased the other current source is activated andthe capacitor is charged in the reverse direction. This arrangement is, also, termedcharge pump due to the apparent pumping of charge on the capacitor plates.

Vin Ccouple

Video precessing device

Clamp

S1

ctl

Figure 3.4: Current-mode DC restoration.

In a digitizer application, it makes sense to utilize the main ADC in the feed-back loop for sensing the DC level and controlling the DC clamp level. Thecurrent-mode clamp, also called charge pump, is readily suited for control directlyfrom the digital domain, that is, the current sources need be just on or off. Aconceptual representation of the current-mode clamp with the main video ADC inthe loop is illustrated in figure 3.5. Note that this topology highly resembles thatof the voltage-mode clamp, but instead of the analog reference voltage a referencedigital code is used, and that the analog buffer is replaced by a digital comparatorwhich generates the “UP-DOWN” control signal.

It should be emphasized that the clamp circuit in figure 3.5 does not operatein continuous time. Certainly, the ADC samples the continuous-time input signaland produces output only at certain instants of time. Furthermore, the chargethat is stored on the capacitor plates is proportional to the time the charge pumpsare activated, thus the loop-gain is dependent on the timing.

Due to its “digital” nature the current-mode clamp is far better suited forimplementation in CMOS technology. It should be noted that a digital comparatorconsumes far less power and die area and is, also, much simpler to design andlayout. Due to the above said, the current-mode clamp has been selected forfurther consideration for implementation in the video AFE.

3.4 Current-mode DC clamp without current sources 25

Vin Ccouple

Video precessing device

DigitalComparator

VideoADC

Reference word

up

down

Figure 3.5: Closed-loop operation of the current-mode clamp utilizing the mainvideo ADC.

3.4 Current-mode DC clamp without currentsources

The current sources of the current-mode clamp described above can be imple-mented with two MOS transistors as shown in figure 3.6 where transistor Ns actsas a current source and transistor Nsw—as switch for turning the clamp on or off.

up/down

Iclamp

up/down

Vbias

Iclamp Nsw

Ns

Figure 3.6: Realization of the controlable current source.

In order for transistor Ns to be in saturation and actually act as a currentsource the condition VGS < VDS + VTH must be met. In the extreme case, thedrain-source voltage (VDS) drops to 100 mV (the minimum clamp voltage) whichmeans that the maximum overdrive voltage (VGS −VTH) can be at most 100 mV.Simulations, carried out with these constraints, showed that in order to make theclamp current sufficiently large the width of that transistor must be made in the

26 DC restore block

order of 150 µm. Furthermore, the output resistance of the transistors in the targetCMOS technology is very low, this directly translates to a low output impedanceof the current source making the clamp current strongly dependent on the inputvoltage.

It should be noted that due to the short channel effects the output resistance(seen at the drain) of short-channel devices does not show significant dependenceon the operating mode of the transistor, making the transition between the linearand saturated region smooth and almost indistinguishable. It makes sense, then,for the clamp circuit to remove the current source (transistor Ns) and leave onlythe switch (transistor Nsw), significantly reducing the size and complexity of thecircuit.

Let us, now, follow one possible operation of this “stripped down” version ofthe clamp circuit in more detail. First, the voltage of the part of the video signalthat is to be “clamped” is sampled and converted by the ADC, note that theADC convertion is running independently of the clamp block and the sample ofinterest is simply taken from the ADC output stream. The sample value (code)is then compared to the reference (target) value and the UP −DOWN signal isgenerated, i.e. it is decided if the DC level should be increased or decreased. Theclamp is then activated for a predetermined amount of time (maximum of 6 pixels,according to the specification) and a specific amount of charge is placed on theinput capacitor plates, thus shifting the DC level at the input.

Here it must be emphasized that since the current through the clamp transistorsis strongly dependent on the signal level to be clamped, the amount of charge puton the input capacitor per cycle is, also, different for different DC levels. Thismakes the clamp settling response non-linear, however, this is not of significantimportance as only the final, settled value, and the settling time is of interest forthe operation of the video digitizer. It is also important to show that the clampbehavior is stable, that is, it does not oscillate from cycle-to-cycle. This will beshown in section 5.3.

Due to its “digital” nature and good results from the initial simulations thetopology described above has been selected for the actual implementation in thevideo multiplexer.

3.4.1 The implemented DC clampSo far, the topology discussed for the clamp block has been somewhat simplifiedto ease its presentation. In practice, however, the clamp current cannot be simplyswitched on and off because this would make the precision with which the DClevel is set too low. Let us consider the change in voltage of the input capacitor(and the DC level) for one activation of the clamp, it can be written as:

∆Vin =∆t · Iclamp

Cin(3.1)

where Iclamp is the clamp current, Cin is the input capacitance and ∆t is the timethe clamp is active, i.e. enabled. The clamp time is more or less fixed, as theclamp can be active for at most 6 pixels and the smallest practical time is one

3.4 Current-mode DC clamp without current sources 27

system clock period. This means that in order to make the clamp precise theclamp current has to be very small, which would make the transient behavior veryslow as well. To circumvent this, the clamp current is made controlable, so thatwhen the error (difference between the target DC level and the actual DC level)is small the current can be set to be small as well, allowing for the DC level tobe changed in small increments. For large errors, the clamp current can be madebigger, so as to speed-up the transition.

The adjustment of the clamp current is made possible by connecting severalclamp current transistors in parallel and enabling only some of them (note theresemblance to a current steering DAC). The need for more signals to control theoperation of the clamp means that the digital comparator of figure 3.6 must nowbe changed to a subtractor which calculates the error code and applies it to theclamp as a control signal.

It is, also, possible to implement a much more complex control strategy of theDC clamp. For example, during the initial transient, when a particular multiplexerinput is selected, the DC level may be at a completely wrong voltage, in that casethe clamp may be activeted for much longer time—even during the active videoportion of the signal. This will allow shorter settling time than possible if the clampis activated only during the back porch. Of course, a more complicated controlblock than the simple subtractor will be required to implement such behavior. Theclamp control strategy is, however, out of the scope of this work.

Chapter 4

Analog Multiplexer -performance metrics

In this chapter, we will introduce the main performance metrics that were used toguide the design process of the analog multiplexer and the accompanying clampcircuitry. We will first relate each metric to the particular non-ideal behavior thatlimits the corresponding performance. Then, we will show how the video signaland the digitizer as a whole are affected, giving examples where appropriate.

4.1 Bandwidth

Probably, one of the most common and popular specification parameters for avideo or graphics system today is its resolution. The resolution is the ability todistinguish between small details in the reproduced picture. The details of animage can be present both in the light intensity (brightness), or in the color of theobjects. High detail in an image corresponds to rapid changes in the video signal,which means that in order to represent high resolution the analog video signalsmust have wide bandwidth. Figure 4.1a shows a commonly used test pattern forvideo systems, while in figure 4.1b the same pattern is shown but this time thebandwidth of the underlying signal has been limited. Notice that the verticalboundaries between the different color patches have become blurred and that thefine vertical black-and-white stripes have practically turned into a grey rectangle.

Any real analog signal is subject to bandwidth limitation, including the analogvideo signal when being processed and transmitted. As discussed in chapter 2,the finite on-resistance of the switches in the multiplexer together with the inputcapacitance of the next module in the digitizer channel form a low-pass filter whichlimits the bandwidth of the video signal being processed.

In order to accommodate all available video and graphics formats availabletoday the 3 dB bandwidth requirement for the video multiplexer is defined byspecification to be 500 MHz. In fact, this is much larger than what is requiredfor the currently available video formats, but is chosen as such in order for future

29

30 Analog Multiplexer - performance metrics

(a) Normal (b) Limited bandwidth

Figure 4.1: Effect of bandwidth limitation of the video signal.

formats to be supported as well.

4.2 Linearity

As was discussed in section 1.5, the color and brightness information is containedin the amplitude of the analog video signal during the active video portion. Thisis why it is important that when video is processed the relative amplitude of thesignal is preserved, excluding any gain. Linearity is defined as the property of asystem to respond to the sum of any two inputs with an output which is the sumof the output responses corresponding to each of the two inputs taken separately.Any non-linear system introduces non-linear distortion to the signals it processes.

If a video signal is non-linearly distorted the color and brightness informationis lost and the picture will not be displayed properly. The actual effect of non-linearity on the image depends on the signaling method that is utilized. Supposethat in a RGB system (for example PC graphics) the color yellow, produced bythe colors green and blue, is to be displayed, Assume, also, that the green and bluecomponents are with equal magnitudes, corresponding do mid brightness level. If,now, the brightness of the image is doubled (maximum brightness), but the bluechannel introduces non-linearity and the intensity of the blue color is increasedonly 1.5 times, then the green color will dominate and the final image will lookgreenish. This effect corresponds to color space deformation. Figure 4.2b showsthe same test pattern as before but with non-linear distortion applied separatelyto each of the color channels—red, green and blue. Notice how the color havechanged and that the overall picture brightness have increased.

As was discussed in section 2, the switches in the video multiplexer are subjectto non-linear behavior, hence the non-linear distortion introduced by the multi-plexer has been the most important performance metric influencing the design de-cisions. The actual performance measure used was the spurious-free dynamic range(SFDR) measured in dBc. Due to the complex non-linear behavior of the switches,

4.3 Inter-channel isolation 31

(a) Normal (b) Non-linear distortion

Figure 4.2: Effect of non-linear distortion of the video signal.

the SFDR was specified for several input signal amplitudes and frequencies—1 Vp-pat 20 MHz, 0.8 Vp-p at 40 MHz and 0.2 Vp-p at 1 MHz, with corresponding linearityof at least 60 dBc, 40 dBc and 80 dBc.

4.3 Inter-channel isolationIt is possible that the signal at a multiplexer input, that is not currently selected,to leak through the open switches and mix with the signal from the active input.Depending on the video formats of the two signals this interference may appearin the final image as noise or as a background ghost image. If the two signals arewith completely different formats, for example TV and computer graphics, theyare not correlated and the interference appears as noise in the form of “crawling”diagonal lines. However, if the signals are with the same format, for example fromtwo TV tuners, then they have the same horizontal and vertical refresh rates andthe image from the interfering input may be visible on the screen.

The inter-channel isolation has been specified to be at least 70 dBc for allfrequencies in the range 0-500 MHz.

4.4 Clamp circuit performance metricsThe primary purpose of the clamp circuit is to define the DC level of the videosignal and keep it stable throughout the frame, it is also required to initially bringthe DC level to the target voltage in a timely manner. If the clamp circuit is notstable, that is the DC voltage oscillates between the lines, then horizontal stripeswith varying brightness will be visible on the screen. This is a highly undesirableeffect since the human eye is very sensitive to different brightness levels. The resultfrom unstable behavior of the clamp circuit is shown in figure 4.3b. Note that,despite of the small random variation of at most ±5% applied to the DC level thevariation in brightness is quite visible.

32 Analog Multiplexer - performance metrics

The performance measures that guided the design of the clamp circuit werestability and settling time. The settling time was specified to be at most 1 frame.

(a) Normal, stable DC level (b) Unstable DC level

Figure 4.3: Effect of unstable DC clamp. The brightness is varied by 5%.

4.5 Leakage and lower cut-off frequencyAs discussed earlier, the video signal is AC coupled to the input of the multiplexerthrough an external capacitor which “holds” the DC level during the active videoportion. If a small current leaks through the internal circuits of the digitizerchannel of the video AFE, the DC level of the signal will change throughout theline. On the screen, this will be visible as a changing brightness of the image fromleft to right as shown in figure 4.4b. This effect can also be viewed as a too high

(a) No leakage (b) Excessive leakage

Figure 4.4: Effect of leakage current through the input capacitor.

lower cut-off frequency, this is indeed possible as the AC coupling acts as a high-

4.5 Leakage and lower cut-off frequency 33

pass filter. In the early video systems the problem with leakage through the inputcoupling capacitor (also called “line droop” or “line tilt”) was quite severe, butin modern systems it is easily corrected in the digital domain. Nevertheless, suchcorrection reduces the available range of the ADC and leakage must be limited asmuch as possible in the analog domain.

Note that the brightness at the rightmost edge of the image in figure 4.4b. isonly 5% lower than that at the leftmost, still it is clearly visible.

The amount of change in DC level per line is not explicitly specified in thedesign specifications, but a value no bigger than 1 LSB of the main video ADCwas targeted in the design of the multiplexer and clamp circuits.

Chapter 5

Design Details

5.1 Introduction

So far, we have only discussed the different blocks of the input multiplexer in termsof their expected performance and different implementation strategies, we havealso selected a particular schematic to be realized for each block. In this chapter,we will describe the design details for each circuit, give detailed transistor sizingstrategies and the rationale and trade-offs behind the design decisions.

Due to the relative simplicity of the interaction between the blocks comprisingthe multiplexer, it was possible to carry-out the design in the meet-in-the-middlefashion, without building behavioral models for the different blocks. Note that thebehavior of a switch, even with parasitics, is not particularly interesting.

First, the bootstrapped switch topology, presented by Lillebrekke et al. in[2], was implemented and the circuit behavior studied in detail in order to verifythat it is suitable for the purposes of an analog switch in the multiplexer. Severalmodifications of the original circuit were proposed and successfully implemented.A behavioral model was, then, built for the clamp block and its operation togetherwith the switch was studied and simulated in order to identify potential problems.The clamp circuits were, then, implemented at transistor level and resimulated.Finally, the whole multiplexer was connected together and thoroughly simulatedin order to identify shortcomings and potentially fix them. During this phase theanalog switches were resized in order for all specifications to be met.

5.2 Bootstrapped switch

The selected in section 2.3 analog switch schematic was implemented in the targetCMOS technology and the circuit operation was assessed in terms of performanceand robustness. The detailed schematic of the switch is shown in figure 5.1, this isthe original schematic as presented by Lillebrekke et al. The Spectre™ simulatoranalog language VerilogA was used to describe the behavior of the non-overlappingclock generator and the input signal generator. This allowed to quickly switch

35

36 Design Details

between different simulation set-ups.

VddswOFF

NS5 N5

Vout

SWG

DS

Vin

ChrgHI

A

N3

N8 N1 N6

NS6

ChrgLO

P2

B

P4

P7

Vdd

Cbootstrap

ChrgLO

ChrgLOND

Figure 5.1: Detailed schematic of the bootstrapped switch presented in [2]

The primary objective of these initial simulations was to explore the designspace and the main trade-offs for the design of the bootstrapped switch. As wasexpected, the bandwidth and linearity of the switch are highly dependent on thesize of the pass transistor (denoted by SW in figure 5.1) and both increase byincreasing the transistor width. Also, both linearity and bandwidth increase whena transistor with a lower threshold voltage and/or a thinner gate oxide is used asthe main switch. The main loading effect for the switch in figure 5.1 is the outputload capacitance, as such, its size also directly affects the performance.

5.2.1 Special design considerations

Originally, the selected bootstrapped switch circuit was designed for switchedcapacitor (SC) applications which have somewhat different requirements for theswitch performance. This imposed different requirements on the design and re-quired some modifications of the original switch circuit.

5.2 Bootstrapped switch 37

In order to achieve high clock rates in a switched capacitor circuit the switchesare required to change state very fast and with minimum delay, in the multiplexerenvironment this is not the case as the switching time is not of particular interest.Actually, the time needed for the circuits following the multiplexer to resynchronizeto a different video source is several orders of magnitude bigger than the timeneeded for any electronic switch to change state. Hence, the switching time is nottaken into consideration when designing the bootstrapped switch.

Also, in order not to introduce significant noise and offset the switches forswitched capacitor applications are required to keep the clock feedthrough andcharge injection to a minimum. For the video multiplexer it is not a problem if aglitch is introduced at the output when inputs are switched as at that instant thevideo signal is not even processed further. Hence, the dummy transistor ND fromthe original circuit shown in figure 5.1 is removed and is not implemented in thefinal design.

Another big difference in the requirements for the switches designed for switchedcapacitor applications and those for the video multiplexer is the time for whichthe switch is supposed to continuously operate in the closed (on) state. For staticswitches like the transmission gate, for example, this is not a problem, but for thebootstrapped switch, which has a dynamic nature, the charge on the bootstrapcapacitor has to be periodically refreshed to compensate for leakages. In SC cir-cuits, where switches are toggled with a few megahertz, this is done during theoff-state (open). However, in the case of the video multiplexer, the witches mustbe closed continuously and cannot be turned off for charging, so there must be amechanism provided for charging without opening the switch. This is achieved byadding the transistors N8, NS8 and P7 as shown in figure 5.3, this also means thatnow separate control signals are used for turning the switch off and for chargingof the bootstrap capacitor. Since, in order to be recharged the bootstrap capaci-tor has to be disconnected from the main switch transistor terminals, the outputsignal will be significantly distorted during that time, therefore, the recharge cycleshould be executed only during the blanking interval. However, due to the capac-itance present between the source and gate terminals of the main pass transistorthe switch will continue to operate in the closed state.

During the initial simulations of the switch circuit it was discovered that asituation potentially damaging the switch circuit may occur. Consider the circuitas shown in figure 5.2, if the input voltage drops to a level such that the voltageat node B becomes lower than the supply voltage with more than the thresholdvoltage of P4, it will turn on and cause current to flow through the bootstrapcapacitor, as shown in figure 5.2. Note that, the gate voltage of P4 is equal toits drain voltage (node B), hence it acts as a resistor for drain voltages higherthan Vt. The resulting current will charge the bootstrap capacitor to the voltagedifference of the input and supply voltages, minus one threshold voltage. It isactually possible for negative voltages to appear at the input node which meansthat the bootstrap capacitor will be charged to a voltage bigger than the supply.For example, if the input voltage drops to 450 mV (the ESD protection operatesat approximately 600 mV) and if the supply voltage is at its maximum of 1.2 Vthen the bootstrap capacitor will be charged to 1.2 V+450 mV-250 mV=1.4 V

38 Design Details

(assuming that the threshold voltage is 250 mV). This voltage when applied to thegate-source terminals of the main pass transistor will significantly reduce the lifeof the circuit. Note, also that in some process corners the threshold voltage maybe lower than 250 mV, further aggravating the situation.

VddswOFF

NS5 N5

Vout

SWG

DS

Vin

ChrgHI

A

N3

N8 N1 N6

NS6

ChrgLO

P2

B

P4

P7

Vdd

Cbootstrap

ChrgLO

Figure 5.2: Harmful current through the bootstrap capacitor due to low negativeinput voltages.

The problem is solved by the addition of the transistor PS4 as shown in figure5.3. During the on phase the control signal, and thus the gate of P4s, is at a highvoltage, approximately equal to the positive supply, this means that the transistorPS4 will stay off for any voltage at node B lower than the supply. For voltages atnode B higher than the supply, PS4 will turn on, but this is not a problem sincetransistor P4 will then be off.

The switch schematic shown in figure 5.3 is the actual schematic implementedin the input multiplexer.

5.2 Bootstrapped switch 39

VddChrgHI

N8NS8

VddswOFF

NS5 N5

q

Vout

SWG

DS

Vin

ChrgHI

A

N3

N8 N1 N6

NS6

ChrgLO

P2

B

PS4

P4

P7

Vdd

ChrgLO

P7

Cbootstrap

ChrgLO

Figure 5.3: The full schematic of the bootstrapped switch as implemented in thefinal version of the design.

5.2.2 Switch linearity and bandwidth

In section 2.2 we discussed that the main source of non-linearity in a MOS transistor-based switch is the variation of the gate-source voltage of the switch pass tran-sistor. While the bootstrap technique largely eliminates this variation there are afew other sources of non-linearity that limit the performance of the switch.

So far, we have neglected a significant source of non-linearity in the analogswitches, this is the non-linear junction capacitance introduced by the reversebiased source-bulk and drain-bulk PN junctions. The capacitance of a reversebiased PN junction is given by

CJ(VJ) =CJ0

(1− VJ

VDiff)mj

(5.1)

where CJ0 is the zero-voltage capacitance, VJ is the junction voltage, VDiff

is the diffusion voltage and m ≈ 1/3 . . . 1/2 is the capacitance coefficient. There-fore, the voltage over a non-linear capacitor charged through a resistor dependsnon-linearly on the input driving voltage. Also, the non-linear behavior is moreclearly pronounced for lower capacitor voltages and bigger resistances.

The non-linear junction capacitances that occur in the switch circuit and affect

40 Design Details

its performance are shown in figure 5.4 with black heavy lines and denoted by Cnli.The greatest effect on linearity is caused by Cnl1 and Cnl2 at the drain and thesource of the main pass transistor SW. They appear directly in the signal pathand are charged to the instantaneous voltage of the input video signal through theequivalent resistance of the pass transistor channel and the external terminationresistance. Also the magnitude of these two capacitances is the greatest since thetransistor SW is far bigger than the rest.

VddChrgHI

N8NS8

VddswOFF

NS5 N5

q

Vout

SWG

DS

Vin

ChrgHI

A

N3

N8 N1 N6

NS6

ChrgLO

P2

B

PS4

P4

P7

Vdd

ChrgLO

P7

Cbootstrap

ChrgLO

Cnl1Cnl2

Cnl3 Cnl4

Cnl5

Figure 5.4: Non-linear junction capacitances affecting the linearity of the boot-strapped switch.

The capacitances Cnl3, Cnl4 and Cnl5, caused by the transistors connected tonodes A, B and G, respectively, also contribute to the non-linear behavior. Noticethat they appear in the signal path from the input node to the gate node of themain pass transistor. This means that the AC component of the input signal isdistorted before it reaches the gate of the pass transistor creating an AC voltagedifference between the source and gate terminals of transistor SW, which resultsin variation of the on resistance. This contribution is, however, relatively small.

The discussion above suggests that a trade-off can be made between the sizeof the main switch, the threshold voltage and the load capacitance. Also, in orderto keep parasitics to a minimum the auxiliary transistors must be kept physicallysmall.

Note that, when the circuit is switched from the off state to the on state the

5.2 Bootstrapped switch 41

parasitic capacitance between the source and the gate of SW must be chargedby the bootstrap capacitor. Thus, the bootstrap charge is redistributed and theavailable overdrive voltage for the main switch is lowered. This suggests a trade-offbetween the size of the bootstrap capacitor and the main switch size and thresholdvoltage can be made.

The body effect is inherent to all integrated NMOS devices in a single-wellCMOS technology, as the one used for this design. The body effect causes thethreshold voltage to increase with the increase of the source-bulk voltage. Thiseffect cannot be fully eliminated for the selected circuit topology, however, it canbe minimized by selecting a transistor with a higher threshold voltage, i.e. therelative variation can be reduced. Despite of that, since the transistors with higherthreshold voltage are more resistive for the same driving voltage the overall lin-earity is not improved. This is because, as shown above, the non-linear loadingcapacitance now has a bigger effect on the total non-linearity.

5.2.3 Bootstrap charge retention

The operation of the bootstrapped switch is based on the ability of the bootstrapcapacitor to hold sufficient charge between recharging events. In order not to affectthe video signal the only possibility to recharge the bootstrap capacitor is duringthe blanking periods, this means that enough charge must be stored for the periodof one line, i.e. the hsync period. This proved to be a major limitation of theperformance of the circuit since, as expected the transistors of the target CMOStechnology were found to present substantial leakage currents both through thegate and between the D-S terminals when operating in the cut-off region.

Figure 5.5 shows the switch circuit when in the on-state, for clarity the tran-sistors that are ON are shown with heavy black lines, while those that are off areshown with light grey lines. The leakage current through the bootstrap capacitorhas several components, denoted with In and shown with different line colors infigure 5.5. The leakage current components notation is chosen such that only onedevice determines the magnitude of each particular component.The currents I3,I4, are determined by the gate leakage of transistor P2, and N1 and N8 com-bined, respectively, while I2, and I5 are due to the drain-source leakage in thecut-off region of transistors N5 and P4, respectively. The leakage component I1 isdetermined by the gate leakage of the main switch transistor SW.

Due to the availability of several different transistor types in the target CMOStechnology there are many ways to reduce the leakage currents, however, this in-troduces design trade-offs. In order to reduce the D-S leakage a transistor with ahigher threshold voltage can be used, also, short wide transistors have higher leak-age than transistors with narrower and longer channels. Loosely, the “stronger”transistors have more drain-source leakage, with the threshold voltage having thegreatest effect. The gate leakage can be reduced by using low-power, thicker oxidetransistor types, but they are also “weaker”. Transistors with greater gate areaalso have bigger gate leakage, so increasing either the length or the width alsoincreases the gate leakage.

The above means that the ability of the switch to operate for longer periods

42 Design Details

VddswOFF

NS5 N5

Vout

SWG

DS

Vin

ChrgHI

A

N3

N8 N1 N6

NS6

ChrgLO

P2

B

P4

P7

Vdd

Cbootstrap

ChrgLO

I1

I4

I3

I2

I5

Figure 5.5: Currents discharging the bootstrap capacitor due to device leakages.Transistors shown in black are ON.

without recharging, i.e. to retain the bootstrap capacitor charge, can be traded forseveral other parameters. The size of the pass transistor SW has the major effecton the circuit performance, thus, it has to be substantially larger than the rest ofthe transistors included in the switch circuit. Due to that, this transistor also hasthe biggest contribution to the leakage current. Thus, the trade-off is bandwidthand linearity for charge retention. In order to minimize the current I2 transistorN5 must be of high Vt type, however, this makes it weak and limits its ability todrain the current injected through the gate of transistor SW and keep it cut-offwhen the switch is in the off-state, i.e. when N5 is on. This means that a trade-offbetween charge retention and isolation in the off-state can be made. Also, to limitthe leakage through the gates of P2, N1 and N8 their area have to be kept smalland they have to be of low-power type, which makes them weak as well. Luckily,since they do not present D-S leakage problems they can be of low Vt type in orderto compensate for the loss in driving capabilities. The reduced driving strength ofthese three transistors leads to a decrease in linearity as the gate-source voltagecan not be kept constant. The leakages through N3 and P4 can be reduced by

5.2 Bootstrapped switch 43

making these transistors of high Vt type, but the reduced driving strength meansthat longer time for charging of the bootstrap capacitor will be needed.

5.2.4 OFF-state resistance and isolation

In order to provide sufficient attenuation for the signals at the non-active inputs ofthe multiplexer the switches must have a high off state resistance. As mentionedabove, in order to turn the bootstrapped switch off its gate is connected to ground.However, since the DC level at the inputs that are OFF is not controlled in any way,it is possible that negative voltages appear at the input of the switches that are inthe off-state, effectively turning the pass transistor on and reaching the output ofthe multiplexer. Furthermore high frequency signals may be capacitively coupledfrom the input of a switch to its output and reach the multiplexer output.

Vout

Vin

SwIn SwOut

SwMid

(a) Open, non-conducting state

Vout

Vin

SwIn SwOut

SwMid

(b) Closed, conducting state

Figure 5.6: T-switch arrangement used for the multiplexer switches implementa-tion.

In order to circumvent these problems, two switches are connected in series,while the middle common node is grounded by a third switch when no signal shouldbe passed. This arrangement, naturally called a T-switch, is shown schematicallyin figure 5.6. When the T-switch is in the off, non-conductive state, the two“horizontal” switches (SwIn and SwOut in figure 5.6) are off, while the third oneis on, hence, any signal that passes through the input switch is grounded and itsamplitude is significantly reduced, such that the output switch can more effectivelystop the signal from reaching the multiplexer output.

It must be noted that, only switches SwIn and SwOut must have high linearityin the on-state as they conduct the video signal when the T-witch is in the on-state,

44 Design Details

while the middle switch SwMid should only provide low impedance to ground whenturned on. Therefore, the middle switch can be a simple NMOS transistor withsufficient size.

5.3 DC restoration circuit

In section 3.4.1 we described the basics of the implemented DC restoration methodand circuit, here we will present the design details and discuss the transistor sizingstrategy.

The circuit topology of the charge pumping block of the DC restore circuit isshown in figure 5.7, it consists of two sections of transistors—a pull-up and a pull-down section. Each section consists of 31 identical (unit) transistors connectedin parallel, the number of active transistors is controlled by a 5-bit digital word.The direction of the output current is controlled by activating either the pull-upor the pull-down transistors. The DC restore block can be viewed as a closed-loop

Vdd

controllogic

Cin

Iclamp

Pull-Up

Pull-Down

P31

N31

P2

N2

P1

N131

31

Werr5

sign

Figure 5.7: Charge pump with a 5-bit controllable current implemented with sim-ple transistor switches.

system, as shown in figure 5.8, the input control variable WinDC is a digital wordrepresenting the target DC level and the output variable WoutDC is the value ofthe output sample from the video ADC which corresponds to the portion of thevideo signal whose level is to be controlled (back porch for example). Since thebehavior of the charge pump is highly non-linear the closed-loop system cannotbe analyzed by means of a transfer function, therefore time domain analysis haveto be utilized. Nevertheless, it is beneficial to linearize the charge pump circuitaround the operating point determined by the video signal voltage at the time of

5.3 DC restoration circuit 45

Charge Pump

Vdd

WinDC WoutDCWerr

512

12

Video ADC

Video In

Cin

Figure 5.8: The DC restore circuit viewed as a digital control loop, the inputvariable is the target DC level and the output is the controlled and measured DClevel.

activation of the clamp.The schematic of the charge pump together with the input capacitor is shown

in figure 5.7, the pump consists of two groups of 31 unit size transistors, onlytransistors from one group are activated per clamp event (the DC restore circuitis not continuously active). The number of active transistors corresponds to thedifference between the input variable WinDC and the output variable WoutDC ,that is, to the error variable Werr. At the operating point, we can consider thetransistors of each of the pull-up or pull-down networks as a controlable currentsource with the control signal being the value of the digital error variable, as shownin figure 5.7. The group of transistors that is to be activated depends on the signof the error, that is, whether the DC level should be increased (pulled-up) ordecreased (pulled-down). Note that, if we disregard the quantization of the errorvariable the two current sources and the input capacitor behave like a discrete-timeintegrator. This means that for the quantized error variable the clamp behaves asan accumulator, summing up the values of the error variable. In the time domainthis behavior can be expressed as:

∆VDC = WerrGI(VDC) ·∆t

Cin(5.2)

where, ∆VDC is the change in the DC voltage level per clamp activation event,Werr is the integer error (control) variable, GI(VDC) is the current gain of thecurrent sources as function of the output DC level, ∆t is the period of time forwhich the clamp is active, and Cin is the capacitance of the input capacitor. Thecurrent gain is dependent on the DC level, since the pull-up/down transistorsoperate in the linear region and in practice behave like resistors, however, it is

46 Design Details

more convenient to work with their equivalent current gain in the operating pointdetermined by the DC voltage.

Note that, the error term Werr corresponds to the digitized version of thedifference between the target DC level and the current DC level measured by thevideo ADC. We can instead write:

∆VDC = Verr ·GI(VDC) ·∆t

GADC · Cin︸ ︷︷ ︸loop gain

(5.3)

where, GADC is the gain of the video ADC, and Verr is the voltage differencebetween the target and the current DC levels, note that, this is a fictitious voltageand does not physically exist in the system.

Observe that, if the voltage change ∆VDC is equal to the current error voltageVerr then the error voltage for the next cycle will be zero, that is the systemwould have settled. Also note, that such system behaves as a unit delay from thereference input to the output and the output response corresponds to the criticallydamped closed loop response.

In order for the equality ∆VDC = Verr to be fulfilled the expression to the rightof Verr in equation 5.3 must be equal to one, that is the loop gain must be unity.We have:

GI(VDC) ·∆t

GADC · Cin= 1 (5.4)

rearranging, we get for the current gain:

GI(VDC) =GADC · Cin

∆t(5.5)

For the sizing of the charge pump transistors the current gain is what is actuallyneeded. If we size the transistors such that the highest loop gain is unity in theworst case then the system response will be underdamped in all other cases. Thisis confirmed by inspection of equation 5.3 — if the loop gain is lower than unitythe change in DC level per period is smaller than the absolute value of the errorvoltage.

The worst case for the loop gain occurs for the smallest input capacitor value,which is given by specification to be 10 nF, the highest ADC gain and the longestpossible activation period. As was discussed in 1.4, the resolution of the video ADCis 12 bits, it has an input range of 1 V and is preceded by a PGA (programable gainamplifier) with a maximum gain of 4, therefore the maximum gain of the ADC is1/4 · (212 − 1) = 61µV/LSB. The clamp time ∆t is defined by specification to bemaximum 6 pixels for the highest pixel rate of 300MHz, yielding ∆t = 6/300.106 =20ns. Substituting the above values in 5.5 we get for the maximum current gain:

max(GI(VDC)) =61.10−6 · 10−9

20.10−9= 30µA/LSB (5.6)

This value is higher than the minimum permitted by specification value of 20 µA/LSB,thus, the transistors in the charge pump are sized such that the in the worst casethe maximum current per LSB to be 30 µA.

5.3 DC restoration circuit 47

In the above calculations we assumed that the input coupling capacitor is10 nF, this value is rather low and in practice a capacitor with a higher value isusually used. In such cases the settling time of the DC restore circuit may becomeexcessively long, to compensate for that a longer activation time may be used.This is indeed possible since most video formats have pixel rates much lower thanthe 300MHz rate assumed above.

The number of bits specified as the precision of the DC restore block is 5,hence, the clamp current can be controlled in 215-1=31 steps. With the abovecalculated value for the current per 1 LSB the maximum current when all bitsare active becomes: 31·30 µA = 930 mA. This is less than half of the maximumpermitted current of 2 mA, so in order to fully exploit the design margin thetransistor in the charge pump that is activated for the highest value of the digitalcontrol word is sized such that when all bits are at a high state the output clampcurrent is 1.98 mA. This means that the largest output current corresponds to66 LSB, thus with this small modification the settling time is more than halvedwhile the resolution is kept the same. The resulting transfer characteristic of thecharge pump is shown in figure 5.9 for all values of the digital control word. Thisbehavior must be taken into account for the design of the control logic that isgoing to implement the DC restore block control strategy. For example, for thecontrol loop from figure 5.8 the result from the subtractor (Werr) must not be setto the maximum value before the actual difference becomes more than 66 LSB,otherwise unstable behavior may occur.

0 1 2 3 30 31

30

60

870

900

1980

Icla

mp [

uA

]

Digital input value [LSB]

Figure 5.9: Transfer characteristic of the charge pump of the clamp block.

48 Design Details

5.3.1 Control signals and actual implementation

The charge pump of the DC restore block is implemented by unit transistors withparallel connected drain and source terminals, while their gates serve as enableinputs. This means that a 31-bit thermometer encoded word is needed to controlthe operation of the charge pump, furthermore the direction selection of the clampcurrent, that is which transistor network is active, is done by a direction (sign)bit. Figure 5.7 shows the charge pump-circuit together with the required controllogic and the names of the control signals, as implemented at the final stage of thedesign.

The functions of the signals shown in figure 5.7 are as follows: bit is a 5-bitdata bus for controlling the clamp current, the data encoding is unsigned binary;sign controls the direction of the clamp current, when high the pull-up networkis active, when low—the pull-down; en is an enable signal, when low the clamp isenabled and the output current corresponds to the value at the bit input, whenlow the clamp is disabled and all pull-down transistors are turned ON. This ratherstrange use of the en signal shall be explained in more detail in the followingsection. It is important to mention here, that the binary-to-thermometer decoderhas not been implemented at transistor level, but only as a behavioral model, theVerilogA code of the decoder is given in Appendix A, there the function of the ensignal and the discontinuity around the 31-st input bit can be seen in more detail.

5.4 Multiplexer topology and top-level design

So far, in order to simplify discussions, we have examined the different blockscomprising the designed multiplexer somewhat in isolation. In this section wepresent the way the different block are interconnected, how they interact witheach other and how the overall performance is affected.

Recall that, the multiplexer switches are implemented as T-switches for whichthe most important requirement for the middle switch is to have sufficient drivingstrength. This is actually the same requirement as for the pull-up/down transistornetworks of the charge pump of the DC restore block. Therefore, it was proposedthat these two blocks, the T-switch and the DC restore, be integrated into a singlefunctional unit, so that the pull-down transistor network of the DC restore circuitcan be used as a grounding (middle) switch of the T-switch structure. This is thereason why a high level of the enable signal for the clamp block is specified to turnon the pull-down network. The resulting topology for a single multiplexer switchis shown in figure 5.10 together with the DC restore circuit. Note that the controllogic circuitry is omitted for clarity.

The overall block diagram of the designed 8-input multiplexer is shown in figure5.11. This is the simplest architecture of a multiplexer, where each multiplexerinput signal is passed to the output through a single switch. In this case the outputparasitic capacitance of all switches is seen at the output of the multiplexer, thiscapacitance is a major source of nonlinearity, as discussed in section 5.2.2. In orderto prevent some of this capacitance from loading the currently conducting switch itis possible to arrange the multiplexer switches in a pyramidal structure. However,

5.4 Multiplexer topology and top-level design 49

5

Vdd

bit

en

RESD

SwIn

ChrgHI ChrgLO swOFF

SwOut

ChrgHI ChrgLO swOFF

Vout

Vin

Figure 5.10: Interconnection of the blocks in a single multiplexer channel as im-plemented in the final design

for the designed multiplexer such arrangement was not necessary and the requiredlinearity and bandwidth could be achieved with the simple topology of figure 5.11.Furthermore, arranging the multiplexer this way makes the physical layout to bevery regular and compact. Also, note that, since for the simple structure of figure5.11 each switch is a standalone structure and independent of the others (it hasthe DC resore and all required control circuitry “built-in”), the multiplexer caneasily be modified by adding or removing input channels.

Since the input of switch SwIn for all multiplexer channels is connected directlyto the integrated circuit bonding pad it must be protected against ESD (electro-static discharge) by a secondary ESD protection circuit (the primary protection isin the input pad itself). The secondary ESD protection consists of two clampingdiodes and a series resistor connected between the input pad and the circuit nodeto be protected, as shown in figure 5.10. Since the protection resistance, whichmust be at least 50Ω and nominally—250Ω, combined with the multiplexer loadcapacitance of 1.5pF would limit the bandwidth to an unacceptably low value,therefore, the pass transistor of the input switch had to be split into seven parallelinstances. Thus, a separate protection resistance with a sufficiently high value wasused for each unit transistor, while the effective (due to the parallel combination)value that determines the time constant was kept low enough so as not to limitthe bandwidth.

5.4.1 Design considerations and transistor sizing

Up to this point of the design of the multiplexer it was not possible to size thetransistors such that the deign specifications are met. In this section we will discussthe most important design considerations and the transistor sizing strategy.

During the top-level simulations it was discovered that the input and output

50 Design Details

Vout

Vin1

Vin2

Vin3

S1

S2

S3

Vin8S8

SwIN SwOUT

Figure 5.11: Final architecture of the designed multiplexer.

switches of a T-switch do not necessarily have to provide the same performance inall aspects as they actually bare different functionality in the multiplexer. Obvi-ously, both switches have to provide good linearity in the on-state, but that doesnot necessary have to be achieved the same way for both of them. It turns outthat due to the shunt section of the T-switch the input switch does not have toprovide very high levels of signal attenuation in the off-state. This means that themain pass transistor of that switch can be implemented by a “leaky” low-thresholdtransistor which requires much smaller width (therefore, smaller area) in order toachieve the required linearity and bandwidth.

The sizing of the pass transistor in the output switch is related to more trade-offs: Firstly, its area must be kept as small as possible in order to limit thenon-linear capacitance introduced at the output node, on the other side, it cannotbe made too small since then the transistor itself will become too resistive andnon-linear. Furthermore, only transistors with high threshold voltage must beused due to the high leakage currents of the other two types (low and standardthreshold voltage). The leakage current between the drain and source terminalsof the output switch in the T-switches that are off passes through the T-switchthat is on and through its corresponding external coupling capacitor. The effectof such leakage currents was discussed in section 4.5, where it was explained whythey should be avoided.

Chapter 6

Test bench and simulationresults

In this chapter we first introduce the test bench that was used throughout thedesign of the multiplexer and to extract the relevant performance parameters andverify the design. After that we present the actual simulation results and theobtained performance parameters together with some comments on them.

6.1 Test bench design

The video multiplexer falls in the, so called, mixed-signal class of circuits, theseare circuits which have both digital signals (usually clocks and control) as wellas analog signals. This type of circuits are particularly hard to simulate, bothdue to their complex behavior and due to the long simulation time required. Thecomplicated behavior arises from the fact that these circuits usually require someform of set-up sequence on their digital inputs before the behavior with respectto the analog signals can be simulated. For example, the bootstrapped switchesof the multiplexer must be pre-charged and put in the on-state before linearitycan be analyzed. Furthermore, the digital signals usually have short rise and falltimes forcing the SPICE-like simulators to use short time steps, hence the longsimulation times.

The simulation of mixed signal circuits is further complicated by the great va-riety of external signal waveforms and timing scenarios that have to be simulated.For example, in order to verify that the transistors in the bootstrapped switchesare not stressed beyond their breakdown voltages, it was necessary to operatethe bootstrap circuitry for different video signal voltages and switching activities.Therefore, additional effort was made when the test bench for the multiplexer wasdesigned.

The performance metrics discussed in chapter 4 are of widely varying natureand each of them requires a totally different test bench set-up to simulate. Take,for example, the simulation of linearity and leakage currents through the input

51

52 Test bench and simulation results

capacitor, linearity simulation requires that an input signal with a sinewave bepresent, while leakage simulation requires a quiet circuit so that the small leakagecurrents are easily measurable. Furthermore, when optimizing a particular per-formance metric, it is quite likely that another one is compromised (trade-offs),hence, it is highly beneficial to be able to quickly re-run simulation setups fordifferent performance metrics. Due to this reason the primary goal in the designof the test bench was to be able to simulate all scenarios that are of interest withjust one schematic (netlist) of the test bench.

The principle schematic of the test bench is shown in figure 6.1, where the videosignal generator block and the timing and control block were written in VerilogA.Since the behavior of these blocks has to be different for the different simulationsetups they were written such that their behavior depends on design parameters.By setting these parameters the environment (for the multiplexer) behavior canbe changed without modifying the netlist. The VerilogA code for the video signalgenerator is listed in Appendix B.

Cin

75

Disturbance

Inactive Channels

Video SignalGenerator

Sim

ula

ted

mu

ltip

lexe

r

Input selectionand bootstraprecharge control

Hori

zon

tal sy

nc Vout

Cin

Cin

75

75

75

75

75

Figure 6.1: Block diagram of the test bench used for the simulations of the mul-tiplexer and clamp circuits

The simulations were entirely driven by an OCEAN script which was executedin the Cadence environment. The script is separated in sections—each sectionperforms a particular simulation, extracts the relevant parameters (such as band-width) and writes them into a text file. Each section is conditionally executed incase a variable enabling it is set to true, while the enable variables were set manu-ally at the top of the script, this allows only the selected simulation analysis to be

6.2 Simulated performance parameters and results 53

performed. A key element in the OCEAN script is that all design variables (suchas transistor widths) are set by a single function which is called in each section,this allows a centralized control over the all-important design variables.

6.2 Simulated performance parameters and resultsHere we present the results obtained by simulating the designed multiplexer in itsintended operating environment. The performance parameters are separated intotwo groups: the first group consists of performance metrics as given in the designspecification and are, therefore, limited by minimum and/or maximum value; thesecond group consists of parameters, that we feel, are important for the operationand future characterization of the designed schematics.

Table 6.1 lists the parameters given in the design specification together withthe results obtained from the simulations of the design. The last column in table6.1 gives some short explanation of the simulation set-up. The minimum and max-imum values are given for the PVT (process-voltage-temperature) corner wherethey occur, while the typical values are given for the typical PVT corner.

6.2.1 Internal voltage levelsSince the operation of the bootstrapped switch is based on the addition of theinput voltage with the voltage of the bootstrap capacitor, voltages bigger than thesupply voltage appear on internal nodes of the switch circuit. The original circuit,as presented by Lillebrekke in [2], is designed such that the transistors are notstressed by these high voltages. However, since for the multiplexer application theswitches operate continuously for long periods of time, in the presence of possiblypulsating video signals (for example vertical black and white stripes), it is possiblethat charge injected in the floating nodes compromise the reliability and robustnessof the circuit. Special attention has been payed to this phenomenon and the theswitch circuit was simulated with several input signal patterns in order to discoverpotentially problematic nodes. As expected, the input signal that caused thegreatest internal node voltages was a square wave.

The bootstrapped switch was simulated with a square wave input with anamplitude of 1.4 Vp-p and the maximal power supply voltage of 1.2 V, the resultswere then processed by an OCEAN script which extracts the maximal and averagecurrents that flow through the transistors and the maximal voltages that appearover each combination of two terminals of the transistors. The absolute values ofthe extracted voltages and currents are presented in table 6.2, note that, these arepeak values and that the average are usually much lower.

54 Test bench and simulation results

Item Min Typ Max Unit CommentNumberof Inputs

specified 8 — — — —simulated 8 — —

Bandwidth specified 500 — — MHz Measured at -3 dB belowDC level.simulated 536 694 3469

Linearity 1 specified 60 — — dBc Measured forVin =1 Vp-p at 20 MHz.simulated 65 81 —

Linearity 2 specified 40 — — dBc Measured forVin =0.8 Vp-p at 40 MHz.simulated 60 78 —

Linearity 3 specified 80 — — dBc Measured forVin = 0.2 Vp-p at 1 MHz.simulated 106 110 —

Isolation specified 70 — — dBc Modified specification.ADC range: 250mV; 12bitsimulated — — 2 LSB

ClampCurrent

specified 25 — 2000µA —simulated 15 30 1980

Output LoadCapacitance

specified — — — pF Not originally specified.PGA input capacitance.simulated — — 1.5

ClampingVoltage

specified 100 — 500 mV Operation outside thisregion may be unstable.simulated 100 — 500

Clamp time specified — 6 — pixels Defined by the selectedexternal control strategy.simulated — 6 —

DC set time specified — 1 — frame Defined by the selectedexternal control strategy.simulated — — —

ESDprotection

specified 50 100 — Ohm —simulated — 200 —

Low Supplyvoltages

specified 1 1.1 1.2

V

Can be lowered if thenumber of inputs or theload capacitance islowered.

simulated 1 1.1 1.2

Table 6.1: Simulated performance parameters for across all process corners.

6.2 Simulated performance parameters and results 55

Terminal Maximal stress CommentMaximal (peak) absolute voltages

Drain–Source 2.1 V —Gate–Source 1.31 V —Gate–Drain 1.34 V —Bulk–Source 1.31 V Forward biasBulk–Source -0.30 V Reverse biasBulk–Gate 2.98 V —

Maximal (peak) absolute currentsGate 16 µA —Bulk 43 µA —Drain/source 1.1 mA Due to the main switch

Average absolute currentsGate 290 nA —Bulk 5 µA —Drain/source 110 µA —

Table 6.2: Simulated stress results for the transistors in the bootstrapped switch

Chapter 7

Conclusion

The various design and implementation details of the project, related to the goalsand limitations stated in sections 1.1 and 1.2 have been discussed in the precedingchapters. In this section we provide an overview of the achievements of the thesiswork.

In chapter 2 analog multiplexers were discussed in general and several tradi-tional approaches for realizing analog switches in CMOS technology were reviewed.These simple realizations are not applicable for submicron CMOS implementationwith its accompanying low supply voltage and poor device characteristics. Thebootstrapping method was proposed at the end of the chapter as a means to cir-cumvent the limitations imposed by the low supply voltage and a suitable circuitof a bootstrapped switch was selected for further analysis and implementation.

Several possible methods for setting the DC voltage level of the AC coupledvideo signals were reviewed in chapter 3. While all of the discussed architectureswere successfully used in analog video systems not all of them are appropriate forrealization in a submicron CMOS integrated circuit technology. A “stripped down”version, consisting only of pull-up and pull-down transistors, of the commonly usedcharge pump was selected for implementation and the trade-offs related to thischoice were discussed.

In chapter 5 we have given the important design considerations for the boot-strapped switch, the DC restore block and the possible hardware sharing betweenthese two circuits. The design trade-offs related to these circuits were discussedand the transistor sizing and selection was given and motivated. Special atten-tion was paid to the leakage currents in the bootstrapped switches, since in manycases leakages are the factors dictating transistor sizing and type selection and,therefore, limit the achievable performance.

Finally, in chapter 6 we provided a brief overview of the testbench that was usedfor the simulations of the designed circuits. At the end of the chapter we presentedthe achieved performance of the design and provided a detailed simulation resultsregarding the performance of the final design.

57

Chapter 8

Future work

In order for an integrated circuit design to be fully characterized and declared tobe conforming to the specification, the physical layout have to be complete andthe extracted netlist simulated and verified. Despite that the completion of thelayout artwork for the designed blocks was set as desirable achievement for theproject, no block was finalized in the layout stage. This is the major direction forfuture development of the designed blocks and towards completion of the videoAFE as a whole. The layout has to be completed in correspondence with theoverall floorplanning of the video AFE, the resulting extracted netlist has to besimulated again and if necessary some of the design stages re-iterated in order toregain any loss of performance.

While the main goal of performance and range of supported video formatshas been accomplished, this was achieved at the cost of suboptimal design in thesense that the different formats have contradictory requirements. High resolutionformats require high bandwidth and linearity, while low resolution (usually TVformats) require the bootstrapped switches to operate for long periods withoutrecharging. A possible future improvement of the design can be the separationof the multiplexer inputs and the optimization of the inputs for specific videoformats. This will allow the required chip area to be minimized, mainly due tothe decreased size of the bootstrap capacitor.

The DC restoration circuit has been designed and verified to be functional butno particular control strategy has been implemented. However, in order for anactual algorithm to be devised, the design of the video ADC has to be completedif it is to be included in the feedback loop for the measurement of the DC level.Also, there could be several possible control algorithms with varying degree ofintelligence, therefore, they should be evaluated and the one which is most suitableto the video AFE has to be selected.

59

Bibliography

[1] Roy Blake. Electronic communication systems. Delmar/Thomson Learning,Albany, NY, USA, second edition, 2002.

[2] C. Lillebrekke, C. Wulff, and T. Ytterdal. Bootstrapped switch in low-voltagedigital 90nm cmos technology. In NORCHIP Conference, 2005. 23rd, pages234 – 236, nov. 2005.

[3] J. Steensgaard. Bootstrapped low-voltage analog switches. In Circuits andSystems, 1999. ISCAS ’99. Proceedings of the 1999 IEEE International Sym-posium on, volume 2, pages 29 –32 vol.2, jul 1999.

[4] M. Waltari and K. Halonen. Bootstrapped switch without bulk effect in stan-dard cmos technology. Electronics Letters, 38(12):555 – 557, 6 2002.

61

Appendix A

VerilogA code of thebinary-to-thermomenterencoder

1 // Veri logA fo r daisyVideoMux ,daisyVideoMus_bin2therm_coder , v e r i l o g a

23 ‘ include " cons tant s . vams "4 ‘ include " d i s c i p l i n e s . vams "56 module daisyVideoMus_bin2therm_coder ( therm , vdd , vss , bin ,

_en , d ir , s i gn ) ;7 output [ 0 : 3 0 ] therm ;8 e l e c t r i c a l [ 0 : 3 0 ] therm ;9 inout vdd ;

10 e l e c t r i c a l vdd ;11 inout vss ;12 e l e c t r i c a l vss ;13 input [ 0 : 4 ] bin ;14 e l e c t r i c a l [ 0 : 4 ] bin ;15 input _en , s i gn ;16 output d i r ;17 e l e c t r i c a l _en , s ign , d i r ;1819 parameter vThres =0.55;20 parameter tR i se = 300p ;21 parameter t F a l l = 300p ;22 parameter real vHigh =1.1;2324 integer therm_tmp [ 0 : 3 0 ] ;

63

64 VerilogA code of the binary-to-thermomenter encoder

25 integer i , inVal , dir_tmp ;26 genvar j ;2728 analog begin29 for ( i =0; i <31; i=i +1) begin30 therm_tmp [ i ]=0;31 end3233 inVal =0;34 for ( j =0; j <5; j=j +1) begin35 inVal=inVal+ ( (V( bin [ j ] )>vThres ) ? 1 : 0 ) ∗pow(2 , j ) ;36 end3738 i f (V( s i gn )>=vThres ) begin39 dir_tmp=1;40 end41 else begin42 dir_tmp=0;43 end4445 for ( i =0; i <31; i=i +1)begin46 i f ( inVal >0)begin47 therm_tmp [ i ]=1;48 end49 inVal=inVal −1;5051 i f (V(_en)>vThres ) begin52 therm_tmp [ i ]=1;53 //dir_tmp=1;54 dir_tmp=0;5556 end57 end5859 for ( j =0; j <31; j=j +1) begin60 V( therm [ j ] ) <+ t r a n s i t i o n ( therm_tmp [ j ] ∗

vHigh , 0 , tRise , t F a l l ) ;61 end62 V( d i r ) <+ t r a n s i t i o n ( dir_tmp∗vHigh , 0 , tRise , t F a l l ) ;63 end64 endmodule

Appendix B

VerilogA code of the videosignal generator

1 // Veri logA fo r daisyVideoMux , daisyVideoGenerator ,v e r i l o g a

2 // Generates a v ideo s i g n a l which can be used f o rs imu la t i on s of , f o r

3 //example , l i n e a r i t y , t iming , e t c . . .4 //5 // A l l t iming and s i g n a l l e v e l c h a r a c t e r i s t i c s can be chnged

from the6 // corresponding parameters7 //An a r b i t r a r y input s i g n a l can be forwarded to the output

during the8 // a c t i v e v ideo por t i on by s e t t i n g . i n p u t S e l e c t to 1 .9 //

10 //The input v O f f s e t can be used to add a DC o f f s e t , noise ,etc , to the

11 // e n t i r e v ideo s i g n a l1213 ‘ include " cons tant s . vams "14 ‘ include " d i s c i p l i n e s . vams "1516 module daisyVideoGenerator ( videoOut , hSync , blanc , vIn ,

vOf f s e t ) ;1718 output videoOut , hSync , blanc ;19 input vIn , vOf f s e t ;20 e l e c t r i c a l videoOut , hSync , blanc , vIn , vOf f s e t ;2122 // This d e f a u l t parameters se tup does not n e c e s s a r i l y

65

66 VerilogA code of the video signal generator

correspond to a23 // meaningfu l v ideo s i gna l , i t i s j u s t good f o r c i r c u i t

s imu la t i on .24 //=================================25 //Timing parameters26 parameter real hSync_period = 25e−6 ;27 parameter real hSync_length = 2e−6 ;28 parameter real fPorch_length = 3e−6;29 parameter real bPorch_length = 4e−6;30 parameter real p ixe l_per iod = 50e−9;3132 //=================================3334 //=================================35 // Vol tage l e v e l parameters . These cou ld be e a s i l y changed

to IRE36 // uni t s , but v o l t s are more meaningfu l f o r c u r c u i t des i gn .37 parameter real vHigh = 1 . 1 , vLow = 0 ; //High/ low output

v o l t a g e s f o r the hSync and b lanc outputs , t h e s e ared i g i t a l

38 parameter real videoMax = 1 . 2 ; //The h i g h e s t l e v e l foundin the a c t i v e v ideo s i g n a l

39 parameter real videoBlack = 0 . 1 ; //The b l a c k v ideol e v e l , u s a l l y the same as b lank l e v e l , but not f o r NTSC

40 parameter real videoBlank = 0 . 0 ; //The b l anc ingl e v e l

41 parameter real hSyncLevel = −0.35; //hSync pu l s eminimum l e v e l

42 parameter real videoGain = 1 . 0 ; //The v ideo s i g n a l ( noto f f s e t ) i s mu l t i p i ed by t h i s

43 //=================================4445 parameter i n p u t S e l e c t =1; // s e t to 1 to s e l e c t e x t e r n a l

input , or to 046 // to s e l e c t i n t e r n a l l y generated

random s i g n a l4748 integer hSyncActive , blankActive , n ;49 real act iveVideo , v ideo ;5051 integer seed ;52 analog begin5354 @( i n i t i a l _ s t e p ) begin55 hSyncActive = 0 ;56 blankAct ive =0;

67

57 seed =100;58 end59 i f ( a n a l y s i s ( " pss " ) ) begin60 V( videoOut )<+2∗(V( vIn )+V( vOf f s e t ) ) ;61 V( hSync )<+vLow ;62 V( blanc ) <+vLow ;63 end64 else begin65 //@( t imer ( bPorch_length , hSync_period ) ) hSyncActive

= 1 ;66 n = ( ( $abstime + hSync_length ) /hSync_period ) ;67 @( t imer (n∗hSync_period ) ) ;68 @( t imer (n∗hSync_period+hSync_length ) ) ;69 //@( t imer ( bPorch_length+hSync_length , hSync_period ) )

hSyncActive = 0 ;70 //@( t imer ( bPorch_length+hSync_length , hSync_period ) )

;71 i f ( ( $abstime−bPorch_length>=n∗hSync_period ) && (

$abstime−bPorch_length<=(n∗hSync_period+hSync_length ) ) ) begin

72 hSyncActive = 1 ;73 end74 else begin75 hSyncActive = 0 ;76 end77787980 //@( t imer (0 , hSync_period ) ) b l ankAc t i v e =1;81 //@( t imer ( bPorch_length+hSync_length+fPorch_length ,

hSync_period ) ) b l ankAc t i v e =0;82 //@( t imer (0 , p i x e l_per iod ) ) ac t i veVideo=

$rdis t_uni form ( seed , v ideoBlack , videoMax ) ;83 n=(( $abstime+bPorch_length+hSync_length+

fPorch_length ) /hSync_period +0.5)−1;84 @( t imer (n∗hSync_period ) ) ;85 @( t imer (n∗hSync_period+(bPorch_length+hSync_length+

fPorch_length ) ) ) ;86 i f ( ( $abstime>=n∗hSync_period ) && ( $abstime<=n∗

hSync_period+(bPorch_length+hSync_length+fPorch_length ) ) ) begin

87 blankAct ive =1;88 end89 else begin90 blankAct ive =0;91 end

68 VerilogA code of the video signal generator

9293 // i f ( i n p u t S e l e c t > 0 .5 ) beg in94 act iveVideo=V( vIn ) ;95 // end9697 video = ( t r a n s i t i o n ((1− blankAct ive ) , 0 . 0 , 240 p ,240 p) ∗

act iveVideo )+t r a n s i t i o n ( ( blankAct ive ∗ videoBlank ), 0 . 0 , 240 p ,240 p)+t r a n s i t i o n ( ( hSyncActive ∗hSyncLevel ) , 0 . 0 , 240 p ,240 p) ;

9899 //V( videoOut ) <+ t r a n s i t i o n ( videoGain ∗ video ,0 .0 ,1000

p ,1000 p ) ;100 V( videoOut ) <+ 2∗ videoGain ∗ video ;101102 //V( videoOut ) <+ t r a n s i t i o n (V( v O f f s e t ) ,0 ,0 , 240p ,240

p ) ;103 V( videoOut ) <+ 2∗V( vOf f s e t ) ;104 V( hSync ) <+ t r a n s i t i o n ( hSyncActive==1 ? vHigh : vLow

, 0 . 0 , 240p , 240p ) ;105 V( blanc ) <+ t r a n s i t i o n ( blankAct ive==1 ? vHigh : vLow

, 0 . 0 , 240p , 240p ) ;106 //V( b lanc )<+n ;107 end // e l s e108 end109 endmodule

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