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Integrated Circuit Devices. Professor Ali Javey Summer 2009. Fabrication Technology. Silicon Device Fabrication Technology. Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. - PowerPoint PPT Presentation
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Integrated Circuit Devices
Professor Ali Javey
Summer 2009
Fabrication Technology
Silicon Device Fabrication Technology
Over 1015 transistors (or 100,000 for every person in the world) are manufactured every year.
Variations of this versatile technology are used for flat-panel displays, micro-electro-mechanical systems (MEMS), and even DNA chips for DNA screening...
Terminology
SSI (Small Scale Integration) – few transistorsMSI (Medium Scale Integration) – hundredsLSI (Large Scale Integration) - thousandsVLSI (Very Large Scale Integration) - millionsULSI (Ultra Large Scale Integration)
Foundry (Fab)
• Foundry (also called a fab for fabrication plant) is used to refer to a factory where devices like integrated circuits are manufactured. The central part of a fab is a cleanroom.
• Note the difference between a fab and a lab.
Cleanroom Standards
Federal Standard Class Limits
CLASSMEASURED PARTICLE SIZE (MICROMETERS)
0.1 0.2 0.3 0.5 5.0
1 35 7.5 3 1 NA
10 350 75 30 10 NA
100 NA 750 300 100 NA
1,000 NA NA NA 1,000 7
10,000 NA NA NA 10,000 70
100,000 NA NA NA 100,000 700
Why do we need cleanrooms?
Introduction to Device FabricationOxidation
Lithography &Etching
Ion Implantation
Annealing & Diffusion
Thin Film Deposition
Oxidation of SiliconSi + O2 SiO2
Si +2H2O SiO2 + 2H2
Dry Oxidation :
Wet Oxidation :
Thin oxide
Thick oxide
Si Wafers
O2
N2
H2O or TCE(trichloroethylene)
Quartz tube
Resistance-heated furnace
Flowcontroller
Oxidation of Silicon
EXAMPLE : Sequential Oxidation
(a) How long does it take to grow 0.1m of dry oxide at 1000 oC ?
(b) After step (a), how long will it take to grow an additional 0.2m of oxide at 900 oC in a wet ambient ?
Solution:
(a) From the “1000oC dry” curve in Slide 3-3, it takes 2.5 hr to grow 0.1m of oxide.
(b) Use the “900oC wet” curve only. It would have taken 0.7hr to grow the 0.1 m oxide and 2.4hr to grow 0.3 m oxide from bare silicon. The answer is 2.4hr–0.7hr = 1.7hr.
Oxidation of Silicon
Lithography
Resist Coating
Exposure
Development
Etching and Resist Strip
Photoresist
Oxide Si
(a)
OpticalLens system
Deep Ultraviolet Light
Photomask withopaque and clear patterns
Si
Si
Si
Si
Positive resist
Negative resist
(c)
(d)(b)
Lithography
Photolithography Resolution Limit, R• R kdue to optical diffraction• Wavelength needs to be minimized. (248 nm, 193 nm, 157 nm?)• k (0.5) can be reduced by • Large aperture, high quality lens
• Small field, step-and-repeat using stepper• Phase-shift mask• Optical proximity correction
• Lithography is difficult and expensive. There are ~20 lithography steps in an IC process.
Other Advanced Lithography Methods
• EUV Photolithography
• E-beam Lithography
• Dip-pen lithography
Dip-pen Lithography, Chad Mirkin, NWU
Richard Feynman
Pattern Transfer–Etching
Isotropic etching Anisotropic etching
SiO2
SiO2
SiO2
(1)
(2)
(3)
photoresist
photoresist
SiO2
(1 )
(2)
photoresist
pho to re sis t
SiO2
SiO2
(3)
(a) Isotropic wet etching (b) Anisotropic dry etching.
wet etch dry etch
Pattern Transfer–Etching
Dry Etching (also known as Plasma Etching, or Reactive-Ion Etching) is anisotropic.
• Silicon and its compounds can be etched by plasmas containing F.• Aluminum can be etched by Cl.• Some concerns :- Selectivity and End-Point Detection- Plasma Process-Induced Damage or Wafer Charging Damage and Antenna Effect
Scanning electron microscope view of a plasma-etched (dry-etched) 0.16 m pattern in polycrystalline silicon film.
DopingIon Implantation
Si
Ions
Masking materialfor example resist or SiO
2
• The dominant doping method• Excellent control of dose (cm-2)• Good control of implant depth with energy (KeV to MeV)• Repairing crystal damage and dopant activation requires
annealing, which can cause dopant diffusion and loss of depth control.
Ion implantation
Phosphorous Density Profile after Implantation
Doping
Other Doping Methods
• Gas-Phase Doping : Used to dope Si with P using POCl3.
• Solid-Source Doping : Dopant diffuses from a doped solid film (SiGe or oxide) into Si.
• In-Situ Doping : Used to dope deposited films during film deposition.
Dopant Diffusion
Dtxo eDt
NtxN 4/2
),(
N : Nd or Na (cm-3)No : dopant atoms per cm2
t : diffusion timeD : diffusivity, is the approximate distance of dopant diffusion
p-type Si
SiO2
n-type diffusion layer
Junction depth, xj
Dt
Dopant Diffusion
Some applications need very deep junctions (high T, long t). Others need very shallow junctions (low T, short t).
D increases with increasing temperature.
Dopant Diffusion
Shallow Junction and Rapid Thermal Annealing
• After ion implantation, thermal annealing is required. Furnace annealing causes too much diffusion of dopant for some applications.
• In rapid thermal annealing (RTA), the wafer is heated to high temperature in seconds by a bank of heat lamps.
Also RTO (oxidation), RTCVD (chemical vapor deposition), RTP (processing).
Thin-Film Deposition
Three Kinds of Solid
Crystalline Polycrystalline
Silicon wafer Thin film of Si or metal. Thin film of SiO2 or Si3N4.
Amorphous
Thin-Film Deposition
• Metal layers for device interconnect
• Inter-metal dielectric
• Poly-Si for transistor gate
• Barrier against interdiffusion
• Encapsulation
Sputtering
Target materialdeposited on wafer
S i W a f e r
Ion (Ar+)
Sputtering target
Atoms sputtered out of the target
Schematic Illustration of Sputtering Process
Chemical Vapor Deposition (CVD)
Molecules of deposited layer
Chemicalreaction
Gas 1
Gas 2
Si Wafer
Thin film is formed from gas phase components.
Si Wafers
Quartz tube
Resistance-heated furnacePressure sensor
Gas control
Source gases
Pump
Trap exhaust To
system
LPCVD Systems
Chemical Vapor Deposition (CVD)
Interconnection–The Back-end Process
Dopant diffusion regionSi
SiO2
Al-Cu
(a)
Sidiffusion region
CoSi2
M etal 1
Metal 2
M etal 3
Dielectric
Dielectric
Encapsulation
(b)
Dielectric
via or plug
Multi-Level Metallization
Sun Microsystems Ultra Sparc Microprocessor
Interconnection–The Back-end Process
Copper Interconnect
• Al interconnect develops voids from electromigration.
• Cu has excellent electromigration reliability and 40% lower resistance than Al.
Interconnection–The Back-end Process
Chapter Summary–A Device Fabrication Example
Start
Oxidation
Lithography
Oxide Etching
Annealing &Diffusion
AlSputtering
Lithography
(0)
Positive resist SiO2
P-Si
P-Si
SiO2
P-Si
Mask
UV
SiO2 SiO2
SiO2 SiO2
SiO 2 SiO2
P-Si
PN+
SiO2 SiO2
PN+
P-Si
SiO2 SiO2
PN+
Mask
Al Res is t
SiO2 SiO2
PN+
(1 )
(2)
(4)
Arsenic implantation
A l
UV
(7)
(3)
(5)
(6)
(8)
(9)
SiO2 SiO2
PN+
SiO2 SiO2
PN+
(10)
SiO2 SiO 2
PN
+
(11)
SiO2 SiO 2
PN+
(12)
SiO2 SiO2
PN
+
(13)
Al
Si3N
4
Si3N
4
Si3N
4
Si3N
4
Si3N
4
Al
Al
Al
Al
Al
Photoresist
Au
Au
wire
Plastic package
metal leads
SiO2
A l
(0)
Positive resist SiO2
P-Si
P-Si
SiO2
P-Si
Mask
UV
SiO2 SiO2
SiO2 SiO2
SiO 2 SiO2
P-Si
PN+
SiO2 SiO2
PN+
P-Si
SiO2 SiO2
PN+
Mask
Al Res is t
SiO2 SiO2
PN+
(1 )
(2)
(4)
Arsenic implantation
A l
UV
(7)
(3)
(5)
(6)
(8)
(9)
SiO2 SiO2
PN+
SiO2 SiO2
PN+
(10)
SiO2 SiO 2
PN
+
(11)
SiO2 SiO 2
PN+
(12)
SiO2 SiO2
PN
+
(13)
Al
Si3N
4
Si3N
4
Si3N
4
Si3N
4
Si3N
4
Al
Al
Al
Al
Al
Photoresist
Au
Au
wire
Plastic package
metal leads
SiO2
A l
Metal etching
CVDnitridedeposition
Lithographyand bondingwindow etching
Back Side milling
Au depositionon the backside
Dicing, wire bonding,and packaging
Chapter Summary–A Device Fabrication Example
(0)
Positive resist SiO2
P-Si
P-Si
SiO2
P-Si
Mask
UV
SiO2 SiO2
SiO2 SiO2
SiO 2 SiO2
P-Si
PN+
SiO2 SiO2
PN+
P-Si
SiO2 SiO2
PN+
Mask
Al Res is t
SiO2 SiO2
PN+
(1 )
(2)
(4)
Arsenic implantation
A l
UV
(7)
(3)
(5)
(6)
(8)
(9)
SiO2 SiO2
PN+
SiO2 SiO2
PN+
(10)
SiO2 SiO 2
PN
+
(11)
SiO2 SiO 2
PN+
(12)
SiO2 SiO2
PN
+
(13)
Al
Si3N
4
Si3N
4
Si3N
4
Si3N
4
Si3N
4
Al
Al
Al
Al
Al
Photoresist
Au
Au
wire
Plastic package
metal leads
SiO2
A l
(0)
Positive resist SiO2
P-Si
P-Si
SiO2
P-Si
Mask
UV
SiO2 SiO2
SiO2 SiO2
SiO 2 SiO2
P-Si
PN+
SiO2 SiO2
PN+
P-Si
SiO2 SiO2
PN+
Mask
Al Res is t
SiO2 SiO2
PN+
(1 )
(2)
(4)
Arsenic implantation
A l
UV
(7)
(3)
(5)
(6)
(8)
(9)
SiO2 SiO2
PN+
SiO2 SiO2
PN+
(10)
SiO2 SiO 2
PN
+
(11)
SiO2 SiO 2
PN+
(12)
SiO2 SiO2
PN
+
(13)
Al
Si3N
4
Si3N
4
Si3N
4
Si3N
4
Si3N
4
Al
Al
Al
Al
Al
Photoresist
Au
Au
wire
Plastic package
metal leads
SiO2
A l