Integrated electronic for SiPMIntegrated electronic for SiPMKOBE – 29 June ‘07

M. Bouchel, F. Dulucq, J. Fleury, C. de La Taille, G. Martin-Chassard, N. Seguin, L.

Raux, S. Blin, P. Barrillon, S. Callier

LAL Orsay IN2P3-CNRS – Université Paris-Sud – B.P. 34

91898 Orsay cedex – France

Introduction LAL microelectronic group is designing integrated front-

end electronic for particle physics Its know-how has evolved from low-noise front-end to

multichannel read out ASICs system on chip design allowing low-cost high number of channel read-out

That talk will introduce a bunch of Front-end ASICs designed by LAL microelectronic group

4 ASICs suitable for SiPM read out will be presented :

2004FLC_SIPM

2006MAROC2

2006HARDROC

2007SPIROC

FLC_SIPM

TCMTAHCAL

beam

ECAL

90 c

m 120

cm

FLC_SIPM has been designed to read out the CALICE AHCAL physics prototype

It is also used in the TCMT read out

Tile HCAL testbeam prototype 1 cubic metre 38 layers, 2cm steel plates 8000 tiles with SiPMs Electronics based on CALICE ECAL

design, common back-end and DAQ

DESY, Hamburg U,ITEP, MEPHI, LPI (Moscow)Northern IllinoisLAL, OrsayPragueUK groups

Tile sizes optimized for cost reasons

ASICs: LALBoards: DESY

DAQ: UK

DESY

From Felix Sefkow’s talk

Gain and dark rate uniformity correction

SiPM gain varies with the high voltage value DAC to adjust gain

CHANNEL BY CHANNEL

from M.Danilov ITEP, Moscow

Gain and dark rate uniformity correction

+HV

Preamp input

50Ω

100nF

SiPM

100kΩ 100nF 8-bit DAC

ASICHigh voltage on

the cable shielding

The input DACs allow to adjust HV channel by channel via slow control on the 8000 SiPM of the detector

Chip description

18-channel 8-bit DAC (0-5V) 18-channel front-end readout :

Variable gain charge preamplifier (0.67 to 10 V/pC) Variable time constant CRRC2 shaper (12 to 180 ns)

Track and hold 1 multiplexed output Power consumption : ~200mW (supply : 0-5V) Technology : AMS 0.8 m CMOS Chip area : ~10mm² Package : QFP-100

Channel architecture for SiPM readout

100nF

10pF

Charge Preamplifier :Low noise : 1300e- @40ns

Variable gain :

4bits : 0.67 to 10 V/pC

CR-RC² Shaper :Variable time constant : 4 bits (12 to 180ns)

12ns photoelectron measurement (calibration mode)180ns Mip measurement (physic mode)

compatibility with ECAL read-out

12kΩ

4kΩ 24pF

12pF

3pF

in

8pF 4pF 2pF 1pF

40kΩ

8-bit

DAC

0-5V

ASIC

Rin =

10kΩ

50Ω

100MΩ 2.4pF

1.2pF

0.6pF

0.3pF

0.1pF

0.2pF

0.4pF

0.8pF

6pF

MIP and photo-electron responses

Physics mode : Cf=0.4pF- t=180ns - Rin ON 1 MIP = 16 p.e. injected Vout = 23 mV @ tp = 160 ns SLOW SHAPING FOR TRIGGER

LATENCY

Calibration mode : Cf=0.2pF - t=12ns - Rin OFF 1 SPE = 0.16pC injected (0.6mV in 270pF) Vout = 11 mV @ tp = 35 ns

Linearity measurement (physics mode)Linearity Rin ON

t=180ns

0

500

1000

1500

2000

2500

0 50 100 150 200 250 300 350

Qinj (MIP)

Vo

ut

(mV

)

Cf=0,1pF

Cf=0,8pF

Cf=0,4pF

Cf=0,2pF

Cf=1,5pF

Linearity Residuals for physics mode (%)

-1

-0,8

-0,6

-0,4

-0,2

0

0,2

0,4

0,6

0 10 20 30 40 50 60 70 80 90

Injected charge (MIP=16p.e.)

0.5%

-0.5%

•Voltage swing : ~2.1V

•Dynamic Range: 80 MIPs

•Linearity: <1%

Cross-talk measurement

Set-up: Cf=0.4pF, t=180ns

Channel-to-Channel cross-talk : ~ 1-2‰ :negligible 2 contributions :

Capacitive coupling between neighboring channels

Long distance crosstalk in all channels (comes from a reference voltage)

Non-Direct neighbouring channel x100

Sampling time

Capacitive coupling contribution

Direct neighbouring channel x100

Long Distance cross-talk contribution

FLC_SIPM results

With russian SiPMWith MPPC

Felix

Sefk

ow

& a

l

Tohru

Take

shit

a &

al

-Physics results on such high number of channel are coming up-So far :

-Noise as expected-Coherent noise very low-Dynamic range as expected

MAROC : a versatile front-end chip

MAROC has been designed to read out 64-anode MA-PMT from HAMAMATSU. The first application is the ATLAS luminometer.Many other application have popped up (medical imaging, astrophysics, basically everything using MA-PMT)

MAROC : main features 64 Channels – designed to read out MA-PMT Discrimination on each channel (3 thresholds) Multi-gain preamp (0-4, 6 bits) tunable channel by channel to

correct PMT gain non uniformity Charge measurement and 12 bit multi-channel ADC working

aside and independently of threshold detection (for cross measurement or calibration)

Perfectly suitable for SIPM read-out

ATLAS luminometer using Hamamatsu MA-PMTExample of high integration

MAROC block diagramHold signal 1

Photomultiplier64 channels

Photons

Variable Gain

Preamp.

VariableSlow Shaper

20-100 ns

S&H 1

BipolarFast Shaper

Unipolar Fast Shaper

Gain correction64*6bits

3 discri thresholds (3*12 bits)

MultiplexedAnalog charge

output

LUCID

S&H 2

3 DACs12 bits

64 Wilkinson 12 bit ADC

64 trigger outputs

MultiplexedDigital charge

output

64 inputs

Hold signal 2

LUCID

FS choice

80 MH

z encod

er

Cmd_LUCID

EN_serializer

MUX

SUM of 7 fibres 9 Sums

Or 64 SiPM

Consumption : 130mW (~2mW/channel)

MAROC measurements

Channel dispersion without any correction

Trigger efficiency : minimal injection

The minimum input charge is 10 fC

DAC resolutionAll three DAC embedded have roughly the same response, DAC2 is presented here

shaper transient responseThe slow shaper transient response is presented here for different preamp gains

S-curves with threshold sweep

DAC1 = 800

DAC1 = 1400

An example of trigger adjustment through the threshold (DAC step: 10)

50% efficiency charge vs thresholdCharge threshold increases linearly with the DAC value

HARDROC presentation

HARDROC has been designed to read out the CALICE RPC DHCAL technical prototype.

HARDROC main features

Full power pulsing

Digital memory: Data saved during bunch train.

Only one serial output @ 1 or 5MHz

Store all channels and BCID for every hit. Depth = 128 bits

Data format : 128(depth)*[2bit*64ch+24bit(BCID)+8bit(Header)] = 20kbits

BASICALLY : MAROC with internal RAM and time counting

One HaRD_ROC event

Discris

resu

lts – 6

4*2

bit

BCID

– 2

4 bi

t

Chip

ID -

8 bi

t

Position Energy Time

160 bits / chip event Depht is 128

Auto trigger and data output

Header

BCID Ch7

Auto trigger with 10fC:Qinj=10fC in Ch7DAC0 and DAC1=255 (~5fC)

Performance summaryNumber of inputs/outputs 64 inputs, 1 serial output

Input Impedance 50-70Ω

Gain Adjustment 0 to 4, 6bits, accuracy 6%

Bipolar Fast Shaper ≈3.5 mV/fC tp=15ns

10 bit-DAC 2.5 mV/fC, INL=0.2%

Trigger sensitivity Down to 10fC

Slow Shaper (analog readout) ≈50 mV/pC, 5fC to 15pC , tp= 50ns to 150ns

Analog Xtk 2%

Analog Readout speed 5 MHz

Memory depth 128 (20kbits)

Digital readout speed 5MHz or more

Power dissipation (not pulsed) 100 mW (64 channels)

Second generation chip for SiPM : SPIROC

SPIROC has been designed to read out the CALICE AHCAL technical prototype

Technical prototype architecture

Very similar to SiW ECAL

Following CALICE / EUDET DAQ concept

2.2m

~ 2000 tiles/layer

Layer units (assembly) subdivided into smaller PCBsHBUs:Typically 12*12 tiles, 4 ASICs

DIF(Layer

Concentrator,Clock, control,Configuration)

LDA(Module

concentrator,Optical link)

SPIROC2nd gen ASIC

incl ADC

With 40 µW / chTemp gradient 0.3 K / 2m

From Felix Sefkow’s talk

Integrated layer design

Sector wall

Reflector Foil100µm

Polyimide Foil100µm PCB

800µm

Bolt with innerM3 threadwelded to bottom plate

MGPD

Tile3mm

HBU Interface500µm gap

Bottom Plate600µm

ASICTQFP-1001mm high

Top Plate600µm steel

Component Area: 900µm highHBU height:6.1mm(4.9mm without covers => absorber)

AbsorberPlates(steel)

Spacer1.7mm

Top Plate fixing

DESY

integrated

From Felix Sefkow’s talk

SPIROC presentation

36-channel readout chip Self triggered Energy measurement :

2 gains / 12 bit ADC 1 pe 2000 pe Variable shaping time from 50ns to 100ns pe/noise ratio : 11

Time measurement : 1 TDC (12 bits) step~100 ps – accuracy ~1ns pe/noise ratio on trigger channel : 24 Fast shaper : ~15ns Auto-Trigger on ½ pe

Internal input 8-bit DAC (0-5V) for SiPM gain adjustment

It is a System on chip device, including control and communication features

Block scheme of SPIROC

Bunch crossing

Ch. 0

Ch. 1

Analog channel Analog mem.

36-channel12 bit

WilkinsonADC

for charge and time Meas.

Analog channel Analog mem.

Ch. 35 Analog channel Analog mem.

12-bit counterTime

digital mem.

Eventbuilder

Memorypointer

Triggercontrol

MainMemory

SRAM

Commodule

HC

AL

SLA

B

Time considerations

time

Time between two trains: 200ms (5 Hz)

Time between two bunch crossing: 337 ns Train length 2820 bunch X

(950 us)

Acquisition

1ms (.5%)

A/D conv..5ms (.25%)

DAQ.5ms (.25%)

1% duty cycle

IDLE MODE

99% duty cycle

199ms (99%)

SPIROC running modes

Acquisition A/D conversion DAQ

When an event occur :•Charge is stored in analogue memory•Time is stored in digital (coarse) and analogue (fine) memory•Trigger is automatically rearmed at next coarse time flag (bunch crossing ID)

Depht of memory is 16

The data (charge and time) stored in the analogue memory are sequentially converted in digital and stored in a SRAM.An event in RAM is :•The coarse time•The fine time•The charge•The shaper gain•The status of the trigger

The events stored in the RAM are outputted through a serial link when the chip gets the token allowing the data transmission.When the transmission is done, the token is transferred to the next chip.256 chips can be read out through one serial link

Read out : token ring, zero suppress

Acquisition A/D conv. DAQ IDLE MODEChip 0

Chip 1 Acquisition A/D conv. DAQ IDLE MODEIDLE

Chip 2 Acquisition A/D conv. IDLE MODEIDLE

Chip 3 Acquisition A/D conv. IDLE MODEIDLE

Chip 4 Acquisition A/D conv. IDLE MODEIDLE DAQ

Chip 0 Chip 1 Chip 2 Chip 3 Chip 4

5 ev

ents

3 ev

ents

0 ev

ent

1 ev

ent

0 ev

ent

Data bus

Read out of millions of channels for ILC

SPIROC: One channel schematic

50 -100ns

50-100ns

Gain selection

8-bit threshold adjustment

Reference voltage

T

15ns

DAC output

Q

HOLD

Slow Shaper

Slow Shaper

Fast Shaper

Time measurement

Charge measurement

Fast ramp

300ns

12-bit Wilkinson

ADC

Trigger

Depth 16

Depth 16

Depth 16

Common to the 36 channels

8-bit DAC

0-5V

Low gain Preamplifier

High gain Preamplifier

Analog memory

50pF

5pF

0.1pF-1.5pF

READ

Variable delay

0.1pF-1.5pF

IN

IN test

Discri

DAQASIC

Chip ID register 8 bits

gain

Trigger discri Output

Wilkinson ADC Discri output

gain

Trigger discri Output

Wilkinson ADC Discri output

..…

OR36

EndRamp (Discri ADC Wilkinson)

36

36

36

TM (Discri trigger)

ValGain (low gain or high Gain)

ExtSigmaTM (OR36)

Channel 1

Channel 0

ValDimGray 12 bits

…

Acquisition

readout

Conversion ADC

+

Writing RAM

RAM

FlagTDC

ValDimGray

12

8

ChipID

Hit channel register 16 x 36 x 1 bits

TDC rampStartRampTDC

BCID 16 x 8 bits

ADC rampStartrampb (wilkinson

ramp)

16

16ValidHoldAnalogb

RazRangN

16ReadMesureb

Rstb

Clk40MHz

SlowClock

StartAcqt

StartConvDAQb

StartReadOut

NoTrig

RamFull

TransmitOn

OutSerie

EndReadOut

Chipsat

Expressions

0 .250 .500 .750 1.0time (us)

2.5

0

-2.5

-5.0

-7.5

-10.0

Y0

(mV

)Y

0 (m

V)

.2500

-.250-.500-.750

-1.0-1.25

Y1

(mV

)Y

1 (m

V)

150100

50.00

-50.0-100-150

Y2

(mV

)Y

2 (m

V)

10.0

7.5

5.0

2.5

0

-2.5

Y3

(mV

)Y

3 (m

V)

1.251.0

.750

.500

.2500

-.250

Y4

(mV

)Y

4 (m

V)

out_pa_hg

out_pa_lg

out_fs

out_ssh_hg

out_ssh_lg

time (us)

User: raux Date: Feb 9, 2007 Time: 2:34:15 PM CET

SPIROC : Photoelectron response simulation

High gain Preamplifier response

Low gain Preamplifier response

Fast shaper

High gain Slow shaper

Low gain Slow shaper

Tp=15ns

Tp=50ns

Tp=50ns

Noise/pe ratio = 25

Noise/pe ratio = 11

Noise/pe ratio = 31mV/pe

10mV/pe

120mV/pe

Simulation obtained with SiPM gain = 106 _ 1 pe = 160 fC

Conclusion

Our group is able to provide in short terms integrated electronic to read out MA-PMT, SiPM or APDs. The versatility of our chips – using programmable parameters (gain, peaking time, thresholds) make them suitable for many applications

Integrated electronic is the best way to read out high number of channels detectors, it allows to reduce cost and improve compacity in every application

More information : fleury@lal.in2p3.fr