vendredi 21 avril 2023

Status report on SPIROC chips

Michel Bouchel, Stéphane Callier, Frédéric Dulucq, Julien Fleury, Gisèle Martin-Chassard, Christophe de La Taille, Ludovic Raux

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Engineering run

• Reticle size : 18x25 mm2– 50-55 reticles/Wafer– 25 wafers needed

• Final arrangement:– « Calice » chips produced:

• 7 Hardroc 2b => ~9000 chips• 1 Spiroc 2a => ~1200 chips• 1 Spiroc 2b => ~1200 chips• 1 Skiroc 2 => ~1200 chips

– Additionnal chips produced:• 1 Spaciroc : JEM EUSO experiement• 1 Maroc 3 : for PMT readout• 3 Spiroc 0 (SPIROC « light » version)=> cost reduction for CALICE

• Production run launched in March

• Wafers sent to packaging last week

• Chips delivery expected => end of July

SPIROCAnalog HCAL(SiPM)36 ch. 32mm²June 07

HARDROCDigital HCAL(RPC, µmegas or GEMs)64 ch. 16mm²Sept 06

SKIROCECAL(Si PIN diode)36 ch. 20mm²Nov 06

E-CAL

H-CAL

(analog or digital)

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SPIROC status

• SPIROC Status :– March 2010 dedicated production run: 2 SPIROC prototypes

are submitted:• A conservative prototype (SPIROC 2a) in which the major bugs of

SPIROC 2 are fixed• A more agressive prototype (SPIROC 2b) in which the major bugs

of SPIROC 2 are also fixed and some interesting improvements are added

Fabricated in SiGe AMS 0.35 µmChip area: 30 mm² (4.2mm × 7.2mm)

Packaging : TQFP 20836-channel ASIC

Charge measurement Time measurement

Autotrigger on MIP or spePower consumption : 25 µW/channel

(in power pulsing mode)

• Packaging: TQFP 208 (made by US company I2A)

Dimensions:28x28x1.4 mm

• NB: SPIROC 2a and 2b pin to pin compatible with the previous version except for the following pins:– A NC pin becomes the OR36 output (SPIROC2a and SPIROC2b)

– The pin “pw_on_sca” and pin “pw_on_dac” have merged to liberate a pin for LVDS trig_ext signal (SPIROC2b)

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Packaging

Measurement on Spiroc 2

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• Setup: Different charges injected in channel 0, full autotrigger mode, plot obtained on column 10 (High gain)Cf=200fF, τ=50ns•Analogue memories are converted twice by forcing the « flag_tdc_ext » signal•Problem during conversion phase

Measurement on Spiroc 2

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• Setup: Different charges injected in channel 0, full autotrigger mode, plot obtained on column 10 (High gain)Cf=200fF, τ=50ns

•Gate added with « val_evt » signal

To be investigated

Measurements on Spiroc 2

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•Setup : Different charges injected in channel 0, full autotrigger mode, plot obtained on each analogue memory

• Gate added with « val_evt » signal during acquisition phase

Pedestal stability issue

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Without a « gate » in acquisition phase

With a « gate » in acquisition phase

• Setup: Different charges injected in channel 0, full autotrigger mode, plot obtained on an other channel

Pedestal shift disappears

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Conclusion

• Last March 2010 : PRODUCTION RUN

• Schedule: Delivery expected =>next summer– Wafers by end May 2010– Chips expected in July 2010

• SPIROC 2a chip :– Conservative prototype : major bugs fixed

• SPIROC 2b chip :– Innovative prototype with « controlled » improvements also

submitted

• Both chips (almost) pin to pin compatible with Spiroc 2

• Measurements in collaboration with DESY group to be continued

• Some problems have to be investigated

Backup slides

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Backup slides

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SPIROC 2a : modifications and improvements (1/3)

• Conservative version of SPIROC 2:

– fix the slow control and probe bus :

• By adding buffers in critical points as done in HARDROC2B

• By correcting the Bug on the reset signal of the multiplexed probe and slow control register

» Active low reset forced to 0 when not selected

» Intempestive reset when register is unselected

• By putting a default Slow control set-up

S elec t

D atao utp ut

S lo wc o ntro l

P ro b e

S lo wc o ntro l

P ro b e

S elec t

D atainp ut

Resetb output

Resetb input

Replace the pull down by a pull up resistance

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SPIROC 2a : modifications and improvements (2/3)

• Conservative version of SPIROC 2:

– add the POD module for the 2 clock LVDS receivers to reduce idle power dissipation (already tested on Hardroc2)

LV D SR ec eiver

Enab le C lo c kfo r A c q uis itio n and

C o nvers io n

C lk O ut

P o w e rO nD ig ita l

S ta rtR e a dO ut

E ndR e a dO ut

S ta rtR e a dO utInt

S ta rtLV D S

C lk in

Enab le C lo c kfo r

R ead o utR s tb

C lk in

C lk O ut

P O D m o dule

E na ble

E na ble C lo c k

S ta r tC onv_ b

S ta r tA c qt

S ta r tR e a d-O ut

C hip_ S a t

E ndR e a d_ O ut

A c q u is it io n C o n v e rs io n R e ad -O u t

R e s e tb

P ow e rO nD igita l

Clo

ckSt

art

Clo

ckSt

art

C alib rate d(L V D S s tart t im e )

F ro m D A Q

F ro m d ais y c h ain

F ro m A S IC

G e ne ra te dS R O

F ro m P O D

Clo

ck S

topp

ed

Clo

ck S

topp

ed

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SPIROC 2a : modifications and improvements (3/3)

• Conservative version of SPIROC 2:

– Put a OR36 output on a non selected pin

– Decrease the consumption of the low gain preamplifier

– The backup SCA is OFF when unused in order to save power

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SPIROC 2b: modifications and improvements (1/2)

• SPIROC 2a + the following improvements:– 6-bit Preamplifier gain adjustment per channel (25fF, 50fF, 100fF, 200fF,

400fF, 800fF) : each preamp gain can vary from 25fF to 1.5pF with a step of 25fF)

– External trigger input (LVDS)

– put the improved version of 8-bit input DAC with new spatial arrangement for a better matching

individualMask (SC)

Val_evt

discri

Sel_trig_int (SC)

Sel_trig_ext (SC)

Out_trigger

Trig_ext

individualMask (SC)

Val_evt

discri

Sel_trig_int (SC)

Sel_trig_ext (SC)

Out_trigger

individualMask (SC)

Val_evt

discri

Sel_trig_int (SC)

Sel_trig_ext (SC)

Out_trigger

Trig_ext

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SPIROC 2b: modifications and improvements (2/2)

• SPIROC 2a + the following improvements:

– put the improved version of threshold 10-bit DAC

– fix the first "zero-frame" by adding an active pull-up to reference voltage on ADC discri input ( Not implemented as expected on SPIROC 2a because the risk would be too high)

ADC discri

Vref ssh

SCA

-

+ADC ramp

OTA

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Future SPIROC 3

• SPIROC 2a + SPIROC 2b + the following improvements:

– New TDC to have 100 ps accuracy (just submitted last November on PARISROC 2 Chip)

– Replace the ADC ramp by an optimized one

– Replace the ADC discriminators by an improved one (PARISROC)

– 8-bit input DAC : auto-regulation with respect to detector temperature

– “Powering-up mode” of SCA columns to save power:• SCA columns are powered only when they are used

– New improved and optimized digital part

– Possibly Wei's input stage after testing

– Possibly new I2C slow control interface