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Circuit Modeling and Fabrication Guided by CoolSPICE Brendan Cusack Z. Dilli, M. Gross, A. Akturk, N. Goldsman, J. McGarrity Research supported by ARL and NASA

Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

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Page 1: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

Circuit Modeling and Fabrication Guided by CoolSPICE

Brendan CusackZ. Dilli, M. Gross, A. Akturk,N. Goldsman, J. McGarrity

Research supported by ARL and NASA

Page 2: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

CoolSPICE Assisted Circuit Design and Fabrication

1. Device Simulation

2. Process Design/Device Fabrication

3. Device Characterization and Model Development

4. Circuit Design and Fabrication

5. Circuit Characterization

Page 3: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

Step 1: Device Simulation of MOSFET using CoolSPICE

SD

G B

VS1Enable=YVdc=3Vac=

VS2Enable=Y

Vdc=5Vac= Imeter1

GND

• Initial simulation performed using device simulator integrated into CoolSPICE

• Use drift-diffusion model and Poisson Equation to determine:

• Potential• Electron/Hole concentration• Electron/Hole current density

• Determination of internal characteristics and terminal currents given Vg, Vs, Vd, Vb

• Device Simulation provides:• Epi-layer doping• Source/Drain/Body implant • Gate oxide thickness

Page 4: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

Step 2: CoolCADMOSFET Fabrication

• Process Design Kit Developed

• Devices are fabricated using University of Maryland NanoFabcenter and in-house facilities

Page 5: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

Step 2: Process Development & Optimization

Process Control– Implantation– Activation– Oxidation – POA– Contact Formation– Metallization

Page 6: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

Step 3: Device Characterization and Model Development with CoolSPICE:

CoolCAD SiC MOS Process

TCAD Device SimulationExperimetal Data

CoolSpiceExperimetal Data

TCAD Simulation and Data CoolSPICE Model and Data

Page 7: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

Step 4: Silicon Carbide OpAmp:Design and Simulation with CoolSpice

VSin1

Amplitude=0.1Frequency=1k

Transient Run Enable=YTime Step=0.01mEnd Time=10mStart Time=0Max Step=0.01m

SD

G BN1AuMOS_20nm

W=21uL=10u

SD

GBN2AuMOS_20nm

W=21uL=10u

SD

G BN3AuMOS_20nm

W=40uL=10u

R2Value=500k

VS1Enable=YVdc=5Vac=

VS3Enable=YVdc=2Vac=

GND

VS2Enable=YVdc=5.0Vac=

R3Value=100k

SD

G BN4AuMOS_20nm

W=40uL=10u

SD

G BN5AuMOS_20nm

W=40uL=10u

R4Value=200k

Vmeter3

.op=-9.23e-001

SD

G BN6AuMOS_20nm

W=40uL=10u

R5Value=150k

V

.op=1.27e

CV

R1Val

R6Val

Page 8: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

Step 4: Circuit Simulation Results Input vs. Output

CoolSPICE graphical output of circuit design on previous slide

Page 9: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

Step 5: CoolCAD Chip Design and Layout

Finalized Layout, Masks Development, Chip in Process (estimated completion in 2 months)

Page 10: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

CoolSPICE: Make Your SiC Circuits “Great Again”

• CoolSPICE facilitates SiC circuit design and fabrication– PDK Development:

• DRC, LVS, SPICE Models– Identify key device parameters for:

• Process optimization• Circuit optimization

• Develop circuits for SiC power electronics– Gate Drivers– Power Converters

Page 11: Integrated Fabrication and Modeling with CoolSpiceneil/SiC_Workshop/Presentations_2016... · 2017-02-14 · 4. Circuit Design and ... Vdc=3 Vac= VS2 Enable=Y Vdc=5 Vac= Imeter1 GND

Thank you• CoolSpiceSim.com• CoolCADElectronics.com